FCP110N65F

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This literature is subject to all applicable copyright laws and is not for resale in any manner. FCP110N65F N 沟道 SuperFET® II FRFET® MOSFET 650 V, 35 A, 110 mΩ 特性 描述 • 700 V @ TJ = 150°C SuperFET® II MOSFET 是飞兆半导体利用电荷平衡技术实现出 色的低导通电阻和更低栅极电荷性能的全新高压超级结 (SJ)MOSFET 系列产品。这项技术专用于最小化导通损耗并提供 卓越的开关性能、dv/dt 额定值和更高雪崩能量。因此，SuperFET II MOSFET 非常适合开关电源应用，如功率因数校正 (PFC)、服 务器 / 电信电源、平板电视电源、 ATX 电源及工业电源应用。 SuperFET II FRFET® MOSFET 优化体二极管的反向恢复性能可 去除额外元件，提高系统可靠性。 • 典型值 RDS(on) = 96 mΩ （典型值） • 超低栅极电荷 （典型值 Qg= 98 nC） • 低有效输出电容 （典型值 Coss(eff.)= 464 pF) • 100% 经过雪崩测试 • 符合 RoHS 标准 应用 • LCD / LED / PDP TV • 通信 / 服务器电源 • 太阳能逆变器 • AC-DC 电源 D GD S G TO-220 S 绝对最大额定值 TC = 25°C 除非另有说明。 符号 FCP110N65F 650 参数 VDSS 漏极－源极电压 VGSS 栅极－源极电压 ID 漏极电流 - 连续 (TC = 25°C) 35 - 连续 (TC = 100°C) 24 - 脉冲 - DC ±20 - AC (f > 1 Hz) ±30 单位 V V A IDM 漏极电流 （注 1） 105 A EAS 单脉冲雪崩能量 （注 2） 809 mJ IAR 雪崩电流 （注 1） 8 A EAR 重复雪崩能量 MOSFET dv/dt （注 1） 3.57 mJ 二极管恢复 dv/dt 峰值 （注 3） dv/dt PD 功耗 TJ, TSTG 工作和存储温度范围 用于焊接的最高引脚温度， 距离外壳 1/8”，持续 5 秒 TL 100 50 V/ns (TC = 25°C) 357 W - 高于 25°C 的功耗系数 2.86 W/°C -55 至 +150 °C 300 °C FCP110N65F 单位 热性能 符号 参数 RθJC 结至外壳热阻最大值 0.35 RθJA 结至环境热阻最大值 62.5 © 2014 飞兆半导体公司 FCP110N65F Rev. C0 1 °C/W www.fairchildsemi.com FCP110N65F — N 沟道 SuperFET® II FRFET® MOSFET 2014 年 10 月 器件编号 FCP110N65F 顶标 FCP110N65F 封装 TO-220 包装方法 塑料管 卷尺寸 N/A 带宽 N/A 数量 50 个 电气特性 TC = 25°C 除非另有说明。 符号 参数 测试条件 最小值 典型值 最大值 单位 关断特性 BVDSS 漏极－源极击穿电压 ΔBVDSS / ΔTJ 击穿电压温度系数 IDSS 零栅极电压漏极电流 IGSS VGS = 0 V, ID = 10 mA, TJ = 25°C 650 - - VGS = 0 V, ID = 10 mA, TJ = 150°C 700 - - - 0.67 - ID = 10 mA，参考 25°C 数值 V V/°C VDS = 650 V, VGS = 0 V - - 10 VDS = 520 V, TC = 125°C - 110 - 栅极－体漏电流 VGS = ±20 V, VDS = 0 V - - ±100 VGS(th) RDS(on) 栅极阈值电压 VGS = VDS, ID = 3.5 mA 3 - 5 V 漏极至源极静态导通电阻 VGS = 10 V, ID = 17.5 A - 96 110 mΩ gFS 正向跨导 VDS = 20 V, ID = 17.5 A - 30 - S VDS = 100 V, VGS = 0 V, f = 1 MHz - 3680 4895 pF - 110 145 pF - 0.65 - pF μA nA 导通特性 动态特性 Ciss 输入电容 Coss 输出电容 Crss 反向传输电容 Coss 输出电容 VDS = 380 V, VGS = 0 V, f = 1 MHz - 65 - pF Coss(eff.) 有效输出电容 VDS = 0 V 至 400 V, VGS = 0 V - 464 - pF Qg(tot) 10 V 的栅极电荷总量 98 145 nC 栅极－源极栅极电荷 VDS = 380 V, ID = 17.5 A, VGS = 10 V - Qgs - 20 - nC Qgd 栅极－漏极 “ 米勒 ” 电荷 - 43 - nC ESR 等效串联电阻 - 0.7 - Ω - 31 72 ns - 21 52 ns - 89 188 ns - 5.7 21 ns （注 4） f = 1 MHz 开关特性 td(on) 导通延迟时间 tr 导通上升时间 td(off) 关断延迟时间 tf 关断下降时间 VDD = 380 V, ID = 17.5 A, VGS = 10 V, Rg = 4.7 Ω （注 4） 漏极 - 源极二极管特性 IS 漏极－源极二极管最大正向连续电流 - - 35 A ISM 漏极－源极二极管最大正向脉冲电流 - - 105 A VSD 漏极－源极二极管正向电压 VGS = 0 V, ISD = 17.5 A - - 1.2 V trr 反向恢复时间 - 133 - ns Qrr 反向恢复电荷 VGS = 0 V, ISD = 17.5 A, dIF/dt = 100 A/μs - 0.67 - μC 注： 1. 重复额定值：脉冲宽度受限于最大结温。 2. IAS = 8 A, RG = 25 Ω, 开始于 TJ = 25°C。 3. ISD ≤ 17.5 A, di/dt ≤ 200 A/μs, VDD ≤ 380 V, 开始于 TJ = 25°C。 4. 典型特性本质上独立于工作温度。 © 2014 飞兆半导体公司 FCP110N65F Rev. C0 2 www.fairchildsemi.com FCP110N65F — N 沟道 SuperFET® II FRFET® MOSFET 封装标识与定购信息 图 1. 导通区域特性 图 2. 传输特性 200 VGS = 10.0V 8.0V 100 7.0V 6.5V 6.0V 5.5V *Notes: 1. VDS = 20V 2. 250μs Pulse Test 100 ID, Drain Current[A] ID, Drain Current[A] 200 10 o 150 C 10 o 25 C *Notes: 1. 250μs Pulse Test o -55 C o 2. TC = 25 C 1 0.3 1 10 VDS, Drain-Source Voltage[V] 1 20 图 3. 导通电阻变化与漏极电流和栅极电压的关系 4 5 6 7 VGS, Gate-Source Voltage[V] IS, Reverse Drain Current [A] 200 100 0.20 0.15 VGS = 10V 0.10 VGS = 20V 10 o 150 C 1 o 25 C 0.1 0.01 *Notes: 1. VGS = 0V o *Note: TC = 25 C 0.05 0 20 40 60 ID, Drain Current [A] 80 0.001 0.0 100 图 5. 电容特性 10 VGS, Gate-Source Voltage [V] Capacitances [pF] 10000 Ciss 1000 Coss 100 *Note: 1. VGS = 0V 2. f = 1MHz 10 Crss Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 0.1 0.1 © 2014 飞兆半导体公司 FCP110N65F Rev. C0 2. 250μs Pulse Test 0.3 0.6 0.9 1.2 1.5 VSD, Body Diode Forward Voltage [V] 1.8 图 6. 栅极电荷特性 100000 1 8 图 4. 体二极管正向电压变化与源极电流和温度的关系 0.25 RDS(ON) [Ω], Drain-Source On-Resistance 3 1 10 100 VDS, Drain-Source Voltage [V] VDS = 130V 8 3 VDS = 325V VDS = 520V 6 4 2 0 660 *Note: ID = 17.5A 0 20 40 60 80 Qg, Total Gate Charge [nC] 100 www.fairchildsemi.com FCP110N65F — N 沟道 SuperFET® II FRFET® MOSFET 典型性能特征 图 7. 击穿电压变化与温度的关系 图 8. 导通电阻变化与温度的关系 2.5 1.10 *Notes: 1. VGS = 0V 2. ID = 10mA RDS(on), [Normalized] Drain-Source On-Resistance BVDSS, [Normalized] Drain-Source Breakdown Voltage 1.15 1.05 1.00 0.95 0.90 -100 -50 0 50 100 150 o TJ, Junction Temperature [ C] 2.0 1.5 1.0 0.5 -100 200 图 9. 最大安全工作区 -50 0 50 100 150 o TJ, Junction Temperature [ C] 200 图 10. 最大漏极电流与壳温的关系 40 300 100 10μs 100μs 10 ID, Drain Current [A] ID, Drain Current [A] *Notes: 1. VGS = 10V 2. ID = 17.5A 1ms DC 1 Operation in This Area is Limited by R DS(on) *Notes: o 1. TC = 25 C 0.1 30 20 10 o 2. TJ = 150 C 3. Single Pulse 0.01 0.1 1 10 100 VDS, Drain-Source Voltage [V] 0 25 1000 50 75 100 125 o TC, Case Temperature [ C] 150 图 11. Eoss 与漏源极电压的关系 20 EOSS, [μJ] 16 12 8 4 0 0 © 2014 飞兆半导体公司 FCP110N65F Rev. C0 132 264 396 528 VDS, Drain to Source Voltage [V] 660 4 www.fairchildsemi.com FCP110N65F — N 沟道 SuperFET® II FRFET® MOSFET 典型性能特性 （接上页） FCP110N65F — N 沟道 SuperFET® II FRFET® MOSFET 典型性能特性 （接上页） 图 12. 瞬态热响应曲线 o ZθJC(t), Thermal Response [ C/W] 1 0.5 0.1 0.2 t1 0.01 0.02 t2 *Notes: 0.01 o 1. ZθJC(t) = 0.35 C/W Max. 2. Duty Factor, D= t1/t2 3. TJM - TC = PDM * ZθJC(t) Single pulse 0.001 -5 10 © 2014 飞兆半导体公司 FCP110N65F Rev. C0 PDM 0.1 0.05 -4 10 -3 -2 10 10 t1, Rectangular Pulse Duration [sec] 5 -1 10 1 www.fairchildsemi.com FCP110N65F — N 沟道 SuperFET® II FRFET® MOSFET IG = 常量 图 13. 栅极电荷测试电路与波形 VDS RG V 10V GS RL VDS 90% VDD VGS VGS DUT 10% td(on) tr t on td(off) tf t off 图 14. 阻性开关测试电路与波形 VGS 图 15. 非箝位电感开关测试电路与波形 © 2014 飞兆半导体公司 FCP110N65F Rev. C0 6 www.fairchildsemi.com FCP110N65F — N 沟道 SuperFET® II FRFET® MOSFET DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop 图 16. 二极管恢复 dv/dt 峰值测试电路与波形 © 2014 飞兆半导体公司 FCP110N65F Rev. C0 7 www.fairchildsemi.com SUPPLIER "B" PACKAGE SHAPE 3.50 10.67 9.65 E SUPPLIER "A" PACKAGE SHAPE 3.40 2.50 16.30 13.90 IF PRESENT, SEE NOTE "D" 16.51 15.42 E 9.40 8.13 E 1 [2.46] 2 3 C 4.10 2.70 14.04 12.70 2.13 2.06 FRONT VIEWS 4.70 4.00 1.62 H 1.42 "A1" 8.65 7.59 SEE NOTE "F" 1.62 1.10 2.67 2.40 1.00 0.55 6.69 6.06 OPTIONAL CHAMFER E 14.30 11.50 NOTE "I" BOTTOM VIEW 3 0.60 0.36 SIDE VIEW 2.85 2.10 2 1 BACK VIEW NOTES: A) REFERENCE JEDEC, TO-220, VARIATION AB B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS COMMON TO ALL PACKAGE SUPPLIERS EXCEPT WHERE NOTED [ ]. D) LOCATION OF MOLDED FEATURE MAY VARY (LOWER LEFT CORNER, LOWER CENTER AND CENTER OF THE PACKAGE) E DOES NOT COMPLY JEDEC STANDARD VALUE. F) "A1" DIMENSIONS AS BELOW: SINGLE GAUGE = 0.51 - 0.61 DUAL GAUGE = 1.10 - 1.45 G) DRAWING FILE NAME: TO220B03REV9 H PRESENCE IS SUPPLIER DEPENDENT I) SUPPLIER DEPENDENT MOLD LOCKING HOLES IN HEATSINK. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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