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or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
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for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
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N-Channel PowerTrench® MOSFET
60 V, 80 A, 3.5 mΩ
Features
• RDS(on) = 3.2 mΩ ( Typ.) @ VGS = 10 V, ID = 80 A
Applications
• QG(tot) = 95 nC ( Typ.) @ VGS = 10 V
• Synchronous Rectification for ATX / Server / Telecom PSU
• Low Miller Charge
• Battery Protection Circuit
• Low Qrr Body Diode
• Motor drives and Uninterruptible Power Supplies
• UIS Capability (Single Pulse and Repetitive Pulse)
Formerly developmental type 82584
D
D
G
G
D2-PAK
S
S
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
VGS
Drain to Source Voltage
FDB035AN06A0
60
Unit
V
Gate to Source Voltage
±20
V
80
A
22
A
Parameterr
Drain Current
ID
Continuous (TC < 153oC, VGS = 10V)
o
o
Continuous (Tamb = 25 C, VGS = 10V, with RθJA = 43 C/W)
Pulsed
E AS
PD
TJ, TSTG
Single Pulse Avalanche Energy (Note 1)
Power dissipation
Figure 4
A
625
mJ
310
Derate above 25oC
Operating and Storage Temperature
W
2.07
W/oC
-55 to 175
C
o
Thermal Characteristics
RθJC
Thermal Resistance, Junction to Case, Max.
RθJA
Thermal Resistance, Junction to Ambient, Max. (Note 2)
RθJA
Thermal Resistance, Junction to Ambient, 1in copper pad area, Max.
©2002 Semiconductor Components Industries, LLC.
September-2017,Rev.3
0.48
2
oC/W
62
o
C/W
43
o
C/W
Publication Order Number:
FDB035AN06A0/D
FDB035AN06A0 — N-Channel PowerTrench® MOSFET
FDB035AN06A0
Device Marking
FDB035AN06A0
Device
FDB035AN06A0
Package
D2-PAK
Reel Size
330 mm
Tape Width
24 mm
Quantity
800 units
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
V
Off Characteristics
B VDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
60
-
-
-
-
1
-
-
250
VGS = ±20V
-
-
±100
nA
VGS = VDS, ID = 250µA
2
-
4
V
ID = 40A, VGS = 6V
V DS = 50V
VGS = 0V
TC = 150oC
µA
On Characteristics
VGS(TH)
Gate to Source Threshold Voltage
rDS(ON)
Drain to Source On Resistance
ID = 80A, VGS = 10V
-
0.0032 0.0035
-
0.0044 0.0066
ID = 80A, VGS = 10V,
TJ = 175oC
-
0.0065 0.0071
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
V DS = 25V, VGS = 0V,
f = 1MHz
Qg(TOT)
Total Gate Charge at 10V
VGS = 0V to 10V
Qg(TH)
Threshold Gate Charge
VGS = 0V to 2V
Qgs
Gate to Source Gate Charge
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
VDD = 30V
ID = 80A
Ig = 1.0mA
-
6400
-
-
1123
-
pF
pF
-
367
-
pF
95
124
nC
-
12
15
nC
-
30
-
nC
-
18
-
nC
-
24
-
nC
Switching Characteristics (VGS = 10V)
Turn-On Time
-
-
163
ns
td(ON)
Turn-On Delay Time
-
15
-
ns
td(OFF)
Turn-Off Delay Time
tOFF
tON
tr
Rise Time
tf
-
93
-
ns
-
38
-
ns
Fall Time
-
13
-
ns
Turn-Off Time
-
-
75
ns
V DD = 30V, ID = 80A
V GS = 10V, RGS = 2.4Ω
Drain-Source Diode Characteristics
ISD = 80A
-
-
1.25
V
ISD = 40A
-
-
1.0
V
Reverse Recovery Time
ISD = 75A, dISD/dt = 100A/µs
-
-
38
ns
Reverse Recovered Charge
ISD = 75A, dISD/dt = 100A/µs
-
-
39
nC
V SD
Source to Drain Diode Voltage
trr
QRR
Notes:
1: Starting TJ = 25°C, L = 0.255mH, IAS = 70A.
2: Pulse Width = 100s
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2
FDB035AN06A0 — N-Channel PowerTrench® MOSFET
Package Marking and Ordering Information
1.2
250
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
150
125
150
100
50
0
25
175
CURRENT LIMITED
BY PACKAGE
200
50
75
TC , CASE TEMPERATURE (o C)
150
175
TC, CASE TEMPERATURE ( C)
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
1
ZθJC, NORMALIZED
THERMAL IMPEDANCE
125
o
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
2
100
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
3000
1000
IDM, PEAK CURRENT (A)
TC = 25oC
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - TC
I = I25
150
VGS = 10V
100
10
10-5
10-4
10-3
10-2
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
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3
10-1
100
101
FDB035AN06A0 — N-Channel PowerTrench® MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
2000
100
10µs
1000
100
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10
10ms
1
DC
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
0.1
1
10
STARTING TJ = 25oC
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
100µs
STARTING TJ = 150oC
10
If R = 0
tAV = (L)(I AS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
1
0.01
100
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Forward Bias Safe Operating Area
100
NOTE: Refer to ON Semiconductor Application Notes AN7514
and AN7515
Figure 6. Unclamped Inductive Switching
Capability
160
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
120
80
ID, DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
160
TJ = 175 oC
TJ = 25o C
40
VGS = 20V
120
VGS = 6V
40
3.5
4.0
4.5
5.0
5.5
VGS , GATE TO SOURCE VOLTAGE (V)
6
0
Figure 7. Transfer Characteristics
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 6V
4
VGS = 10V
3
0
20
40
60
TC = 25o C
0.5
1.0
VDS , DRAIN TO SOURCE VOLTAGE (V)
1.5
Figure 8. Saturation Characteristics
2.5
5
DRAIN TO SOURCE ON RESISTANCE(mΩ)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
3.0
VGS = 5V
80
TJ = -55 oC
0
VGS = 10V
80
2.0
1.5
1.0
0.5
-80
ID, DRAIN CURRENT (A)
Figure 9. Drain to Source On Resistance vs Drain
Current
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID =80A
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
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4
200
FDB035AN06A0 — N-Channel PowerTrench® MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
1.4
1.2
VGS = VDS, I D = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
1.2
1.0
0.8
0.6
0.4
0.2
-80
-40
0
40
80
120
160
1.1
1.0
0.9
200
ID = 250µA
o
-80
-40
TJ, JUNCTION TEMPERATURE ( C)
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
10000
VGS , GATE TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
CISS = CGS + CGD
1000
100
CRSS = CGD
VGS = 0V, f = 1MHz
0.1
1
40
80
120
160
200
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
10
COSS ≅ C DS + C GD
0
TJ , JUNCTION TEMPERATURE (o C)
VDD = 30V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 80A
ID = 40A
2
0
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 13. Capacitance vs Drain to Source
Voltage
60
0
25
50
Qg , GATE CHARGE (nC)
75
100
Figure 14. Gate Charge Waveforms for Constant
Gate Current
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5
FDB035AN06A0 — N-Channel PowerTrench® MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
VDS
BVDSS
tP
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
-
VGS
VDS
IAS
VDD
VDD
DUT
tP
0V
IAS
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT)
VDS
L
VGS
+
-
VGS
VGS = 10V
Qgs2
VDD
DUT
VGS = 2V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tr
VDS
90%
90%
+
VGS
RGS
tf
VDD
10%
0
10%
DUT
90%
VGS
VGS
0
Figure 19. Switching Time Test Circuit
50%
10%
PULSE WIDTH
50%
Figure 20. Switching Time Waveforms
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6
FDB035AN06A0 — N-Channel PowerTrench® MOSFET
Test Circuits and Waveforms
(T
–T )
JM
A
P D M = ----------------------------R θ JA
(EQ. 1)
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P DM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
80
RθJA = 26.51+ 19.84/(0.262+Area) EQ.2
RθJA = 26.51+ 128/(1.69+Area) EQ.3
60
RθJA (o C/W)
The maximum rated junction temperature, TJM , and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM , in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
40
20
0.1
1
10
(0.645)
(6.45)
AREA, TOP COPPER AREA in2 (cm2 )
(64.5)
Figure 21. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
ON Semiconductor provides thermal information to
assist the designer’s preliminary application evaluation.
Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds of
steady state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the ON
Semiconductor device Spice thermal model or manually
utilizing the normalized maximum transient thermal
impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area
defined in inches square and equation 3 is for area in
centimeters square. The area, in square inches or square
centimeters is the top copper area including the gate and
source pads.
R
θ JA
19.84
( 0.262 + Area )
= 26.51 + -------------------------------------
(EQ. 2)
Area in Inches Squared
R
θ JA
128
( 1.69 + Area )
= 26.51 + ----------------------------------
(EQ. 3)
Area in Centimeters Squared
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7
FDB035AN06A0 — N-Channel PowerTrench® MOSFET
Thermal Resistance vs. Mounting Pad Area
.SUBCKT FDB035AN06A0 2 1 3 ; rev July 04, 2002
Ca 12 8 1.5e-9
Cb 15 14 1.5e-9
Cin 6 8 6.1e-9
DPLCAP
10
RSLC2
Lgate 1 9 4.81e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 4.63e-9
ESG
+
GATE
1
LGATE
RLGATE
DBREAK
ESLC
11
50
RDRAIN
6
8
EVTEMP
RGATE + 18 22
9
20
EVTHRES
+ 19 8
6
21
EBREAK
16
+
17
18
-
DBODY
MWEAK
MMED
MSTRO
CIN
LSOURCE
8
7
RSOURCE
RLgate 1 9 48.1
RLdrain 2 5 10
RLsource 3 7 46.3
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
5
51
-
Ebreak 11 7 17 18 69.3
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
12
S1A
CA
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 1e-4
Rgate 9 20 1.36
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 2.5e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
S2A
13
8
S1B
DRAIN
2
RLDRAIN
RSLC1
51
+
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
It 8 17 1
LDRAIN
5
15
14
13
17
RBREAK
CB
+
EGS
-
18
EDS
-
19
VBAT
+
IT
14
+
6
8
RLSOURCE
RVTEMP
S2B
13
SOURCE
3
5
8
8
RVTHRES
22
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),10))}
.MODEL DbodyMOD D (IS=2.4E-11 N=1.04 RS=1.65e-3 TRS1=2.7e-3 TRS2=2e-7
+ CJO=4.35e-9 M=5.4e-1 TT=1e-9 XTI=3.9)
.MODEL DbreakMOD D (RS=1.5e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=1.7e-9 IS=1e-30 N=10 M=0.47)
.MODEL MmedMOD NMOS (VTO=3.3 KP=9 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.36 T_abs=25)
.MODEL MstroMOD NMOS (VTO=4.00 KP=275 IS=1e-30 N=10 TOX=1 L=1u W=1u T_abs=25)
.MODEL MweakMOD NMOS (VTO=2.72 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=13.6 RS=0.1 T_abs=25)
.MODEL RbreakMOD RES (TC1=9e-4 TC2=-9e-7)
.MODEL RdrainMOD RES (TC1=4e-2 TC2=1.75e-4)
.MODEL RSLCMOD RES (TC1=1e-3 TC2=1e-5)
.MODEL RsourceMOD RES (TC1=5e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-6.7e-3 TC2=-1.5e-5)
.MODEL RvtempMOD RES (TC1=-2.5e-3 TC2=1e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-1.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1).
ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
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8
FDB035AN06A0 — N-Channel PowerTrench® MOSFET
PSPICE Electrical Model
rev July 4, 2002
template FDB035AN06A0 n2,n1,n3 = m_temp
electrical n2,n1,n3
number m_temp=25
{
var i iscl
dp..model dbodymod = (isl=2.4e-11,nl=1.04,rs=1.65e-3,trs1=2.7e-3,trs2=2e-7,cjo=4.35e-9,m=5.4e-1,tt=1e-9,xti=3.9)
dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=1.7e-9,isl=10e-30,nl=10,m=0.47)
m..model mmedmod = (type=_n,vto=3.3,kp=9,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.00,kp=275,is=1e-30, tox=1)
LDRAIN
m..model mweakmod = (type=_n,vto=2.72,kp=0.03,is=1e-30, tox=1,rs=0.1DP
) LCAP 5
DRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-1.5)
2
10
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-4)
RLDRAIN
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1,voff=0.5)
RSLC1
51
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1)
RSLC2
c.ca n12 n8 = 1.5e-9
ISCL
c.cb n15 n14 = 1.5e-9
c.cin n6 n8 = 6.1e-9
DBREAK
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 69.3
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
GATE
1
ESG
+
LGATE
RLGATE
EVTEMP
RGATE + 18 22
9
20
res.rlgate n1 n9 = 48.1
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 46.3
EVTHRES
+ 19 8
6
21
11
DBODY
16
MWEAK
EBREAK
+
17
18
-
MMED
MSTRO
CIN
8
LSOURCE
7
RSOURCE
i.it n8 n17 = 1
l.lgate n1 n9 = 4.81e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 4.63e-9
RDRAIN
6
8
12
14
13
13
8
S1B
CA
S2A
S1A
15
17
RBREAK
RLSOURCE
18
RVTEMP
S2B
13
CB
EGS
-
6
8
EDS
-
-
5
8
m.mmed n16 n6 n8 n8 = model=mmedmod, temp=m_temp, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, temp=m_temp, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, temp=m_temp, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=9e-4,tc2=-9e-7
res.rdrain n50 n16 = 1e-4, tc1=4e-2,tc2=1.75e-4
res.rgate n9 n20 = 1.36
res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=1e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2.5e-3, tc1=5e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-6.7e-3,tc2=-1.5e-5
res.rvtemp n18 n19 = 1, tc1=-2.5e-3,tc2=1e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10))
}
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9
IT
14
+
+
19
+
8
RVTHRES
22
VBAT
SOURCE
3
FDB035AN06A0 — N-Channel PowerTrench® MOSFET
SABER Electrical Model
th
REV 23 July 4, 2002
JUNCTION
FDB035AN06A0T
CTHERM1 TH 6 6.45e-3
CTHERM2 6 5 3e-2
CTHERM3 5 4 1.4e-2
CTHERM4 4 3 1.65e-2
CTHERM5 3 2 4.85e-2
CTHERM6 2 TL 1e-1
RTHERM1
CTHERM1
6
RTHERM1 TH 6 3.24e-3
RTHERM2 6 5 8.08e-3
RTHERM3 5 4 2.28e-2
RTHERM4 4 3 1e-1
RTHERM5 3 2 1.1e-1
RTHERM6 2 TL 1.4e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
RTHERM3
SABER thermal model FDB035AN06A0T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =6.45e-3
ctherm.ctherm2 6 5 =3e-2
ctherm.ctherm3 5 4 =1.4e-2
ctherm.ctherm4 4 3 =1.65e-2
ctherm.ctherm5 3 2 =4.85e-2
ctherm.ctherm6 2 tl =1e-1
CTHERM3
4
RTHERM4
rtherm.rtherm1 th 6 =3.24e-3
rtherm.rtherm2 6 5 =8.08e-3
rtherm.rtherm3 5 4 =2.28e-2
rtherm.rtherm4 4 3 =1e-1
rtherm.rtherm5 3 2 =1.1e-1
rtherm.rtherm6 2 tl=1.4e-1
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
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10
CASE
FDB035AN06A0 — N-Channel PowerTrench® MOSFET
SPICE Thermal Model
TO-263 2L (D2PAK)
Figure 22. 2LD, TO263, Surface Mount
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11
FDB035AN06A0 — N-Channel PowerTrench® MOSFET
Mechanical Dimensions
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