FDB050AN06A0

N-Channel PowerTrench® MOSFET 60 V, 80 A, 5 mΩ Features • RDS(on) = 4.3 mΩ ( Typ.) @ VGS = 10 V, ID = 80 A Applications • QG(tot) = 61 nC ( Typ.) @ VGS = 10 V • Synchronous Rectification for ATX / Server / Telecom PSU • Low Miller Charge • Battery Protection Circuit • Low Qrr Body Diode • Motor drives and Uninterruptible Power Supplies • UIS Capability (Single Pulse and Repetitive Pulse) Formerly developmental type 82575 D D GD S G TO-220 G D2-PAK S S MOSFET Maximum Ratings TC = 25°C unless otherwise noted Symbol Parameter FDP050AN06A0 FDB050AN06A0 Unit V DSS Drain to Source Voltage 60 V VGS Gate to Source Voltage ±20 V 80 A 18 A Drain Current ID Continuous (TC < 135oC, VGS = 10V) Continuous (TA = 25oC, VGS = 10V, R θJA = 43oC/W) Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy (Note 1) Power dissipation Figure 4 A 470 mJ 245 Derate above 25oC Operating and Storage Temperature W 1.63 W/oC -55 to 175 C o Thermal Characteristics RθJC Thermal Resistance Junction to Case, Max. TO-220, D2-PAK RθJA Thermal Resistance Junction to Ambient, Max. TO-220, D2-PAK (Note 2) RθJA Thermal Resistance Junction to Ambient ©2003 Semiconductor Components Industries, LLC. November-2017,Rev.3 D2-PAK, Max. 1in2 0.61 copper pad area oC/W 62 o C/W 43 o C/W Publication Order Number: FDP050AN06A0/D FDP050AN06A0 / FDB050AN06A0 — N-Channel PowerTrench® MOSFET FDP050AN06A0 / FDB050AN06A0 Device Marking FDB050AN06A0 Device FDB050AN06A0 Package D2-PAK Reel Size 330 mm Tape Width 24 mm Quantity 800 units FDP050AN06A0 FDP050AN06A0 TO-220 Tube N/A 50 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Unit V Off Characteristics B VDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V 60 - - - - 1 - - 250 VGS = ±20V - - ±100 nA VGS = VDS, ID = 250µA V ID = 40A, VGS = 6V V DS = 50V VGS = 0V TC = 150oC µA On Characteristics VGS(TH) Gate to Source Threshold Voltage rDS(ON) Drain to Source On Resistance 2 - 4 ID = 80A, VGS = 10V - 0.0043 0.005 - 0.007 0.011 ID = 80A, VGS = 10V, TJ = 175oC - 0.0085 0.010 - 3900 - - 750 - pF - 270 - pF nC Ω Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance V DS = 25V, VGS = 0V, f = 1MHz Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V Qg(TH) Threshold Gate Charge VGS = 0V to 2V Qgs Gate to Source Gate Charge Qgs2 Gate Charge Threshold to Plateau Qgd Gate to Drain “Miller” Charge VDD = 30V ID = 80A Ig = 1.0mA pF 61 80 - 8 11 nC - 24 - nC - 16 - nC - 15 - nC Switching Characteristics (VGS = 10V) tON Turn-On Time - - 264 ns Turn-On Delay Time - 16 - ns tr Rise Time - 160 - ns - 28 - ns tf td(ON) V DD = 30V, ID = 80A V GS = 10V, RGS = 4.3Ω td(OFF) Turn-Off Delay Time Fall Time - 29 - ns tOFF Turn-Off Time - - 86 ns Drain-Source Diode Characteristics ISD = 80A - - 1.25 V ISD = 40A - - 1.0 V Reverse Recovery Time ISD = 75A, dISD/dt = 100A/µs - - 34 ns Reverse Recovered Charge ISD = 75A, dISD/dt = 100A/µs - - 25 nC V SD Source to Drain Diode Voltage trr QRR Notes: 1: Starting TJ = 25°C, L = 229µH, IAS = 64A. 2: Pulse width = 100s. www.onsemi.com 2 FDP050AN06A0 / FDB050AN06A0 — N-Channel PowerTrench® MOSFET Package Marking and Ordering Information 1.2 160 CURRENT LIMITED BY PACKAGE ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 120 80 40 0.2 0 0 0 25 50 75 100 150 125 175 25 50 75 TC , CASE TEMPERATURE (o C) 100 125 TC, CASE TEMPERATURE Figure 1. Normalized Power Dissipation vs Ambient Temperature 150 175 (oC) Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t , RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 2000 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK IDM, PEAK CURRENT (A) 1000 CURRENT AS FOLLOWS: 175 - TC I = I25 VGS = 10V 150 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 100 50 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) Figure 4. Peak Current Capability www.onsemi.com 3 10-1 100 101 FDP050AN06A0 / FDB050AN06A0 — N-Channel PowerTrench® MOSFET Typical Characteristics TC = 25°C unless otherwise noted 1000 500 If R = 0 tAV = (L)(I AS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] IAS, AVALANCHE CURRENT (A) 10µs ID, DRAIN CURRENT (A) 100µs 100 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 10ms DC 1 SINGLE PULSE TJ = MAX RATED TC = 25oC 100 STARTING TJ = 25oC 10 STARTING TJ = 150 oC 1 0.01 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100 NOTE: Refer to ON Semiconductor Application Notes AN7514 and AN7515 Figure 5. Forward Bias Safe Operating Area Figure 6. Unclamped Inductive Switching Capability 160 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V VGS = 7V VGS = 10V 120 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 160 80 TJ = 175oC TJ = 25o C 40 VGS = 6V 120 80 VGS = 5V 40 TC = 25oC PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TJ = -55oC 0 0 4.0 4.5 5.0 5.5 VGS , GATE TO SOURCE VOLTAGE (V) 0 6.0 Figure 7. Transfer Characteristics 1.0 1.5 Figure 8. Saturation Characteristics 2.0 8 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 6V NORMALIZED DRAIN TO SOURCE ON RESISTANCE DRAIN TO SOURCE ON RESISTANCE(mΩ) 0.5 VDS , DRAIN TO SOURCE VOLTAGE (V) 7 6 5 VGS = 10V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 1.5 1.0 VGS = 10V, ID =80A 4 0 20 40 60 80 0.5 -80 ID, DRAIN CURRENT (A) Figure 9. Drain to Source On Resistance vs Drain Current -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature www.onsemi.com 4 200 FDP050AN06A0 / FDB050AN06A0 — N-Channel PowerTrench® MOSFET Typical Characteristics TC = 25°C unless otherwise noted 1.4 1.15 ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE 160 1.00 0.95 0.90 -80 200 10000 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 200 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10 VGS , GATE TO SOURCE VOLTAGE (V) CISS = CGS + CGD C, CAPACITANCE (pF) 1.05 (oC) Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature COSS ≅ CDS + CGD 1000 CRSS = CGD VGS = 0V, f = 1MHz 100 0.1 1.10 VDD = 30V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 80A ID = 18A 2 0 60 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 0 10 20 30 40 50 60 70 Qg, GATE CHARGE (nC) Figure 13. Capacitance vs Drain to Source Voltage Figure 14. Gate Charge Waveforms for Constant Gate Current www.onsemi.com 5 FDP050AN06A0 / FDB050AN06A0 — N-Channel PowerTrench® MOSFET Typical Characteristics TC = 25°C unless otherwise noted VDS BVDSS tP L VDS VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDD VDD - VGS DUT tP IAS 0V 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS VGS VGS = 10V + Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 18. Gate Charge Waveforms Figure 17. Gate Charge Test Circuit VDS tON tOFF td(ON) td(OFF) RL tr VDS tf 90% 90% + VGS VDD - 10% 0 10% DUT 90% RGS VGS VGS 0 Figure 19. Switching Time Test Circuit 50% 10% 50% PULSE WIDTH Figure 20. Switching Time Waveforms www.onsemi.com 6 FDP050AN06A0 / FDB050AN06A0 — N-Channel PowerTrench® MOSFET Test Circuits and Waveforms (T –T ) JM A P D M = ----------------------------R θ JA (EQ. 1) In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of P DM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 80 RθJA = 26.51+ 19.84/(0.262+Area) EQ.2 RθJA = 26.51+ 128/(1.69+Area) EQ.3 60 RθJA (o C/W) The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. 40 20 0.1 1 10 (0.645) (6.45) AREA, TOP COPPER AREA in2 (cm2 ) (64.5) Figure 21. Thermal Resistance vs Mounting Pad Area 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. ON Semiconductor provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the ON Semiconductor device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. R θ JA 19.84 ( 0.262 + Area ) = 26.51 + ------------------------------------- (EQ. 2) Area in Inches Squared R θ JA 128 ( 1.69 + Area ) = 26.51 + ---------------------------------- (EQ. 3) Area in Centimeters Squared www.onsemi.com 7 FDP050AN06A0 / FDB050AN06A0 — N-Channel PowerTrench® MOSFET Thermal Resistance vs. Mounting Pad Area .SUBCKT FDB050AN06A0 2 1 3 ; rev February 2003 Ca 12 8 1.5e-9 Cb 15 14 1.5e-9 Cin 6 8 3.75e-9 LDRAIN DPLCAP 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD RLDRAIN RSLC1 51 5 51 ESLC EVTHRES + 19 8 + LGATE GATE 1 11 50 RDRAIN 6 8 ESG DBREAK + RSLC2 Ebreak 11 7 17 18 64.8 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 DRAIN 2 5 EVTEMP RGATE + 18 22 9 20 21 EBREAK 16 + 17 18 - DBODY MWEAK 6 MMED MSTRO RLGATE Lgate 1 9 4.7e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 4.03e-9 LSOURCE CIN 8 7 SOURCE 3 RSOURCE RLSOURCE RLgate 1 9 47 RLdrain 2 5 10 RLsource 3 7 40 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD S1A 12 S2A 13 8 14 13 S1B CA 15 17 18 RVTEMP S2B 13 CB 6 8 5 8 EDS - 19 VBAT + IT 14 + + EGS Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 1.1e-3 Rgate 9 20 1.3 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 2.1e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD RBREAK - 8 22 RVTHRES Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),10))} .MODEL DbodyMOD D (IS=1.3E-11 N=1.04 RS=1.76e-3 TRS1=2.7e-3 TRS2=2e-7 + CJO=2.7e-9 M=5.4e-1 TT=1e-10 XTI=3.9) .MODEL DbreakMOD D (RS=8e-1 TRS1=5e-4 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=1.3e-9 IS=1e-30 N=10 M=0.45) .MODEL MmedMOD NMOS (VTO=3.7 KP=9 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.3) .MODEL MstroMOD NMOS (VTO=4.29 KP=155 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=3.05 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=13 RS=0.1) .MODEL RbreakMOD RES (TC1=9.3e-4 TC2=-5.5e-7) .MODEL RdrainMOD RES (TC1=1.3e-2 TC2=4e-5) .MODEL RSLCMOD RES (TC1=1e-3 TC2=1e-5) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-5.8e-3 TC2=-1.4e-5) .MODEL RvtempMOD RES (TC1=-2.8e-3 TC2=1e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-2) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1.5) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. www.onsemi.com 8 FDP050AN06A0 / FDB050AN06A0 — N-Channel PowerTrench® MOSFET PSPICE Electrical Model rev February 2003 template FDB050AN06A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.3e-11,nl=1.04,rs=1.76e-3,trs1=2.7e-3,trs2=2e-7,cjo=2.7e-9,m=5.4e-1,tt=1e-10,xti=3.9) dp..model dbreakmod = (rs=8e-1,trs1=5e-4,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.3e-9,isl=10e-30,nl=10,m=0.45) m..model mmedmod = (type=_n,vto=3.7,kp=9,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.29,kp=155,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3.05,kp=0.03,is=1e-30, tox=1,rs=0.1) LDRAIN sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-2) DPLCAP 5 DRAIN sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-4) 2 10 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=0.5) RLDRAIN sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1.5) RSLC1 51 c.ca n12 n8 = 1.5e-9 RSLC2 c.cb n15 n14 = 1.5e-9 ISCL c.cin n6 n8 = 3.75e-9 spe.ebreak n11 n7 n17 n18 = 64.8 GATE spe.eds n14 n8 n5 n8 = 1 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE DBREAK 50 - dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod EVTEMP RGATE + 18 22 9 20 21 11 DBODY 16 MWEAK 6 EBREAK + 17 18 - MMED MSTRO RLGATE CIN 8 LSOURCE 7 RSOURCE RLSOURCE i.it n8 n17 = 1 S1A 12 l.lgate n1 n9 = 4.7e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 4.03e-9 S2A 13 8 res.rlgate n1 n9 = 47 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 40 15 14 13 S1B CA RBREAK 17 18 RVTEMP S2B 13 CB + 6 8 EGS 19 - VBAT 5 8 EDS - m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=9.3e-4,tc2=-5.5e-7 res.rdrain n50 n16 = 1.1e-3, tc1=1.3e-2,tc2=4e-5 res.rgate n9 n20 = 1.3 res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=1e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.1e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-5.8e-3,tc2=-1.4e-5 res.rvtemp n18 n19 = 1, tc1=-2.8e-3,tc2=1e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10)) } } www.onsemi.com 9 IT 14 + + 8 22 RVTHRES SOURCE 3 FDP050AN06A0 / FDB050AN06A0 — N-Channel PowerTrench® MOSFET SABER Electrical Model th JUNCTION REV 23 February 2003 FDB050AN06A0T CTHERM1 TH 6 5e-3 CTHERM2 6 5 1.3e-2 CTHERM3 5 4 1.4e-2 CTHERM4 4 3 1.9e-2 CTHERM5 3 2 4.7e-2 CTHERM6 2 TL 9e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 1e-2 RTHERM2 6 5 3.1e-2 RTHERM3 5 4 4.5e-2 RTHERM4 4 3 1.2e-1 RTHERM5 3 2 1.3e-1 RTHERM6 2 TL 1.52e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDB050AN06A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =5e-3 ctherm.ctherm2 6 5 =1.3e-2 ctherm.ctherm3 5 4 =1.4e-2 ctherm.ctherm4 4 3 =1.9e-2 ctherm.ctherm5 3 2 =4.7e-2 ctherm.ctherm6 2 tl =9e-2 RTHERM3 CTHERM3 4 RTHERM4 rtherm.rtherm1 th 6 =1e-2 rtherm.rtherm2 6 5 =3.1e-2 rtherm.rtherm3 5 4 =4.5e-2 rtherm.rtherm4 4 3 =1.2e-1 rtherm.rtherm5 3 2 =1.3e-1 rtherm.rtherm6 2 tl =1.52e-1 } CTHERM4 3 RTHERM5 CTHERM5 2 CTHERM6 RTHERM6 tl www.onsemi.com 10 CASE FDP050AN06A0 / FDB050AN06A0 — N-Channel PowerTrench® MOSFET SPICE Thermal Model FDP050AN06A0 / FDB050AN06A0 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-220 3L Figure 22. TO-220, Molded, 3Lead, Jedec Variation AB Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a ON Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor's worldwide terms and conditions, specif-ically the warranty therein, which covers ON Semiconductor products. Dimension in Millimeters www.onsemi.com 11 FDP050AN06A0 / FDB050AN06A0 — N-Channel PowerTrench® MOSFET Mechanical Dimensions TO-263 2L (D2PAK) Figure 23. 2LD, TO263, Surface Mount Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a ON Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor's worldwide terms and conditions, specif-ically the warranty therein, which covers ON Semiconductor products. Dimension in Millimeters 12 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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