FDG6320C

Digital FET, Dual N & P Channel FDG6320C General Description These dual N & P−Channel logic level enhancement mode field effect transistors are produced using ON Semiconductor’s proprietary, high cell density, DMOS technology, this very high density process is especially tailored to minimize on−state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values. www.onsemi.com S2 G2 D1 D2 G1 S1 Pin 1 SC−88/SC70−6/SOT−363 CASE 419B−02 Features • N−Ch 0.22 A, 0.25 V MARKING DIAGRAM RDS(ON) = 4.0 W @ VGS = 4.5 V ♦ RDS(ON) = 5.0 W @ VGS = 2.7 V P−Ch −0.14 A, −25 V ♦ RDS(ON) = 10 W @ VGS = −4.5 V ♦ RDS(ON) = 13 W @ VGS = −2.7 V Very Small Package Outline SC70−6 Very Low Level Gate Drive Requirements Allowing Direct Operation in 3 V Circuits (VGS(th) < 1.5 V) Gate−Source Zener for ESD Ruggedness (>6 kV Human Body Model) These Devices are Pb−Free and are RoHS Compliant ♦ • • • • • ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Parameter Symbol N−Channel P−Channel Drain−Source Voltage 25 −25 V VGSS Gate−Source Voltage 8 −8 V Continuous 0.22 −0.14 A Pulsed 0.65 Drain Current PD Maximum Power Dissipation (Note 1) TJ, TSTG ESD Operating and Storage Temperature Range Electrostatic Discharge Rating MIL−STD−883D Human Body Model (100 pF / 1500 W) 20 M = Specific Device Code = Assembly Operation Month PIN CONNECTIONS 1 6 2 5 3 4 Units VDSS ID 20M −0.4 0.3 W −55 to 150 °C 6 kV ORDERING INFORMATION See detailed ordering and shipping information on page 8 of this data sheet. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. © Semiconductor Components Industries, LLC, 1998 June, 2020 − Rev. 5 1 Publication Order Number: FDG6320C/D FDG6320C THERMAL CHARACTERISTICS Symbol RqJA Parameter Ratings Unit 415 _C/W Thermal Resistance, Junction−to−Ambient (Note 1) 1. RqJA is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RqJC is guaranteed by design while RqCA is determined by the user’s board design. RqJA = 415°C/W on minimum pad mounting on FR−4 board in still air. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Type Min Typ Max Unit VGS = 0 V, ID = 250 mA N−Ch 25 − − V VGS = 0 V, ID = −250 mA P−Ch −25 − − Breakdown Voltage Temperature Coefficient ID = 250 mA, Referenced to 25_C N−Ch − 25 − ID = −250 mA, Referenced to 25_C P−Ch − −19 − Zero Gate Voltage Drain Current VDS = 20 V, VGS = 0 V N−Ch − − 1 − − 10 − − −1 − − −10 OFF CHARACTERISTICS BVDSS DBVDSS / DTJ IDSS Drain−Source Breakdown Voltage VDS = 20 V, VGS = 0 V, TJ = 55_C IDSS Zero Gate Voltage Drain Current VDS = −20 V, VGS = 0 V P−Ch VDS = −20 V, VGS = 0 V, TJ = 55_C IGSS Gate−Body Leakage Current VGS = 8 V, VDS = 0 V N−Ch − − 100 VGS = −8 V, VDS = 0 V P−Ch − − −100 VDS = VGS, ID = 250 mA N−Ch 0.65 0.85 1.5 VDS = VGS, ID = −250 mA P−Ch −0.65 −0.82 −1.5 Gate Threshold Voltage Temperature Coefficient ID = 250 mA, Referenced to 25_C N−Ch − −2.1 − ID = −250 mA, Referenced to 25_C P−Ch − 2.1 − Static Drain−Source On−Resistance VGS = 4.5 V, ID = 0.22 A N−Ch − 2.6 4 VGS = 4.5 V, ID = 0.22 A, TJ = 125_C − 5.3 7 VGS = 2.7 V, ID = 0.19 A − 3.7 5 − 7.3 10 VGS = −4.5 V, ID = −0.14 A, TJ = 125_C − 11 17 VGS = −2.7 V, ID = −0.05 A − 10.4 13 N−Ch 0.22 − − VGS = −4.5 V, VDS = −5 V P−Ch −0.14 − − VDS = 5 V, ID = 0.22 A N−Ch − 0.2 − VDS = −5 V, ID = −0.14 A P−Ch − 0.12 − N−Channel VDS = 10 V, VGS = 0 V, f = 1.0 MHz N−Ch − 9.5 − P−Ch − 12 − N−Ch − 6 − P−Ch − 7 − N−Ch − 1.3 − P−Ch − 1.5 − mV/_C mA mA nA ON CHARACTERISTICS (Note 2) VGS(th) DVGS(th) / DTJ RDS(ON) Gate Threshold Voltage VGS = −4.5 V, ID = −0.14 A ID(ON) gFS On−State Drain Current Forward Transconductance VGS = 4.5 V, VDS = 5 V P−Ch V mV/_C W A S DYNAMIC CHARACTERISTICS Ciss Coss Crss Input Capacitance Output Capacitance P−Channel VDS = −10 V, VGS = 0 V, f = 1.0 MHz Reverse Transfer Capacitance www.onsemi.com 2 pF FDG6320C ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (continued) Symbol Parameter Conditions Type Min Typ Max Unit N−Ch − 5 12 ns P−Ch − 5 12 N−Ch − 4.5 10 P−Ch − 8 16 N−Ch − 4 8 P−Ch − 9 18 N−Ch − 3.2 7 P−Ch − 5 12 N−Ch − 0.29 0.4 SWITCHING CHARACTERISTICS (Note 2) tD(on) tr tD(off) tf Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time P−Channel VDD = −5 V, ID = −0.5 A, VGS = −4.5 V, RGEN = 50 W Turn-Off Fall Time Qg Total Gate Charge Qgs Gate−Source Charge Qgd N−Channel VDD = 5 V, ID = 0.5 A, VGS = 4.5 V, RGEN = 50 W Gate−Drain Charge N−Channel VDS = 5 V, ID = 0.22 A, VGS = 4.5 V P−Ch − 0.22 0.31 N−Ch − 0.12 − P−Ch − 0.12 − N−Ch − 0.03 − P−Ch − 0.05 − N−Ch − − 0.25 P−Ch − − −0.25 VGS = 0 V, IS = 0.5 A (Note 2) N−Ch − 0.8 1.2 VGS = 0 V, IS = −0.5 A (Note 2) P−Ch − −0.8 −1.2 P−Channel VDS = −5 V, ID =−0.14 A, VGS = −4.5 V ns ns ns nC nC nC DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS VSD Maximum Continuous Source Current Drain−Source Diode Forward Voltage A V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2.0% www.onsemi.com 3 FDG6320C VGS =4.5 V 3.5 V 0.4 R DS(ON), NORMALIZED I D , DRAIN−SOURCE CURRENT (A) 0.5 3.0 V 2.7 V 0.3 2.5 V 0.2 2.0 V 0.1 0 0 1 2 3 4 DRAIN−SOURCE ON−RESISTANCE TYPICAL PERFORMANCE CHARACTERISTICS: N−CHANNEL 5 4.5 2.7 V 4 3.0 V 3.5 3.5 V 4.0 V 3 0 0.1 0.3 0.4 Figure 2. On−Resistance Variation with Drain Current and Gate Voltage 20 1.8 I D = 0.22 A 1.6 ID = 0.10 A RDS(ON), ON−RESISTANCE ( W) V GS = 4.5 V 1.4 1.2 1 0.8 0.6 −50 −25 0 25 50 75 100 125 16 12 8 T A =125°C 4 25°C 0 150 1 2 TJ , JUNCTION TEMPERATURE (°C) Figure 3. On−Resistance Variation with Temperature 0.2 TJ = -55°C VDS = 5 V 0.4 25°C 0.1 0.05 0 0.5 1 1.5 2 4 5 Figure 4. On−Resistance Variation with Gate−to−Source Voltage 125°C 0.15 3 VGS , GATE TO SOURCE VOLTAGE (V) I , REVERSE DRAIN CURRENT (A) RDS(ON) , NORMALIZED Figure 1. On−Region Characteristics DRAIN−SOURCE ON−RESISTANCE 0.2 5.0 V I D , DRAIN CURRENT (A) VDS , DRAIN−SOURCE VOLTAGE (V) I , DRAIN CURRENT (A) 4.5 V 2.5 2 5 VGS = 2.5 V 2.5 TJ = 125°C 0.01 25°C −55°C 0.001 0.0001 3 VGS = 0 V 0.1 0 0.2 0.4 0.6 0.8 1 1.2 VSD , BODY DIODE FORWARD VOLTAGE (V) VGS , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature www.onsemi.com 4 FDG6320C TYPICAL PERFORMANCE CHARACTERISTICS: N−CHANNEL (continued) 30 6 VDS = 5 V VGS , GATE−SOURCE VOLTAGE (V) I D = 0.22 A 10 V 15 CAPACITANCE (pF) 5 4 3 2 Ciss 8 3 1 0 0 0.1 0.2 0.3 0.4 0.5 Coss 5 2 0.1 0.6 Crss f = 1 MHz VGS = 0 V 0.3 Figure 7. Gate Charge Characteristics 25 SINGLE PULSE RqJA = 415°C/W TA = 25°C 40 POWER (W) I D , DRAIN CURRENT (A) 10 50 0.3 0.1 0.01 0.4 3 Figure 8. Capacitance Characteristics 1 0.03 1 V DS , DRAIN TO SOURCE VOLTAGE (V) Q g , GATE CHARGE (nC) VGS = 4.5 V SINGLE PULSE RqJA = 415°C/W TA = 25°C 0.8 30 20 10 2 5 10 25 0 0.0001 40 0.001 0.01 0.1 1 10 SINGLE PULSE TIME (sec) VDS , DRAIN−SOURCE VOLTAGE (V) Figure 9. Maximum Safe Operating Area Figure 10. Single Pulse Maximum Power Dissipation www.onsemi.com 5 200 FDG6320C 0.2 VGS = −4.5 V −3.5 V 0.15 R DS(ON), NORMALIZED −3.0 V −2.7 V −2.5 V 0.1 −2.0 V 0.05 0 0 1 2 3 DRAIN−SOURCE ON−RESISTANCE −ID , DRAIN−SOURCE CURRENT (A) TYPICAL PERFORMANCE CHARACTERISTICS: P−CHANNEL 2.5 VGS = −2.0 V 2 −2.7 V −3.0 V 1.5 −3.5 V −4.0 V −4.5 V 1 0.5 4 −2.5 V −VDS , DRAIN−SOURCE VOLTAGE (V) 0 Figure 11. On−Region Characteristics I D = −0.07 A I D = −0.14 A RDS(ON), ON−RESISTANCE ( W) VGS = −4.5 V 1.4 1.2 1 0.8 −25 0 25 50 75 100 125 20 15 T A = 125°C 10 TA = 25°C 5 0 1.5 150 2 TJ, JUNCTION TEMPERATURE (°C) 2.5 3 3.5 4 4.5 −VGS , GATE TO SOURCE VOLTAGE (V) Figure 13. On−Resistance Variation with Temperature Figure 14. On−Resistance Variation with Gate−to−Source Voltage 0.14 0.3 VDS = −5.0 V 0.12 TA = −55°C 0.1 −I , REVERSE DRAIN CURRENT (A) R DS(ON) , NORMALIZED 0.2 25 0.6 −50 −I , DRAIN CURRENT (A) 0.1 0.15 −I D, DRAIN CURRENT (A) Figure 12. On−Resistance Variation with Drain Current and Gate Voltage 1.6 DRAIN−SOURCE ON−RESISTANCE 0.05 25°C 125°C 0.08 0.06 0.04 0.02 0 0 1 2 3 VGS = 0 V 0.1 TA = 125°C 25°C −55°C 0.01 0.001 0.0001 0.2 4 5 0.4 0.6 0.8 1 1.2 −VSD , BODY DIODE FORWARD VOLTAGE (V) −VGS , GATE TO SOURCE VOLTAGE (V) Figure 15. Transfer Characteristics Figure 16. Body Diode Forward Voltage Variation with Source Current and Temperature www.onsemi.com 6 FDG6320C 8 40 ID = −0.14 A VDS = −5 V −10 V −15 V 6 20 CAPACITANCE (pF) −VGS , GATE−SOURCE VOLTAGE (V) TYPICAL PERFORMANCE CHARACTERISTICS: P−CHANNEL (continued) 4 2 Coss 5 3 1 0 0 0.1 0.2 0.3 0.4 0.5 0.1 0.5 Ciss 10 0.2 1 50 0.3 40 0.1 VGS = −4.5 V SINGLE PULSE RqJA = See Note 1b TA = 25°C 1 2 3 1 2 5 10 20 Figure 18. Capacitance Characteristics POWER (W) −ID , DRAIN CURRENT (A) Figure 17. Gate Charge Characteristics 0.005 0.5 −VDS , DRAIN TO SOURCE VOLTAGE (V) Qg , GATE CHARGE (nC) 0.03 Crss f = 1 MHz VGS = 0 V SINGLE PULSE RqJA = 415°C/W TA = 25°C 30 20 10 5 10 20 0 0.0001 40 0.001 0.01 0.1 1 10 SINGLE PULSE TIME (sec) − V DS , DRAIN−SOURCE VOLTAGE (V) Figure 19. Maximum Safe Operating Area Figure 20. Single Pulse Maximum Power Dissipation www.onsemi.com 7 200 FDG6320C TYPICAL PERFORMANCE CHARACTERISTICS: N & P−CHANNEL r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 0.5 D = 0.5 0.2 0.2 0.1 0.05 0.02 RqJA (t) = r(t) * RqJA RqJA = 415°C/W 0.1 0.05 P(pk) 0.02 0.01 t1 Single Pulse 0.01 t2 TJ − TA = P * RqJA (t) Duty Cycle, D = t1 / t2 0.005 0.002 0.0001 0.001 0.01 0.1 1 10 100 200 t 1, TIME (sec) Thermal characterization performed using the conditions described in Note 1. Transient thermal response will change depending on the circuit board design. Figure 21. Transient Thermal Response Curve ORDERING INFORMATION Device Order Number Device Marking Package Type Shipping† FDG6320C 20 SC−88/SC70−6/SOT−363 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE Y 1 SCALE 2:1 DATE 11 DEC 2012 2X aaa H D D H A D 6 5 GAGE PLANE 4 1 2 L L2 E1 E DETAIL A 3 aaa C 2X bbb H D 2X 3 TIPS e B 6X b ddd TOP VIEW C A-B D M A2 DETAIL A A 6X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END. 4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY AND DATUM H. 5. DATUMS A AND B ARE DETERMINED AT DATUM H. 6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. ccc C A1 SIDE VIEW C SEATING PLANE END VIEW c RECOMMENDED SOLDERING FOOTPRINT* 6X DIM A A1 A2 b C D E E1 e L L2 aaa bbb ccc ddd MILLIMETERS MIN NOM MAX −−− −−− 1.10 0.00 −−− 0.10 0.70 0.90 1.00 0.15 0.20 0.25 0.08 0.15 0.22 1.80 2.00 2.20 2.00 2.10 2.20 1.15 1.25 1.35 0.65 BSC 0.26 0.36 0.46 0.15 BSC 0.15 0.30 0.10 0.10 GENERIC MARKING DIAGRAM* 6 XXXMG G 6X 0.30 INCHES NOM MAX −−− 0.043 −−− 0.004 0.035 0.039 0.008 0.010 0.006 0.009 0.078 0.086 0.082 0.086 0.049 0.053 0.026 BSC 0.010 0.014 0.018 0.006 BSC 0.006 0.012 0.004 0.004 MIN −−− 0.000 0.027 0.006 0.003 0.070 0.078 0.045 0.66 1 2.50 0.65 PITCH XXX = Specific Device Code M = Date Code* G = Pb−Free Package (Note: Microdot may be in either location) DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *Date Code orientation and/or position may vary depending upon manufacturing location. *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42985B SC−88/SC70−6/SOT−363 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE Y DATE 11 DEC 2012 STYLE 1: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 2: CANCELLED STYLE 3: CANCELLED STYLE 4: PIN 1. CATHODE 2. CATHODE 3. COLLECTOR 4. EMITTER 5. BASE 6. ANODE STYLE 5: PIN 1. ANODE 2. ANODE 3. COLLECTOR 4. EMITTER 5. BASE 6. CATHODE STYLE 6: PIN 1. ANODE 2 2. N/C 3. CATHODE 1 4. ANODE 1 5. N/C 6. CATHODE 2 STYLE 7: PIN 1. SOURCE 2 2. DRAIN 2 3. GATE 1 4. SOURCE 1 5. DRAIN 1 6. GATE 2 STYLE 8: CANCELLED STYLE 9: PIN 1. EMITTER 2 2. EMITTER 1 3. COLLECTOR 1 4. BASE 1 5. BASE 2 6. COLLECTOR 2 STYLE 10: PIN 1. SOURCE 2 2. SOURCE 1 3. GATE 1 4. DRAIN 1 5. DRAIN 2 6. GATE 2 STYLE 11: PIN 1. CATHODE 2 2. CATHODE 2 3. ANODE 1 4. CATHODE 1 5. CATHODE 1 6. ANODE 2 STYLE 12: PIN 1. ANODE 2 2. ANODE 2 3. CATHODE 1 4. ANODE 1 5. ANODE 1 6. CATHODE 2 STYLE 13: PIN 1. ANODE 2. N/C 3. COLLECTOR 4. EMITTER 5. BASE 6. CATHODE STYLE 14: PIN 1. VREF 2. GND 3. GND 4. IOUT 5. VEN 6. VCC STYLE 15: PIN 1. ANODE 1 2. ANODE 2 3. ANODE 3 4. CATHODE 3 5. CATHODE 2 6. CATHODE 1 STYLE 16: PIN 1. BASE 1 2. EMITTER 2 3. COLLECTOR 2 4. BASE 2 5. EMITTER 1 6. COLLECTOR 1 STYLE 17: PIN 1. BASE 1 2. EMITTER 1 3. COLLECTOR 2 4. BASE 2 5. EMITTER 2 6. COLLECTOR 1 STYLE 18: PIN 1. VIN1 2. VCC 3. VOUT2 4. VIN2 5. GND 6. VOUT1 STYLE 19: PIN 1. I OUT 2. GND 3. GND 4. V CC 5. V EN 6. V REF STYLE 20: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 21: PIN 1. ANODE 1 2. N/C 3. ANODE 2 4. CATHODE 2 5. N/C 6. CATHODE 1 STYLE 22: PIN 1. D1 (i) 2. GND 3. D2 (i) 4. D2 (c) 5. VBUS 6. D1 (c) STYLE 23: PIN 1. Vn 2. CH1 3. Vp 4. N/C 5. CH2 6. N/C STYLE 24: PIN 1. CATHODE 2. ANODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE STYLE 25: PIN 1. BASE 1 2. CATHODE 3. COLLECTOR 2 4. BASE 2 5. EMITTER 6. COLLECTOR 1 STYLE 26: PIN 1. SOURCE 1 2. GATE 1 3. DRAIN 2 4. SOURCE 2 5. GATE 2 6. DRAIN 1 STYLE 27: PIN 1. BASE 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. EMITTER 2 6. COLLECTOR 2 STYLE 28: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 29: PIN 1. ANODE 2. ANODE 3. COLLECTOR 4. EMITTER 5. BASE/ANODE 6. CATHODE STYLE 30: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1 Note: Please refer to datasheet for style callout. If style type is not called out in the datasheet refer to the device datasheet pinout or pin assignment. DOCUMENT NUMBER: DESCRIPTION: 98ASB42985B SC−88/SC70−6/SOT−363 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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