FDH047AN08A0

MOSFET – N-Channel, POWERTRENCH) 75 V, 80 A, 4.7 mW FDH047AN08A0, FDP047AN08A0 www.onsemi.com Features • • • • • • RDS(ON) = 4.0 mW (Typ.), VGS = 10 V, ID = 80 A Qg (tot) = 92 nC (Typ.), VGS = 10 V Low Miller Charge Low Qrr Body Diode UIS Capability (Single Pulse and Repetitive Pulse) This Device is Pb−Free and is RoHS Compliant VDSS RDS(ON) MAX ID MAX 75 V 4.7 mW 80 A D Applications G • Synchronous Rectification for ATX / Server / Telecom PSU • Battery Protection Circuit • Motor Drives and Uninterruptible Power Supplies S TO−247−3 CASE 340CK G G D S TO−220−3 CASE 340AT D S MARKING DIAGRAM $Y&Z&3&K FDX047AN 08A0 $Y &Z &3 &K FDX047AN08A0 X = ON Semiconductor Logo = Assembly Plant Code = Data Code (Year & Week) = Lot = Specific Device Code = H/P ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2003 December, 2019 − Rev. 4 1 Publication Order Number: FDH047AN08A0/D FDH047AN08A0, FDP047AN08A0 MOSFET MAXIMUM RATINGS (TC = 25°C, Unless otherwise noted) Symbol Value Unit VDSS Drain to Source Voltage 75 V VGS Gate to Source Voltage ±20 V − Continuous (TC < 144°C, VGS = 10 V) 80 A − Continuous (TC = 25°C, VGS = 10 V, RqJA = 62°C/W) 15 ID ID Parameter Drain Current Drain Current − Pulsed Figure 4 A EAS Single Pulse Avalanche Energy (Note 1) 475 mJ PD Power Dissipation 310 W 2.0 W/°C −55 to +175 °C Derate Above 25°C TJ, TSTG Operating and Storage Temperature Range Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Starting TJ = 25°C, L = 0.232 mH, IAS = 64 A. THERMAL CHARACTERISTICS Symbol Parameter Value Unit 0.48 _C/W RqJC Thermal Resistance, Junction to Case, Max. TO−220, TO−247 RqJA Thermal Resistance, Junction to Ambient, Max. TO−220 (Note 2) 62 _C/W RqJA Thermal Resistance, Junction to Ambient, Max. TO−247 (Note 2) 30 _C/W 2. Pulse Width = 100 s. PACKAGE MARKING AND ORDERING INFORMATION Device Marking Device Package Reel Size Tape Width Quantity FDH047AN08A0 FDH047AN08A0 TO−247 Tube N/A 30 Units FDP047AN08A0 FDP047AN08A0 TO−220 Tube N/A 50 Units www.onsemi.com 2 FDH047AN08A0, FDP047AN08A0 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Parameter Symbol Test Conditions Min. Typ. Max. Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage ID = 250 mA, VGS = 0 V IDSS Zero Gate Voltage Drain Current VDS = 60 V, VGS = 0 V IGSS Gate to Source Leakage Current BVDSS 75 V 1 mA VDS = 60 V, VGS = 0 V, TC = 150_C 250 VGS = ±20 V ±100 nA 4.0 V W ON CHARACTERISTICS VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250 mA 2.0 RDS(ON) Drain to Source On Resistance ID = 80 A, VGS = 10 V 0.0040 0.0047 ID = 37 V, VGS = 6 V 0.0058 0.0087 ID = 80 A, VGS = 10 V, Tj = 175 °C 0.0082 0.011 VDS = 25 V, VGS = 0 V, f = 1 MHz 6600 pF DYNAMIC CHARACTERISTICS CISS Input Capacitance COSS Output Capacitance 1000 pF CRSS Reverse Transfer Capacitance 240 pF Qg(TOT) Total Gate Charge at 10 V VGS = 0 V to 10 V, VDD = 40 V, ID = 80 A, Ig = 1.0 mA 92 138 nC Qg(TH) Threshold Gate Charge VGS = 0 V to 2 V, VDD = 40 V, ID = 80 A, Ig = 1.0 mA 11 17 nC Qgs Gate to Source Gate Charge VDD = 40 V, ID = 80 A, Ig = 1.0 mA 27 nC Qgs2 Gate Charge Threshold to Plateau 16 nC Qgd Gate to Drain “Miller” Charge 21 nC SWITCHING CHARACTERISTICS (VGS = 10 V) tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time VDD = 40 V, ID = 80 A, VGS = 10 V, RGS = 3.3 W 160 ns 18 ns Rise Time 88 ns Turn-Off Delay Time 40 ns Fall Time 45 ns Turn-Off Time 128 ns ISD = 80 A 1.25 V ISD = 40 A 1 V Reverse Recovery Time ISD = 75 A, dlSD/dt = 100 A/ms 53 ns Reverse Recovered Charge ISD = 75 A, dlSD/dt = 100 A/ms 54 nC DRAIN−SOURCE DIODE CHARACTERISTICS VSD trr QRR Source to Drain Diode Voltage Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 3 FDH047AN08A0, FDP047AN08A0 TYPICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) 200 CURRENT LIMITED BY PACKAGE ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 160 120 80 40 0.2 0 0 25 50 75 100 125 150 0 175 25 50 TC , CASE TEMPERATURE ( o C) 75 100 125 150 175 TC, CASE TEMPERATURE ( oC) Figure 1. Normalized Power Dissipation vs. Case Temperature Figure 2. Maximum Continuous Drain Current vs. Case Temperature ZQJC, NORMALIZED THERMAL IMPEDANCE 2 1 DUTY CYCLE − DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZQJC x RQJC + TC SINGLE PULSE 0.01 10−5 10−4 10−3 10−2 10−1 100 101 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 2000 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK 1000 IDM, PEAK CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 CURRENT AS FOLLOWS: VGS = 10V 100 50 10−5 175 − TC I = I25 150 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10−4 10−3 10−2 t, PULSE WIDTH (s) Figure 4. Peak Current Capability www.onsemi.com 4 10−1 100 101 FDH047AN08A0, FDP047AN08A0 TYPICAL CHARACTERISTICS (Continued) (TC = 25°C unless otherwise noted) NOTE: 500 2000 If R = 0 tAV = (L)(I AS)/(1.3*RATED BVDSS − VDD) If R 0 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS − VDD) +1] IAS, AVALANCHE CURRENT (A) 10ms 1000 100ms ID, DRAIN CURRENT (A) Refer to ON Semiconductor Application Notes AN−7514 and AN−7515 100 1ms 10ms 10 OPERATION IN THIS AREA MAY BE LIMITEDD BY r DS(ON) 1 DC SINGLE PULSE TJ = MAX RATED TC = 25oC 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC 1 0.1 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) .01 100 Figure 5. Forward Bias Safe Operating Area 150 150 90 TJ = 175oC 60 TJ = −55 oC TJ = 25oC VGS = 7V VGS = 10V 120 ID, DRAIN CURRENT (A) ID , DRAIN CURRENT (A) Figure 6. Unclamped Inductive Switching Capability PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX VDD = 15V 120 100 0.1 1 10 tAV, TIME IN AVALANCHE (ms) VGS = 6V 90 60 VGS = 5V TC = 25oC 30 30 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 0 4.0 0 4.5 5.0 5.5 VGS , GATE TO SOURCE VOLTAGE (V) 0 6.0 Figure 7. Transfer Characteristics 2.5 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 6 VGS = 6V 5 4 VGS = 10V 20 40 60 ID , DRAIN CURRENT (A) PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 VGS = 10V, I D = 80A 3 0 1.5 Figure 8. Saturation Characteristics NORMALIZED DRAIN TO SOURCE ON RESISTANCE DRAIN TO SOURCE ON RESISTANCE (mW) 7 0.5 1.0 VDS , DRAIN TO SOURCE VOLTAGE (V) 0.5 −80 80 Figure 9. Drain to Source On Resistance vs. Drain Current −40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 Figure 10. Normalized Drain to Source On Resistance vs. Junction Temperature www.onsemi.com 5 FDH047AN08A0, FDP047AN08A0 TYPICAL CHARACTERISTICS (Continued) (TC = 25°C unless otherwise noted) 1.2 1.15 ID = 250 mA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250 mA 1.0 0.8 0.6 0.4 −80 −40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 1.05 1.00 0.95 0.90 −80 200 −40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) Figure 11. Normalized Gate Threshold Voltage vs. Junction Temperature Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10000 VGS , GATE TO SOURCE VOLTAGE (V) 10 CISS = CGS + CGD C, CAPACITANCE (pF) 1.10 COSS ^ CDS + CGD 1000 CRSS = CGD VGS = 0V, f = 1MHz 100 0.1 1 VDD = 40V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 80A ID = 10A 2 0 10 75 0 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 13. Capacitance vs. Drain to Source Voltage 25 50 Qg, GATE CHARGE (nC) 75 Figure 14. Gate Charge Waveforms for Constant Gate Currents www.onsemi.com 6 100 FDH047AN08A0, FDP047AN08A0 TEST CIRCUITS AND WAVEFORMS VDS L VARY tp TO OBTAIN REQUIRED PEAK IAS RG + DUT VGS 0V tp − VDD IAS 0.01 W Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS L VGS + DUT − VDD Ig(REF) Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS RL + VGS − VDD DUT RGS VGS Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms www.onsemi.com 7 FDH047AN08A0, FDP047AN08A0 PSPICE Electrical Model .SUBCKT FDP047AN08A0 2 1 3 ; rev March 2002 CA 12 8 1.5e−9 CB 15 14 1.5e−9 CIN 6 8 6.4e−9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 82.3 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e−9 LGATE 1 9 4.81e−9 LSOURCE 3 7 4.63e−9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 9e−4 RGATE 9 20 1.36 RLDRAIN 2 5 10 RLGATE 1 9 48.1 RLSOURCE 3 7 46.3 RSLC1 5 51 RSLCMOD 1e−6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 2.3e−3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*250),10))} .MODEL DBODYMOD D (IS = 2.4e−11 N = 1.04 RS = 1.76e−3 TRS1 = 2.7e−3 TRS2 = 2e−7 XTI=3.9 CJO = 4.35e−9 TT = 1e−8 M = 5.4e−1) .MODEL DBREAKMOD D (RS = 1.5e−1 TRS1 = 1e−3 TRS2 = −8.9e−6) .MODEL DPLCAPMOD D (CJO = 1.35e−9 IS = 1e−30 N = 10 M = 0.53) .MODEL MMEDMOD NMOS (VTO = 3.7 KP = 9 IS =1e−30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.36) .MODEL MSTROMOD NMOS (VTO = 4.4 KP = 250 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 3.05 KP = 0.03 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.36e1 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.05e−3 TC2 = −9e−7) .MODEL RDRAINMOD RES (TC1 = 1.9e−2 TC2 = 4e−5) .MODEL RSLCMOD RES (TC1 = 1.3e−3 TC2 = 1e−5) .MODEL RSOURCEMOD RES (TC1 = 1e−3 TC2 = 1e−6) www.onsemi.com 8 FDH047AN08A0, FDP047AN08A0 .MODEL RVTHRESMOD RES (TC1 = −6e−3 TC2 = −1.9e−5) .MODEL RVTEMPMOD RES (TC1 = −2.4e−3 TC2 = 1e−6) .MODEL S1AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −4.0 VOFF= −1.5) .MODEL S1BMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −1.5 VOFF= −4.0) .MODEL S2AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −1.0 VOFF= 0.5) .MODEL S2BMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = 0.5 VOFF= −1.0) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. Figure 21. PSPICE Electrical Model www.onsemi.com 9 FDH047AN08A0, FDP047AN08A0 SABER Electrical Model REV March 2002 template FDP047AN08A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 2.4e−11, n1 = 1.04, rs = 1.76e−3, trs1 = 2.7e−3, trs2 = 2e−7, xti = 3.9, cjo = 4.35e−9, tt = 1e−8, m = 5.4e−1) dp..model dbreakmod = (rs = 1.5e−1, trs1 = 1e−3, trs2 = −8.9e−6) dp..model dplcapmod = (cjo = 1.35e−9, isl =10e−30, nl =10, m = 0.53) m..model mmedmod = (type=_n, vto = 3.7, kp = 9, is =1e−30, tox=1) m..model mstrongmod = (type=_n, vto = 4.4, kp = 250, is = 1e−30, tox = 1) m..model mweakmod = (type=_n, vto = 3.05, kp = 0.03, is = 1e−30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e−5, roff = 0.1, von = −4.0, voff = −1.5) sw_vcsp..model s1bmod = (ron =1e−5, roff = 0.1, von = −1.5, voff = −4.0) sw_vcsp..model s2amod = (ron = 1e−5, roff = 0.1, von = −1.0, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e−5, roff = 0.1, von = 0.5, voff = −1.0) c.ca n12 n8 = 1.5e−9 c.cb n15 n14 = 1.5e−9 c.cin n6 n8 = 6.4e−9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e−9 l.lgate n1 n9 = 4.81e−9 l.lsource n3 n7 = 4.63e−9 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.05e−3, tc2 = −9e−7 res.rdrain n50 n16 = 9e−4, tc1 = 1.9e−2, tc2 = 4e−5 res.rgate n9 n20 = 1.36 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 48.1 res.rlsource n3 n7 = 46.3 res.rslc1 n5 n51= 1e−6, tc1 = 1e−3, tc2 =1e−5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.3e−3, tc1 = 1e−3, tc2 =1e−6 res.rvtemp n18 n19 = 1, tc1 = −2.4e−3, tc2 = 1e−6 res.rvthres n22 n8 = 1, tc1 = −6e−3, tc2 = −1.9e−5 spe.ebreak n11 n7 n17 n18 = 82.3 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod www.onsemi.com 10 FDH047AN08A0, FDP047AN08A0 sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51−>n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10)) } } Figure 22. SABER Electrical Model www.onsemi.com 11 FDH047AN08A0, FDP047AN08A0 SPICE Thermal Model th JUNCTION REV 23 March 2002 FDP047AN08A0T CTHERM1 th 6 6.45e−3 CTHERM2 6 5 3e−2 CTHERM3 5 4 1.4e−2 CTHERM4 4 3 1.65e−2 CTHERM5 3 2 4.85e−2 CTHERM6 2 tl 1e−1 RTHERM1 RTHERM1 th 6 3.24e−3 RTHERM2 6 5 8.08e−3 RTHERM3 5 4 2.28e−2 RTHERM4 4 3 1e−1 RTHERM5 3 2 1.1e−1 RTHERM6 2 tl 1.4e−1 RTHERM2 CTHERM1 6 CTHERM2 5 SABER Thermal Model CTHERM3 RTHERM3 SABER thermal model FDP047AN08A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 6.45e−3 ctherm.ctherm2 6 5 = 3e−2 ctherm.ctherm3 5 4 = 1.4e−2 ctherm.ctherm4 4 3 = 1.65e−2 ctherm.ctherm5 3 2 = 4.85e−2 ctherm.ctherm6 2 tl = 1e−1 4 CTHERM4 RTHERM4 3 rtherm.rtherm1 th 6 = 3.24e−3 rtherm.rtherm2 6 5 = 8.08e−3 rtherm.rtherm3 5 4 = 2.28e−2 rtherm.rtherm4 4 3 = 1e−1 rtherm.rtherm5 3 2 = 1.1e−1 rtherm.rtherm6 2 tl = 1.4e−1 } CTHERM5 RTHERM5 2 CTHERM6 RTHERM6 tl CASE Figure 23. Thermal Model POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−220−3LD CASE 340AT ISSUE A DATE 03 OCT 2017 Scale 1:1 DOCUMENT NUMBER: DESCRIPTION: 98AON13818G TO−220−3LD Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−247−3LD SHORT LEAD CASE 340CK ISSUE A A DATE 31 JAN 2019 A E P1 P A2 D2 Q E2 S B D 1 2 D1 E1 2 3 L1 A1 L b4 c (3X) b 0.25 M (2X) b2 B A M DIM (2X) e GENERIC MARKING DIAGRAM* AYWWZZ XXXXXXX XXXXXXX XXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week ZZ = Assembly Lot Code *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON13851G TO−247−3LD SHORT LEAD A A1 A2 b b2 b4 c D D1 D2 E E1 E2 e L L1 P P1 Q S MILLIMETERS MIN NOM MAX 4.58 4.70 4.82 2.20 2.40 2.60 1.40 1.50 1.60 1.17 1.26 1.35 1.53 1.65 1.77 2.42 2.54 2.66 0.51 0.61 0.71 20.32 20.57 20.82 13.08 ~ ~ 0.51 0.93 1.35 15.37 15.62 15.87 12.81 ~ ~ 4.96 5.08 5.20 ~ 5.56 ~ 15.75 16.00 16.25 3.69 3.81 3.93 3.51 3.58 3.65 6.60 6.80 7.00 5.34 5.46 5.58 5.34 5.46 5.58 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative