FDH3632

MOSFET – Power, N-Channel, POWERTRENCH 100 V, 80 A, 9 mW FDH3632, FDP3632, FDB3632 www.onsemi.com Features • • • • • • RDS(ON) = 7.5 mW (Typ.), VGS = 10 V, ID = 80 A Qg (tot) = 84 nC (Typ.), VGS = 10 V Low Miller Charge Low Qrr Body Diode UIS Capability (Single Pulse and Repetitive Pulse) These Devices are Pb−Free and are RoHS Compliant VDSS RDS(ON) MAX ID MAX 100 V 9 mW 80 A D Applications • • • • G Synchronous Rectification Battery Protection Circuit Motor Drives and Uninterruptible Power Supplies Micro Solar Inverter S TO−247−3 CASE 340CK G D S TO−220−3 CASE 340AT GD S D2PAK−3 CASE 418AJ MARKING DIAGRAM $Y&Z&3&K FDX3632 $Y &Z &3 &K FDX3632 = ON Semiconductor Logo = Assembly Plant Code = Data Code (Year & Week) = Lot = Specific Device Code X = H/P/B ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2017 May, 2020 − Rev. 5 1 Publication Order Number: FDP3632/D FDH3632, FDP3632, FDB3632 MOSFET MAXIMUM RATINGS (TC = 25°C, Unless otherwise noted) Symbol Value Unit VDSS Drain to Source Voltage 100 V VGS Gate to Source Voltage ±20 V − Continuous (TC < 111°C, VGS = 10 V) 80 A − Continuous (Tamb = 25°C, VGS = 10 V, RqJA = 43°C/W) 12 ID ID Parameter Drain Current Drain Current − Pulsed Figure 4 A EAS Single Pulse Avalanche Energy (Note 1) 337 mJ PD Power Dissipation 310 W 2.07 W/°C −55 to +175 °C (TC = 25°C) − Derate Above 25°C TJ, TSTG Operating and Storage Temperature Range Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Starting TJ = 25°C, L = 0.12mH, IAS = 75 A, VDD = 80 V. THERMAL CHARACTERISTICS Symbol Parameter D2−PAK, TO−247 Value Unit 0.48 _C/W RqJC Thermal Resistance, Junction to Case, Max. TO−220, RqJA Thermal Resistance, Junction to Ambient, Max. TO−220 (Note 2) 62 _C/W RqJA Thermal Resistance, Junction to Ambient, D2−PAK, Max. 1 in2 copper pad area 43 _C/W RqJA Thermal Resistance, Junction to Ambient, Max. TO−247 (Note 2) 30 _C/W 2. Pulse Width = 100 s PACKAGE MARKING AND ORDERING INFORMATION Device Marking Device Package Reel Size Tape Width Quantity FDB3632 D2−PAK 330 mm 24 mm 800 Units FDP3632 FDP3632 TO−220 Tube N/A 50 Units FDH3632 FDH3632 TO−247 Tube N/A 30 Units FDB3632 www.onsemi.com 2 FDH3632, FDP3632, FDB3632 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Parameter Symbol Test Conditions Min. Typ. Max. Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage ID = 250 mA, VGS = 0 V IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V IGSS Gate to Source Leakage Current BVDSS 100 V 1 mA VDS = 80 V, VGS = 0 V, TC = 150_C 250 VGS = ±20 V ±100 nA 4.0 V W ON CHARACTERISTICS VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250 mA 2.0 RDS(ON) Drain to Source On Resistance ID = 80 A, VGS = 10 V 0.0075 0.009 ID = 40 V, VGS = 6 V 0.009 0.015 ID = 80 A, VGS = 10 V, TC = 175 °C 0.018 0.022 VDS = 25 V, VGS = 0 V, f = 1 MHz 6000 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance 820 pF Crss Reverse Transfer Capacitance 200 pF Qg(tot) Total Gate Charge at 10 V VGS = 0 V to 10 V, VDD = 50 V, ID = 80 A, Ig = 1 mA 84 110 nC Qg(th) Threshold Gate Charge VGS = 0 V to 2 V, VDD = 50 V, ID = 80 A, Ig = 1 mA 11 14 nC Qgs Gate to Source Gate Charge VDD = 50 V, ID = 80 A, Ig = 1 mA 30 nC Qgs2 Gate Charge Threshold to Plateau 20 nC Qgd Gate to Drain “Miller” Charge 20 nC RESISTIVE SWITCHING CHARACTERISTICS (VGS = 10 V) tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time VDD = 50 V, ID = 80 A, VGS = 10 V, RGS = 3.6 W 102 ns 30 ns Rise Time 39 ns Turn-Off Delay Time 96 ns Fall Time 46 ns Turn-Off Time 213 ns ISD = 80 A 1.25 V ISD = 40 A 1 V ISD = 75 A, dlSD/dt = 100 A/ms 64 ns 120 nC DRAIN−SOURCE DIODE CHARACTERISTICS VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 3 FDH3632, FDP3632, FDB3632 TYPICAL CHARACTERISTICS TC = 25°C unless otherwise noted 125 1.0 CURRENT LIMITED BY PACKAGE ID, DRAIN CURRENT (A) 100 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 75 25 0 175 25 ZQJC, NORMALIZED THERMAL IMPEDANCE Figure 1. Normalized Power Dissipation vs. Ambient Temperature 2 VGS = 10V 50 TC , CASE TEMPERATURE ( oC) 50 75 100 125 150 TC , CASE TEMPERATURE (oC) 175 Figure 2. Maximum Continuous Drain Current vs Case Temperature DUTY CYCLE − DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 1 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZQJC x RQJC + TC SINGLE PULSE 0.01 10−5 10−4 10 −3 10−2 10−1 t, RECTANGULAR PULSE DURATION (s) 100 10 1 Figure 3. Normalized Maximum Transient Thermal Impedance 2000 TC = 25 oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 1000 CURRENT AS FOLLOWS: IDM, PEAK CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 VGS = 10V I = I25 175 − TC 150 100 50 10 −5 10−4 10−3 10 −2 t, PULSE WIDTH (s) 10−1 Figure 4. Peak Current Capability www.onsemi.com 4 100 101 FDH3632, FDP3632, FDB3632 TYPICAL CHARACTERISTICS (Continued) TC = 25°C unless otherwise noted NOTE: 400 200 10 ms IAS , AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 100 100 ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 1ms 1 10ms SINGLE PULSE TJ = MAX RATED TC = 25oC 0.1 1 DC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS − VDD) If R  0 tAV = (L/R)ln[(IAS *R)/(1.3*RATED BVDSS − VDD) +1] 100 STARTING T J = 25 oC STARTING TJ = 150oC 10 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 200 0.1 1 tAV , TIME IN AVALANCHE (ms) 0.01 Figure 5. Forward Bias Safe Operating Area 10 Figure 6. Unclamped Inductive Switching Capability 150 150 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX VDD = 15V 90 VGS = 10V VGS = 6V 120 ID, DRAIN CURRENT (A) 120 ID , DRAIN CURRENT (A) Refer to ON Semiconductor Application Notes AN−7514 and AN−7515 TJ = 175oC 60 TJ = 25oC TJ = −55oC 30 VGS = 5.5V 90 VGS = 5V 60 TC = 25oC 30 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 0 0 3.0 3.5 4.0 4.5 5.0 5.5 VGS , GATE TO SOURCE VOLTAGE (V) 0 6.0 1 2 3 VDS , DRAIN TO SOURCE VOLTAGE (V) 10 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX Figure 8. Saturation Characteristics 2.5 VGS = 6V NORMALIZED DRAIN TO SOURCE ON RESISTANCE DRAIN TO SOURCE ON RESISTANCE (mW) Figure 7. Transfer Characteristics 4 9 8 VGS = 10V 7 6 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 VGS = 10V, I D =80A 0.5 0 20 40 62 ID, DRAIN CURRENT (A) 80 −80 Figure 9. Drain to Source On Resistance vs Drain Current −40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 200 Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature www.onsemi.com 5 FDH3632, FDP3632, FDB3632 TYPICAL CHARACTERISTICS (Continued) TC = 25°C unless otherwise noted 1.2 1.4 VGS = VDS, ID = 250 mA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250 mA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 0.2 1.1 1.0 0.9 −80 −40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 −80 Figure 11. Normalized Gate Threshold Voltage vs. Junction Temperature 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 10 VGS , GATE TO SOURCE VOLTAGE (V) CISS  CGS + CGD COSS ^ CDS+ CGD 1000 CRSS  CGD VGS = 0V, f = 1MHz VDD = 50V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 80A ID = 40A 2 0 100 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 200 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10000 C, CAPACITANCE (pF) −40 0 100 Figure 13. Capacitance vs. Drain to Source Voltage 20 40 60 Qg, GATE CHARGE (nC) 80 Figure 14. Gate Charge Waveforms for Constant Gate Currents www.onsemi.com 6 100 FDH3632, FDP3632, FDB3632 TEST CIRCUITS WAVEFORMS VDS L VARY tp TO OBTAIN REQUIRED PEAK IAS RG + DUT VGS 0V tp − VDD IAS 0.01 W Figure 15. Unclamped Energy Test Curcuit Figure 16. Unclamped Energy Waveforms VDS L VGS + DUT − VDD Ig(REF) Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS RL + VGS − VDD DUT RGS VGS Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms www.onsemi.com 7 FDH3632, FDP3632, FDB3632 Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA (°C), and thermal resistance RqJA (°C/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. P DM + (T JM * T A) R QJA ON Semiconductor provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RqJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR−4 board with 1 oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the ON Semiconductor device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeter square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. (eq. 1) In using surface mount devices such as the TO−263 package, the environment in which it is applied will have a significant influence on the parts current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. R QJA + 26.51 ) 19.84 (0.262 ) Area) (eq. 2) 128 (1.69 ) Area) (eq. 3) Area in in2. R QJA + 26.51 ) Area in cm2. 80 RQJA= 26.51+ 19.84/(0.262+Area) EQ.2 RQJA = 26.51+ 128/(1.69+Area) EQ.3 RQJA (o C/W) 60 40 20 0.1 1 10 (0.645) (6.45) AREA, TOP COPPER AREA in2 (cm 2 ) (64.5) Figure 21. Thermal Resistance vs. Mounting Pad Area www.onsemi.com 8 FDH3632, FDP3632, FDB3632 PSPICE Electrical Model .SUBCKT FDB3632 2 1 3 ; rev May 2002 CA 12 8 1.7e−9 Cb 15 14 2.5e−9 Cin 6 8 6.0e−9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 102.5 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 5.61e−9 Ldrain 2 5 1.0e−9 Lsource 3 7 2.7e−9 RLgate 1 9 56.1 RLdrain 2 5 10 RLsource 3 7 27 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 3.8e−3 Rgate 9 20 1.1 RSLC1 5 51 RSLCMOD 1.0e−6 RSLC2 5 50 1.0e3 Rsource 8 7 RsourceMOD 2.5e−3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*350),3))} .MODEL DbodyMOD D (IS=5.9E−11 N=1.07 RS=2.3e−3 TRS1=3.0e−3 TRS2=1.0e−6 + CJO=4e−9 M=0.58 TT=4.8e−8 XTI=4.2) .MODEL DbreakMOD D (RS=0.17 TRS1=3.0e−3 TRS2=−8.9e−6) .MODEL DplcapMOD D (CJO=15e−10 IS=1.0e−30 N=10 M=0.6) .MODEL MstroMOD NMOS (VTO=4.1 KP=200 IS=1e−30 N=10 TOX=1 L=1u W=1u) .MODEL MmedMOD NMOS (VTO=3.4 KP=10.0 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=1.1) .MODEL MweakMOD NMOS (VTO=2.75 KP=0.05 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=1.1e+1 RS=0.1) .MODEL RbreakMOD RES (TC1=1.0e−3 TC2=−1.7e−6) .MODEL RdrainMOD RES (TC1=8.5e−3 TC2=2.8e−5) .MODEL RSLCMOD RES (TC1=2.0e−3 TC2=2.0e−6) www.onsemi.com 9 FDH3632, FDP3632, FDB3632 .MODEL RsourceMOD RES (TC1=4e−3 TC2=1e−6) .MODEL RvthresMOD RES (TC1=−4.0e−3 TC2=−1.8e−5) .MODEL RvtempMOD RES (TC1=−4.4e−3 TC2=2.2e−6) .MODEL S1AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−4 VOFF=−2) .MODEL S1BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−2 VOFF=−4) .MODEL S2AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−0.8 VOFF=0.4) .MODEL S2BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=0.4 VOFF=−0.8) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. Figure 22. PSPICE Electrical Model www.onsemi.com 10 FDH3632, FDP3632, FDB3632 SABER Electrical Model REV May 2002 template FDB3632 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=5.9e−11,nl=1.07,rs=2.3e−3,trs1=3.0e−3,trs2=1.0e−6,cjo=4e−9,m=0.58,tt=4.8e−8,xti=4.2) dp..model dbreakmod = (rs=0.17,trs1=3.0e−3,trs2=−8.9e−6) dp..model dplcapmod = (cjo=15e−10,isl=10.0e−30,nl=10,m=0.6) m..model mstrongmod = (type=_n,vto=4.1,kp=200,is=1e−30, tox=1) m..model mmedmod = (type=_n,vto=3.4,kp=10.0,is=1e−30, tox=1) m..model mweakmod = (type=_n,vto=2.75,kp=0.05,is=1e−30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e−5,roff=0.1,von=−4,voff=−2) sw_vcsp..model s2amod = (ron=1e−5,roff=0.1,von=−0.8,voff=0.4) sw_vcsp..model s2bmod = (ron=1e−5,roff=0.1,von=0.4,voff=−0.8) c.ca n12 n8 = 1.7e−9 c.cb n15 n14 = 2.5e−9 c.cin n6 n8 = 6.0e−9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 102.5 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 5.61e−9 l.ldrain n2 n5 = 1.0e−9 l.lsource n3 n7 = 2.7e−9 res.rlgate n1 n9 = 56.1 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 27 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=1.0e−3,tc2=−1.7e−6 res.rdrain n50 n16 = 3.8e−3, tc1=8.5e−3,tc2=2.8e−5 res.rgate n9 n20 = 1.1 res.rslc1 n5 n51 = 1.0e−6, tc1=2.0e−3,tc2=2.0e−6 res.rslc2 n5 n50 = 1.0e3 res.rsource n8 n7 = 2.5e−3, tc1=4e−3,tc2=1e−6 res.rvthres n22 n8 = 1, tc1=−4.0e−3,tc2=−1.8e−5 res.rvtemp n18 n19 = 1, tc1=−4.4e−3,tc2=2.2e−6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51−>n50) +=iscl www.onsemi.com 11 FDH3632, FDP3632, FDB3632 iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/350))** 3)) }} Figure 23. SABER Electrical Model www.onsemi.com 12 FDH3632, FDP3632, FDB3632 SPICE Thermal Model REV May 2002 th JUNCTION FDB3632 CTHERM1 TH 6 7.5e−3 CTHERM2 6 5 8.0e−3 CTHERM3 5 4 9.0e−3 CTHERM4 4 3 2.4e−2 CTHERM5 3 2 3.4e−2 CTHERM6 2 TL 6.5e−2 CTHERM1 RTHERM1 6 RTHERM1 TH 6 3.1e−4 RTHERM2 6 5 2.5e−3 RTHERM3 5 4 2.2e−2 RTHERM4 4 3 8.1e−2 RTHERM5 3 2 1.35e−1 RTHERM6 2 TL 1.5e−1 CTHERM2 RTHERM2 5 SABER Thermal Model SABER thermal model FDB3632 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =7.5e−3 ctherm.ctherm2 6 5 =8.0e−3 ctherm.ctherm3 5 4 =9.0e−3 ctherm.ctherm4 4 3 =2.4e−2 ctherm.ctherm5 3 2 =3.4e−2 ctherm.ctherm6 2 tl =6.5e−2 CTHERM3 RTHERM3 4 CTHERM4 RTHERM4 3 rtherm.rtherm1 th 6 =3.1e−4 rtherm.rtherm2 6 5 =2.5e−3 rtherm.rtherm3 5 4 =2.2e−2 rtherm.rtherm4 4 3 =8.1e−2 rtherm.rtherm5 3 2 =1.35e−1 rtherm.rtherm6 2 tl =1.5e−1 } CTHERM5 RTHERM5 2 CTHERM6 RTHERM6 tl CASE Figure 24. Thermal Model POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−220−3LD CASE 340AT ISSUE A DATE 03 OCT 2017 Scale 1:1 DOCUMENT NUMBER: DESCRIPTION: 98AON13818G TO−220−3LD Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−247−3LD SHORT LEAD CASE 340CK ISSUE A A DATE 31 JAN 2019 A E P1 P A2 D2 Q E2 S B D 1 2 D1 E1 2 3 L1 A1 L b4 c (3X) b 0.25 M (2X) b2 B A M DIM (2X) e GENERIC MARKING DIAGRAM* AYWWZZ XXXXXXX XXXXXXX XXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week ZZ = Assembly Lot Code *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON13851G TO−247−3LD SHORT LEAD A A1 A2 b b2 b4 c D D1 D2 E E1 E2 e L L1 P P1 Q S MILLIMETERS MIN NOM MAX 4.58 4.70 4.82 2.20 2.40 2.60 1.40 1.50 1.60 1.17 1.26 1.35 1.53 1.65 1.77 2.42 2.54 2.66 0.51 0.61 0.71 20.32 20.57 20.82 13.08 ~ ~ 0.51 0.93 1.35 15.37 15.62 15.87 12.81 ~ ~ 4.96 5.08 5.20 ~ 5.56 ~ 15.75 16.00 16.25 3.69 3.81 3.93 3.51 3.58 3.65 6.60 6.80 7.00 5.34 5.46 5.58 5.34 5.46 5.58 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS D2PAK−3 (TO−263, 3−LEAD) CASE 418AJ ISSUE F SCALE 1:1 GENERIC MARKING DIAGRAMS* XX XXXXXXXXX AWLYWWG IC DOCUMENT NUMBER: DESCRIPTION: XXXXXXXXG AYWW Standard 98AON56370E AYWW XXXXXXXXG AKA Rectifier XXXXXX XXYMW SSG DATE 11 MAR 2021 XXXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week W = Week Code (SSG) M = Month Code (SSG) G = Pb−Free Package AKA = Polarity Indicator *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. D2PAK−3 (TO−263, 3−LEAD) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative