FDMF3035

FDMF3035 Smart Power Stage (SPS) Module Description The SPS family is ON Semiconductor’s next−generation, fully optimized, ultra−compact, integrated MOSFET plus driver power stage solution for high−current, high−frequency, synchronous buck, DC− DC applications. The FDMF3035 integrates a driver IC with a bootstrap Schottky diode and two power MOSFETs into a thermally enhanced, ultra−compact 5 mm x 5 mm package. With an integrated approach, the SPS switching power stage is optimized for driver and MOSFET dynamic performance, minimized system inductance, and power MOSFET RDS(ON). The SPS family uses ON Semiconductor’s high−performance PowerTrench ® MOSFET technology, which reduces switch ringing, eliminating the need for a snubber circuit in most buck converter applications. A driver IC with reduced dead times and propagation delays further enhances the performance. The FDMF3035 supports diode emulation (using FCCM pin) for improved light−load efficiency. The FDMF3035 also provides a 3−state 5 V PWM input for compatibility with a wide range of PWM controllers. www.onsemi.com PQFN31 5y5, 0.5P CASE 483BR SCALE 2.5:1 MARKING DIAGRAM Features $Y&Z&3&K FDMF 3035 • Supports PS4 Mode for IMVP−8 • Ultra−Compact 5 mm x 5 mm PQFN Copper−Clip Package with Flip • • • • • • • • • • • • Chip Low−Side MOSFET High Current Handling: 50 A 3−State 5 V PWM Input Gate Driver Low Shutdown Current IVCC < 6 mA Diode Emulation for Enhanced Light Load Efficiency ON Semiconductor PowerTrench MOSFETs for Clean Voltage Waveforms and Reduced Ringing ON Semiconductor SyncFET™Technology (Integrated Schottky Diode) in Low−Side MOSFET Integrated Bootstrap Schottky Diode Optimized / Extremely Short Dead−Times Under−Voltage Lockout (UVLO) on VCC Optimized for Switching Frequencies up to 1.5 MHz Operating Junction Temperature Range: −40°C to +125°C ON Semiconductor Green Packaging and RoHS Compliance $Y &Z &3 &K FDMF3035 = ON Semiconductor Logo = Assembly Plant Code = Numeric Date Code = Lot Code = Specific Device Code ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. Applications • Notebook, Tablet PC and Ultrabook • Servers and Workstations, V−Core and Non−V−Core DC−DC Converters • Desktop and All−in−One Computers, V−Core and Non−V−Core DC−DC Converters • High−Current DC−DC Point−of−Load Converters • Small Form−Factor Voltage Regulator Modules © Semiconductor Components Industries, LLC, 2015 August, 2018 − Rev. 3 1 Publication Order Number: FDMF3035/D FDMF3035 ORDERING INFORMATION Part Number Current Rating Package Top Mark FDMF3035 50 A 31−Lead, Clip Bond PQFN SPS, 5.0 mm x 5.0 mm Package FDMF3035 APPLICATION DIAGRAM V5V RVCC CPVCC PVCC PWM Input VIN CVCC VCC CVIN VIN GL PWM RBOOT BOOT FDMF3035 CBOOT PHASE LOUT FCCM FCCM Input SW AGND VOUT VSW PGND COUT Figure 1. Typical Application Diagram FUNCTIONAL BLOCK DIAGRAM VCC PVCC BOOT VCC VIN PHASE DBoot ↓ 10 mA ↓ 10 mA (Q1) High Side MOSFET FCCM LEVEL SHIFT SW SHOOT− THROUGH PROTECTION 10 k PWM HDRV (Q2) Low Side MOSFET PVCC CONTROL LOGIC LDRV GL PGND AGND Figure 2. Functional Block Diagram www.onsemi.com 2 FDMF3035 FDMF3035 FCCM PWM 32 AGND 28 PGND 15 24 PGND 17 18 19 20 21 22 SW 16 16 23 17 18 19 20 21 22 23 SW 25 SW 14 SW PGND SW 26 15 13 14 PGND 13 27 12 12 33 GL 31 VIN 1 N/C 30 29 2 N/C 29 10 11 3 PVCC 28 VIN 4 PGND 27 30 5 GL 26 9 10 6 SW 25 VIN 7 SW 24 31 8 11 9 VCC 1 AGND 2 BOOT 3 SW 4 N/C 5 SW 6 PHASE 7 SW 8 VIN PIN CONFIGURATION SW Figure 3. Pin Configuration − Top View and Transparent View PIN DEFINITIONS Pin # Name 1 PWM PWM input to the gate driver IC FCCM The FCCM pin enables or disables Diode Emulation. When FCCM is LOW, diode emulation is allowed. When FCCM is HIGH, continuous conduction mode is forced. High impedance on the input of FCCM will shut down the driver IC (and module) 2 Description 3 VCC Power supply input for all analog control functions; this is the “quiet” VCC 4, 32 AGND Analog ground for analog portions of the IC and for substrate, pin 4 and pin 32 are internally fused (shorted) 5 BOOT Supply for high−side MOSFET gate driver. A capacitor from BOOT to PHASE supplies the charge to turn on the N−channel high−side MOSFET. During the freewheeling interval (LS MOSFET on), the high side capacitor is recharged by an internal diode connected to PVCC 6, 30, 31 N/C 7 PHASE No connect Return connection for the boot capacitor 8~11 VIN Power input for the power stage 12~15, 28 PGND Power return for the power stage 16~26 SW Switching node junction between high and low side MOSFETs; also the input into both the gate driver SW node comparator and the ZCD comparator 27, 33 GL Low−side MOSFET gate monitor 29 PVCC Power supply input for LS (Note 1) gate driver and boot diode 1. LS = Low Side. www.onsemi.com 3 FDMF3035 ABSOLUTE MAXIMUM RATINGS (TA = TJ = 25°C) Symbol VCC Parameter Min. Max. Unit Supply Voltage Referenced to AGND −0.3 7.0 V PVCC Drive Voltage Referenced to AGND −0.3 7.0 V VPWM PWM Signal Input Referenced to AGND −0.3 VCC + 0.3 V VFCCM Skip Mode Input Referenced to AGND −0.3 VCC + 0.3 V Low Gate Manufacturing Test Pin Referenced to PGND (DC) GND − 0.3 VCC + 0.3 V Referenced to AGND (AC < 20 ns, 10 mJ) GND − 0.3 VCC + 0.3 Power Input Referenced to PGND −0.3 30.0 V PHASE and SW Referenced to PGND (DC) −0.3 30.0 V Referenced to PGND (AC < 5ns) −8.0 37.0 Bootstrap Supply Referenced to AGND (DC) −0.3 33.0 V Boot to PHASE Voltage Boot to PHASE Voltage DC −0.3 7.0 V AC < 20 ns, 10 mJ −0.3 9.0 V fSW = 300 kHz, VIN = 12 V, VOUT = 1 V 50 A fSW = 1000 kHz, VIN = 12 V, VOUT = 1 V 45 VGL VIN VPHASE VSW VBOOT VBOOT−PHASE IO(AV) (Note 2) Output Current qJ−A qJ−PCB Junction−to−Ambient Thermal Resistance 12.4 °C/W Junction−to−PCB Thermal Resistance (under ON Semiconductor SPS Thermal Board) 1.8 °C/W +125 °C +150 °C +150 °C Human Body Model, JESD22−A114 1.5 kV Charged Device Model, JESD22−C101 2.5 TA Ambient Temperature Range TJ Maximum Junction Temperature TSTG Storage Temperature Range ESD Electrostatic Discharge Protection −40 −55 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. IO(AV) is rated with testing ON Semiconductor’s SPS evaluation board at TA = 25°C with natural convection cooling. This rating is limited by the peak SPS temperature, TJ = 150°C, and varies depending on operating conditions and PCB layout. This rating may be changed with different application settings. RECOMMENDED OPERATING CONDITIONS Symbol VCC PVCC VIN Parameter Min. Typ. Max. Unit Control Circuit Supply Voltage 4.5 5.0 5.5 V Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V 4.5 (Note 3) 12.0 24.0 (Note 4) V Output Stage Supply Voltage Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 3. 3.0 V VIN is possible according to the application condition. 4. Operating at high VIN can create excessive AC voltage overshoots on the SW−to−GND and BOOT−to−GND nodes during MOSFET switching transient. For reliable SPS operation, SW to GND and BOOT to GND must remain at or below the Absolute Maximum Ratings in the table above. www.onsemi.com 4 FDMF3035 ELECTRICAL CHARACTERISTICS (Typical value is under VIN = 12 V, VCC = PVCC = 5 V and TA = TJ = + 25°C unless otherwise noted. Minimum / Maximum values are under VIN = 12 V, VCC = PVCC = 5 V + 10% and TJ = TA = −40 ~ 125°C unless otherwise noted) Symbol Parameter Condition Min. Typ. Max. Unit 11 mA BASIC OPERATION ICC_SD Quiescent Current with PWM and FCCM Pin Floating (PS4 Mode) ICC = IVCC + IPVCC, PWM = Floating, FCCM = Floating (Non−Switching) 6 ICC_HIGH Quiescent Current with PWM Pin Floating and VFCCM = 5 V ICC = IVCC + IPVCC, PWM = Floating, FCCM = 5 V 80 mA ICC_LOW Quiescent Current with PWM Pin Floating and VFCCM = 0 V ICC = IVCC + IPVCC, PWM = Floating, FCCM = 0V 120 mA VUVLO_RISE UVLO Rising Threshold VCC Rising 3.4 VUVLO_FALL UVLO Falling Threshold VCC Falling tD_POR POR Delay to Enable IC 2.5 3.9 3.0 VCC UVLO Rising to Internal PWM Enable V V 15 ms FCCM INPUT IFCCM_HIGH Pull−Up Current VFCCM = 5 V 50 mA IFCCM_LOW Pull−Down Current VFCCM = 0 V −50 mA VIH_FCCM FCCM High Level Input Voltage VTRI_FCCM FCCM 3−State Window VCC = PVCC = 5 V 3.8 VCC = PVCC = 5 V 2.2 V 2.8 V VIL_FCCM FCCM Low Level Input Voltage VCC = PVCC = 5 V 1.0 V tPS_EXIT PS4 Exit Latency VCC = PVCC = 5 V 15 ms PWM INPUT IPWM_HIGH Pull−Up Current VFCCM = 5 V 250 mA IPWM_LOW Pull−Down Current VFCCM = 0 V −250 mA VIH_PWM PWM High Level Input Voltage VCC = PVCC = 5 V 4.1 VTRI_PWM PWM 3−State Window VCC = PVCC = 5 V 1.6 PWM Low Level Input Voltage VCC = PVCC = 5 V VIL_PWM tD_HOLD−OFF 3−State Shut−off Time VCC = PVCC = 5 V, TJ = 25°C 100 V 175 3.4 V 0.7 V 250 ns PWM PROPAGATION DELAYS & DEAD TIMES (VIN = 12 V, VCC = PVCC = 5 V, FSW = 1 MHz, IOUT = 20 A, TA = 255C) tPD_PHGLL PWM HIGH Propagation Delay PWM Going HIGH to GL Going LOW, VIH_PWM to 90% GL 25 ns tPD_PLGHL PWM LOW Propagation Delay PWM Going LOW to GH (Note 5) Going LOW, VIL_PWM to 90% GH 15 ns tPD_PHGHH PWM HIGH Propagation Delay (FCCM Held LOW) PWM Going HIGH to GH Going HIGH, VIH_PWM to 10% GH (FCCM = LOW, IL = 0, Assumes DCM) 15 ns tPD_TSGHH Exiting 3−State Propagation Delay PWM (from 3−State) Going HIGH to GH Going HIGH, VIH_PWM to 10% GH 35 ns tPD_TSGLH PWM (from 3−State) Going LOW to GL Going HIGH, VIL_PWM to 10% GL 35 ns tD_DEADON LS Off to HS On Adaptive Dead Time SW ≤ −0.2 V with GH ≤ 10%, PWM Transition LOW to HIGH 25 ns tD_DEADOFF HS Off to LS On Adaptive Dead Time SW ≤ −0.2 V with GL ≤ 10%, PWM Transition HIGH to LOW 20 ns Exiting 3−State Propagation Delay www.onsemi.com 5 FDMF3035 ELECTRICAL CHARACTERISTICS (Typical value is under VIN = 12 V, VCC = PVCC = 5 V and TA = TJ = + 25°C unless otherwise noted. Minimum / Maximum values are under VIN = 12 V, VCC = PVCC = 5 V + 10% and TJ = TA = −40 ~ 125°C unless otherwise noted) Symbol Parameter Condition Min. Typ. Max. Unit 1.0 2.5 W HIGH−SIDE DRIVER (HDRV, VCC = PVCC = 5 V) RSOURCE_GH Output Impedance, Sourcing Source Current = 100 mA ISOURCE_GH Output Sourcing Peak Current GH = 2.5 V 2 1.0 A RSINK_GH Output Impedance, Sinking Sink Current = 100 mA 2.5 ISINK_GH Output Sinking Peak Current GH = 2.5 V 4 A tR_GH GH Rise Time GH = 10% to 90%, CLOAD = 3.0 nF 8 ns tF_GH GH Fall Time GH = 90% to 10%, CLOAD = 3.0 nF 8 ns W LOW−SIDE DRIVER (LDRV, VCC = PVCC = 5 V) RSOURCE_GL Output Impedance, Sourcing Source Current = 100 mA ISOURCE_GL Output Sourcing Peak Current GL = 2.5 V 1.0 2.5 W 2 A 0.5 W RSINK_GL Output Impedance, Sinking Sink Current = 100 mA ISINK_GL Output Sinking Peak Current GL = 2.5 V 4 A tR_GL GL Rise Time GL = 10% to 90%, CLOAD = 3.0 nF 8 ns tF_GL GL Fall Time GL = 90% to 10%, CLOAD = 3.0 nF 4 ns 0.6 V BOOT DIODE VF Forward−Voltage Drop IF = 10 mA VR Breakdown Voltage IR = 1 mA 30 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. GH = Gate High, internal gate pin of the high−side MOSFET. www.onsemi.com 6 FDMF3035 TYPICAL PERFORMANCE CHARACTERISTICS 55 50 50 45 40 FSW = 300 kHz 35 FSW = 1000 kHz 30 25 20 15 10 5 0 VIN = 12 V PVCC & VCC = 5 V, VOUT = 1V 0 25 50 75 100 125 40 FSW = 300kHz 35 FSW = 1000kHz 30 25 20 15 10 5 0 150 VIN = 19 V, PCCC & VCC = 5 V, VOUT = 1V 0 25 100 125 150 Figure 5. Safe Operating Area with 19 VIN 12 12 VIN, 300 kHz PVCC & VCC = 5 V, VOUT = 1 V 12 VIN, 500 kHz 12 VIN, 800 kHz 8 12 VIN, 1000 kHz 7 6 5 4 3 2 1 0 5 10 15 20 25 30 35 40 45 50 19 VIN, 300 kHz PVCC & VCC = 5 V, VOUT = 1 V 11 19 VIN, 500 kHz 10 19 VIN, 800 kHz 9 19 VIN, 1000 kHz 8 7 6 5 4 3 2 1 0 55 0 5 10 Figure 6. Power Loss vs. Output Current with 12 VIN Normalized Module Power Loos VIN = 12 V, PVCC & VCC = 5 V, VOUT = 1 V, IOUT = 30 A 1.3 1.2 1.1 1.0 0.9 200 300 400 500 600 700 800 900 20 25 30 35 40 45 50 55 Figure 7. Power Loss vs. Output Current with 19 VIN 1.20 1.4 15 Module Output Current, IOUT [A] Module Output Current, IOUT [A] Normalized Module Power Loos 75 Figure 4. Safe Operating Area with 12 VIN 9 0.8 50 PCB Temperature, TPCB [°C] 10 0 45 PCB Temperature, TPCB [°C] 11 Module Power Loss, PLMOD [W] Module Output Current IOUT [A] 55 Module Power Loss, PLMOD [W] Module Output Current IOUT [A] (Test Conditions: VIN = 12 V, VCC = PVCC = 5 V, VOUT = 1 V, LOUT = 250 nH, TA = 25°C and natural convection cooling, unless otherwise noted) 1.15 1.10 1.05 1.00 0.95 1000 1100 PVCC & VVCC = 5 V, VOUT = 1 V, FSW = 500 kHz, VOUT = 30A Module Switching Frequency, FSW [kHz] 4 6 8 10 12 14 16 18 20 Module Input Voltage, VIN [V] Figure 8. Power Loss vs. Switching Frequency Figure 9. Power Loss vs. Input Voltage www.onsemi.com 7 FDMF3035 TYPICAL PERFORMANCE CHARACTERISTICS (continued) (Test Conditions: VIN = 12 V, VCC = PVCC = 5 V, VOUT = 1 V, LOUT = 250 nH, TA = 25°C and natural convection cooling, unless otherwise noted) 1.5 VIN = 12 V, VOUT = 1 V, FSW = 500 kHz, VOUT = 30 A Normalized Module Power Loss Normalized Module Power Loss 1.15 1.10 1.05 1.00 0.95 0.90 VIN = 12 V, PVCC & VVCC = 5 V, FSW = 500 kHz, VOUT = 30 A 1.4 1.3 1.2 1.1 1.0 0.9 4.0 4.5 5.0 5.5 6.0 0.5 1.0 1.5 Driver Supply Voltage, PVCC & VCC [V] Driver Supply Current, IPVCC + IVCC, [A] Normalized Module Power Loss VIN = 12 V, PVCC & VVCC = 5 V, FSW = 500 kHz, VOUT = 1 V, IOUT = 30 A 1.000 0.998 0.996 0.994 0.992 300 350 400 3.5 450 500 0.04 VIN = 12 V, PVCC & VCC = 5 V, VOUT = 1 V, I OUT = 0 A 0.035 0.03 0.025 0.02 0.015 0.01 200 300 Output Inductor, LOUT [nH] 400 500 600 700 800 900 1000 1100 Module Switching Frequency, FSW [kHz] Figure 13. Driver Supply Current vs. Switching Frequency Figure 12. Power Loss vs. Output Inductor 1.06 0.024 VIN = 12 V, VOUT = 1 V, FSW = 500 kHz, IOUT = 0 A Normalized Driver Supply Current Driver Supply Current,IPVCC + IVCC, [A] 3.0 Figure 11. Power Loss vs. Output Voltage 1.002 250 2.5 Module Output Voltage, VOUT [V] Figure 10. Power Loss vs. Driver Supply Voltage 0.990 200 2.0 0.022 0.02 0.018 0.016 0.014 0.012 4.0 4.5 5.0 5.5 6.0 VIN = 12 V, PVCC & V VCC = 5 V, I OUT = 1 V 1.04 1.02 1.00 FSW = 1000 kHz 0.98 0.96 0.94 FSW = 300 kHz 0.92 0.90 Driver Supply Voltage, PVCC & VCC [V] 0 5 10 15 20 25 30 35 40 45 50 Module Output Current, IOUT [A] Figure 15. Driver Supply Current vs. Output Current Figure 14. Driver Supply Current vs. Driver Supply Voltage www.onsemi.com 8 55 FDMF3035 TYPICAL PERFORMANCE CHARACTERISTICS (continued) (Test Conditions: VIN = 12 V, VCC = PVCC = 5 V, VOUT = 1 V, LOUT = 250 nH, TA = 25°C and natural convection cooling, unless otherwise noted) PWM Threshold Voltage, VPWM [V] Driver Supply Voltage, VCC [V] 3.7 UVLO UP 3.6 3.5 3.4 3.3 3.2 3.1 3.0 UVLODN 2.9 2.8 −50 −25 0 25 50 75 100 125 150 175 5.0 T A = 25°C 4.5 V IH_PWM 4.0 V TRI_HI 3.5 3.0 2.5 2.0 V TRI_LO 1.5 1.0 V IL_PWM 0.5 0.0 4.50 4.75 Driver IC Junction Temperature, TJ [°C] FCCM Threshold Voltage, VFCCM[V] PWM Threshold Voltage, VPWM [V] VIH_PWM 4.0 VTRI_HI 3.5 3.0 2.5 2.0 VTRI_LO 1.5 1.0 VIL_PWM 0.5 0.0 −50 −25 0 25 50 75 100 125 150 175 4.0 TA = 25°C VIH_FCCM 3.5 VTRI_HI_FCCM 3.0 2.5 VHIZ_FCCM 2.0 VTRI_LO_FCCM 1.5 VIL_FCCM 1.0 4.50 4.75 Driver IC Junction Temperature, TJ [°C] V IH_FCCM 3.5 V TRI_HI_FCCM 3 2.5 V HIZ_FCCM 2 V TRI_LO_FCCM 1.5 1 V IL_FCCM −50 −25 0 25 50 75 100 125 5.25 5.50 Figure 19. FCCM Threshold vs. Driver Supply Voltage FCCM Pull−Up Current, IFCCM_HIGH [mA] FCCM Threshold Voltage, VFCCM, [V] V CC = 5 V 5.00 Driver Supply Voltage, VCC [V] Figure 18. PWM Threshold vs. Temperature 4 5.50 Figure 17. PWM Threshold vs. Driver Supply Voltage V CC = 5 V 4.5 5.25 Driver Supply Voltage, VCC [V] Figure 16. UVLO Threshold vs. Temperature 5.0 5.00 150 175 54 VCC = 5V 52 50 48 46 44 42 −50 Driver IC Junction Temperature, TJ [°C] −25 0 25 50 75 100 125 150 Driver IC Junction Temperature, TJ [°C] Figure 21. FCCM Pull−Up Current vs. Temperature Figure 20. FCCM Threshold vs. Temperature www.onsemi.com 9 175 FDMF3035 TYPICAL PERFORMANCE CHARACTERISTICS (continued) (Test Conditions: VIN = 12 V, VCC = PVCC = 5 V, VOUT = 1 V, LOUT = 250 nH, TA = 25°C and natural convection cooling, unless otherwise noted) Driver Shut−Down Current, ISHDN [mA] Boot Diode Forward Voltage, VF [mV] 800 IF = 10 mA 750 700 650 600 550 500 −50 −25 0 25 50 75 100 125 150 175 10 V CC = 5V, PWM = floating, FCCM = floating 9 8 7 6 5 4 3 Driver IC Junction Temperature, TJ [°C] Driver Quiescent Current, ICC [mA] V CC = 5 V, PWM = Floating FCCM = 0 V 120 110 100 90 FCCM = 5 V 80 70 60 −50 −25 0 25 50 75 100 125 0 25 50 75 100 125 150 Figure 23. Driver Shutdown Current vs. Temperature 150 130 −25 Driver IC Junction Temperature, TJ [°C] Figure 22. Boot Diode Forward Voltage vs. Temperature 140 −50 150 175 Driver IC Junction Temperature, TJ [°C] Figure 24. Driver Quiescent Current vs. Temperature www.onsemi.com 10 175 FDMF3035 VIH_PWM VIL_PWM PWM tPD_PHGLL = PWM HI to GL LOW, V IH_PWM to 90% GL GL 90% 90% 10% 10% GH−PHASE (internal) 90% 90% 10% 10% tFALL_GL = 90% GL to 10% GL tD_DEADON = LS Off to HS On Dead Time, 10% GL to VBOOT−GND tD_HOLD−OFF. 8. VTRI_HI = PWM trip level to enter 3−state on PWM falling edge. 9. VTRI_LO = PWM trip level to enter 3−state on PWM rising edge. 10. VIH_PWM = PWM trip level to exit 3−state on PWM rising edge and enter the PWM HIGH logic state. 11. VIL_PWM = PWM trip level to exit 3−state on PWM falling edge and enter the PWM LOW logic state. Figure 26. PWM Threshold Definition www.onsemi.com 11 FDMF3035 FUNCTIONAL DESCRIPTION The SPS FDMF3035 is a driver−plus−MOSFET module optimized for the synchronous buck converter topology. A PWM input signal is required to properly drive the high−side and the low−side MOSFETs. The part is capable of driving speed up to 1.5 MHz. Table 2. FCCM LOGIC TABLE PWM FCCM GH GL Driver Enable State x 3−State 0 0 0 (ICC < 6 mA) Power−On Reset (POR & UVLO) 3−State 0 0 0 1 The FDMF3035 incorporates a POR feature that ensures both LDRV and HDRV are forced inactive (LDRV = HDRV = 0) until UVLO > 3.4 V (typical rising threshold). UVLO is performed on VCC (not on PVCC or VIN). After all gate drive blocks are fully powered on and have finished the startup sequence, the internal driver IC EN_PWM signal is released HIGH, enabling the driver outputs. Once the driver POR has finished, the driver follows the state of the PWM signal (it is assumed that at startup the controller is either in a high− impedance state or forcing the PWM signal to be within the driver 3−state window). 3−State 1 0 0 1 0 0 0 1 when IL > 0 0 when IL < 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 1 (FCCM = 1 ³ Forced CCM) Setting the FCCM pin to a HIGH state will allow for forced CCM operation. During forced CCM, the FDMF3035 will always follow the PWM signal and allow for negative inductor current. Driver State (FCCM = 0 ³ Diode Emulation / DCM) Setting the FCCM pin to a LOW state will enable diode emulation. Diode emulation allows for higher converter efficiency under light load situations. With diode emulation is activated, the FDMF3035 will detect the zero current crossing of the output inductor (at light loads) and will turn off low side MOSFET gate GL to prevent negative inductor current from flowing. Diode emulation ensures discontinuous conduction mode (DCM) operation. Diode emulation is asynchronous to the PWM signal. Therefore, the FDMF3035 will respond to the FCCM input immediately after it changes state. Enable Disable 3.0 3.4 VCC [V] Figure 27. UVLO 3−State PWM Input The FDMF3035 incorporates a 3−state 5 V PWM input gate drive design. The 3−state gate drive has both logic HIGH and LOW levels, along with a 3−state shutdown window. When the PWM input signal enters and remains within the 3−state window for a defined hold−off time (tD_HOLD−OFF), both GL and GH are pulled LOW. This feature enables the gate drive to shutdown both the high−side and the low−side MOSFETs to support features such as phase shedding, a common feature on multi−phase voltage regulators. (FCCM = HiZ " Shutdown) Setting the FCCM pin to a HIGH impedance state (HiZ) will shutdown the driver IC with ICC < 6 mA. The FDMF3035 requires a startup latency time of (