FDMF5833

FDMF5833 Smart Power Stage (SPS) Module with Integrated Thermal Warning and Thermal Shutdown www.onsemi.com Description The SPS family is ON Semiconductor’s next−generation, fully optimized, ultra−compact, integrated MOSFET plus driver power stage solution for high−current, high−frequency, synchronous buck, DC−DC applications. The FDMF5833 integrates a driver IC with a bootstrap Schottky diode, two power MOSFETs, and a thermal monitor into a thermally enhanced, ultra−compact 5 mm x 5 mm package. With an integrated approach, the SPS switching power stage is optimized for driver and MOSFET dynamic performance, minimized system inductance, and power MOSFET RDS(ON). The SPS family uses ON Semiconductor’s high−performance POWERTRENCH® MOSFET technology, which reduces switch ringing, eliminating the need for a snubber circuit in most buck converter applications. A driver IC with reduced dead times and propagation delays further enhances the performance. A thermal warning function warns of a potential over−temperature situation. A thermal shutdown function turns off the driver if an over−temperature condition occurs. The FDMF5833 incorporates an Auto−DCM Mode (ZCD#) for improved light−load efficiency. The FDMF5833 also provides a 3−state 5 V PWM input for compatibility with a wide range of PWM controllers. Features • Ultra−Compact 5 mm x 5 mm PQFN Copper−Clip Package with Flip Chip Low−Side MOSFET PQFN31 5x5, 0.5P CASE 483BR MARKING DIAGRAMS FDMF5833 $Y&Z&3&K FDMF 5833 $Y &Z &3 &K FDMF5833 • High Current Handling: 50 A • 3−State 5 V PWM Input Gate Driver • Dynamic Resistance Mode for Low−Side Drive (LDRV) Slows = Logo = Assembly Plant Code = Numeric Date Code = Lot Code = Specific Device Code FDMF5833−F085 Low−Side MOSFET during Negative Inductor Current Switching • Auto DCM (Low−Side Gate Turn Off) Using ZCD# Input • Thermal Warning (THWN#) to Warn Over− Temperature of Gate • • • • • • • • Driver IC Thermal Shutdown (THDN) HS−Short Detect Fault# / Shutdown Dual Mode Enable / Fault# Pin Internal Pull−Up and Pull−Down for ZCD# and EN Inputs, respectively ON Semiconductor POWERTRENCH MOSFETs for Clean Voltage Waveforms and Reduced Ringing ON Semiconductor SyncFET™ Technology (Integrated Schottky Diode) in Low−Side MOSFET Integrated Bootstrap Schottky Diode Optimized / Extremely Short Dead−Times © Semiconductor Components Industries, LLC, 2013 June, 2018 − Rev.3 1 5833 F085 AZZYYWW 5833 F085 A ZZ YY WW = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information on page 24 of this data sheet. Publication Order Number: FDMF5833/D FDMF5833 Features (continued) Applications • Under−Voltage Lockout (UVLO) on VCC • Optimized for Switching Frequencies up to 1.5 MHz • PWM Minimum Controllable On−Time: • • • • • • • Notebook, Tablet PC and Ultrabook • Servers and Workstations, V−Core and Non−V−Core DC−DC Converters • Desktop and All−in−One Computers, V−Core and 30 ns Low Shutdown Current: < 3 mA Optimized FET Pair for Highest Efficiency: 10 ~ 15% Duty Cycle Operating Junction Temperature Range: −40°C to +125°C ON Semiconductor Green Packaging Automotive Qualified to AEC−Q100 (F085 Version) These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant • • • • • Non−V−Core DC−DC Converters High−Performance Gaming Motherboards High−Current DC−DC Point−of−Load Converters Networking and Telecom Microprocessor Voltage Regulators Small Form−Factor Voltage Regulator Modules Automotive−qualified Systems (F085 Version) www.onsemi.com 2 FDMF5833 VIN 32 AGND 28 16 17 18 19 20 21 22 23 16 17 18 19 20 21 22 23 SW PGND SW 24 SW 15 SW PGND SW 25 SW 14 SW PGND SW 26 15 13 33 GL 14 PGND 13 27 12 12 31 29 1 EN/ FAULT# 30 10 11 2 THWN# 29 VIN 3 PVCC 28 30 4 PGND 27 9 10 5 GL 26 VIN 6 SW 25 31 7 11 9 8 SW 24 1 PWM 2 ZCD# 3 VCC 4 AGND 5 BOOT 6 NC 7 PHASE 8 VIN PIN CONFIGURATION SW Figure 1. Pin Configuration − Top View and Transparent View PIN DESCRIPTION Pin No. Symbol Description 1 PWM PWM input to the gate driver IC 2 ZCD# Enable input for the ZCD (Auto DCM) comparator 3 VCC Power supply input for all analog control functions; this is the “quiet” VCC 4, 32 AGND Analog ground for analog portions of the IC and for substrate, internally tied to PGND 5 BOOT Supply for the high−side MOSFET gate driver. A capacitor from BOOT to PHASE supplies the charge to turn on the N−channel high−side MOSFET. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 6 NC 7 PHASE No connect 8~11 VIN Power input for the power stage 12~15, 28 PGND Power return for the power stage 16~26 SW Switching node junction between high−side and low−side MOSFETs; also input to the gate driver SW node comparator and input into the ZCD comparator 27, 33 GL Gate Low, Low−side MOSFET gate monitor 29 PVCC Return connection for the boot capacitor, internally tied to SW node Power supply input for LS (Note1) gate driver and boot diode 30 THWN# 125°C Thermal Warning Flag – pulls LOW upon detection of 125°C thermal warning pre− set temperature 31 EN / FAULT# Dual−functionality, enable input to the gate driver IC. FAULT# − internal pull−down physically pulls this pin LOW upon detection of fault condition (HS (Note 2) MOSFET short or 150°C THDN). 1. LS = Low Side 2. HS = High Side www.onsemi.com 3 FDMF5833 DIAGRAMS V5V PVCC EN VIN CVCC RVCC CPVCC VCC CVIN VIN GL EN/FAULT# RBOOT PWM Input BOOT PWM CBOOT FD M F5833 OFF ON ZCD# PHASE THWN# SW LOUT THWN# AGND VOUT PGND COUT Figure 2. Typical Application Diagram EN/ FAULT# PVCC BOOT VIN THWN# 0.8 V/ 2.0 V FAULT LATCH VCC THWN / THDN FAULT VCC PHASE LEVEL SHIFT EN/UVLO HDRV POR RUP_ PWM PWM SW PWM INPUT PVCC PWM CONTROL LOGIC RDN_ PWM LDRV1 PVCC POR VCC GL LDRV2 10 mA ZCD/CCM/DCM LOGIC ZCD# 0.8 V/ 2.0 V AGND Figure 3. Functional Block Diagram www.onsemi.com 4 PGND FDMF5833 ABSOLUTE MAXIMUM RATINGS (TA = TJ = 25°C) Value Ratings Unit Supply Voltage Parameter Referenced to AGND −0.3 6.0 V Drive Voltage Referenced to AGND −0.3 6.0 V Output Enable / Disable Referenced to AGND −0.3 6.0 V VPWM PWM Signal Input Referenced to AGND −0.3 VCC+0.3 V VZCD# ZCD Mode Input Referenced to AGND −0.3 6.0 V Low Gate Manufacturing Test Pin Referenced to AGND (DC Only) −0.3 6.0 V Referenced to AGND, AC < 20 ns −3.0 6.0 Thermal Warning Referenced to AGND −0.3 6.0 V Power Input Referenced to PGND, AGND −0.3 30.0 V PHASE Referenced to PGND, AGND (DC Only) −0.3 30.0 V Referenced to PGND, AC < 20 ns −7.0 35.0 Referenced to PGND, AGND (DC Only) −0.3 30.0 Referenced to PGND, AC < 20 ns −7.0 35.0 Referenced to AGND (DC Only) −0.3 35.0 Referenced to AGND, AC < 20 ns −5.0 40.0 Boot to PHASE Voltage Referenced to PVCC −0.3 6.0 V IO(AV) (Note3) Output Current fSW = 300 kHz, VIN = 12 V, VOUT = 1.8 V − 50 A fSW = 1 MHz, VIN = 12 V, VOUT = 1.8 V − 45 IFAULT EN / FAULT# Sink Current Symbol VCC PVCC VEN/FAULT# VGL VTHWN# VIN VPHASE VSW VBOOT VBOOT−PHASE DJ−A DJ−PCB Switch Node Input Bootstrap Supply Value V V −0.1 7.0 mA Junction−to−Ambient Thermal Resistance − 12.4 °C/W Junction−to−PCB Thermal Resistance (under ON Semiconductor SPS Thermal Board) − 1.8 °C/W −40 +125 °C +150 °C −55 +150 °C Human Body Model, ANSI/ESDA/JEDEC JS−001−2012 3000 − V Charged Device Model, JESD22−C101 2500 − TA Ambient Temperature Range TJ Maximum Junction Temperature TSTG Storage Temperature Range ESD Electrostatic Discharge Protection Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3. IO(AV) is rated with testing ON Semiconductor’s SPS evaluation board at TA = 25°C with natural convection cooling. This rating is limited by the peak SPS temperature, TJ = 150°C, and varies depending on operating conditions and PCB layout. This rating may be changed with different application settings. RECOMMENDED OPERATING CONDITIONS Symbol VCC PVCC VIN Min Typ Max Unit Control Circuit Supply Voltage Parameter 4.5 5.0 5.5 V Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V 4.5 (Note 4) 19.0 24.0 (Note 5) V Output Stage Supply Voltage Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 4. 3.0 V VIN is possible according to the application condition. 5. Operating at high VIN can create excessive AC voltage overshoots on the SW−to−GND and BOOT−to−GND nodes during MOSFET switching transient. For reliable SPS operation, SW to GND and BOOT to GND must remain at or below the Absolute Maximum Ratings in the table above. www.onsemi.com 5 FDMF5833 ELECTRICAL CHARACTERISTICS (Typical value is under VIN = 12 V, VCC = PVCC = 5 V and TA = TJ = +25°C unless otherwise noted. Minimum and maximum values are under VIN = 12 V, VCC = PVCC = 5 V ±10% and TJ = TA = −40°C ~ +125°C) Parameter Symbol Test Conditions Min Typ Max Unit BASIC OPERATION VF Forward−Voltage Drop IF = 10 mA − 0.4 − V IQ Quiescent Current IQ = IVCC + IPVCC, EN = HIGH, PWM = LOW or HIGH or Float (Non−Switching) − − 2 mA ISHDN Shutdown Current ISHDN = IVCC + IPVCC, EN = GND − − 3 mA VUVLO UVLO Threshold VCC Rising 3.5 3.8 4.1 V VUVLO_HYST UVLO Hysteresis − 0.4 − V − − 20 ms tD_POR POR Delay to Enable IC VCC UVLO Rising to Internal PWM Enable EN INPUT VIH_EN High−Level Input Voltage 2.0 − − V VIL_EN Low−Level Input Voltage − − 0.8 V RPLD_EN Pull−Down Resistance − 250 tPD_ENL EN LOW Propagation Delay PWM = GND, EN Going LOW to GL Going LOW − 25 − ns tPD_ENH EN HIGH Propagation Delay PWM = GND, EN Going HIGH to GL Going HIGH − − 69 ms kW ZCD# INPUT VIH_ZCD# High−Level Input Voltage 2.0 − − V VIL_ZCD# Low−Level Input Voltage − − 0.8 V IPLU_ZCD# Pull−Up Current − 10 − mA tPD_ZLGLL ZCD# LOW Propagation Delay PWM = GND, ZCD# Going LOW to GL Going LOW (assume IL ≤ 0) − 10 − ns tPD_ZHGLH ZCD# HIGH Propagation Delay PWM = GND, ZCD# Going HIGH to GL Going HIGH − 10 − ns RUP_PWM Pull−Up Impedance − 10 − kW RDN_PWM Pull−Down Impedance − 10 − kW VIH_PWM PWM High Level Voltage Typical Values: TA = TJ = 25°C VCC = PVCC = 5 V Min. / Max. Values: TA = TJ = −40°C to 125°C VCC = PVCC = 5 V ±10% 3.8 − − V PWM INPUT VTRI_Window 1.2 − 3.1 V PWM Low Level Voltage − − 0.8 V tD_HOLD−OFF 3−State Shut−Off Time − 90 130 ns VHIZ_PWM 3−State Open Voltage 2.1 2.5 2.9 V Minimum PWM HIGH Pulse Required for SW Node to Switch from GND to VIN 30 − − ns Minimum GL HIGH Time when LOW VBOOT−SW detected and PWM LOW ≤ 100 ns − 100 − ns VIL_PWM 3−State Window MINIMUM CONTROLLABLE ON−TIME tMIN_PWM_ON PWM Minimum Controllable On−Time FORCED MINIMUM GL HIGH TIME tMIN_GL_HIGH Forced Minimum GL HIGH PWM INPUT PROPAGATION DELAYS AND DEAD TIMES (VIN = 12 V, VCC = PVCC = 5 V, fsw = 1 MHz, IOUT = 20 A, TA = 25°C) tPD_PHGLL PWM HIGH Propagation Delay PWM Going HIGH to GL Going LOW, VIH_PWM to 90% GL − 15 − ns tPD_PLGHL PWM LOW Propagation Delay PWM Going LOW to GH (Note 6) Going LOW, VIL_PWM to 90% GH − 30 − ns www.onsemi.com 6 FDMF5833 ELECTRICAL CHARACTERISTICS (continued) (Typical value is under VIN = 12 V, VCC = PVCC = 5 V and TA = TJ = +25°C unless otherwise noted. Minimum and maximum values are under VIN = 12 V, VCC = PVCC = 5 V ±10% and TJ = TA = −40°C ~ +125°C) Symbol Parameter Test Conditions Min Typ Max Unit PWM INPUT PROPAGATION DELAYS AND DEAD TIMES (VIN = 12 V, VCC = PVCC = 5 V, fsw = 1 MHz, IOUT = 20 A, TA = 25°C) tPD_PHGHH PWM LOW Propagation Delay (ZCD# Held LOW) PWM Going HIGH to GH Going HIGH, VIH_PWM to 10% GH (ZCD# = LOW, IL = 0, assumes DCM) − 10 − ns tD_DEADON LS Off to HS On Dead Time GL Going LOW to GH Going HIGH, 10% GL to 10% GH, PWM Transition LOW to HIGH (See Figure 29) − 10 − ns tD_DEADOFF HS Off to LS On Dead Time GH Going LOW to GL Going HIGH, 10% GH to 10% GL, PWM Transition HIGH to LOW (See Figure 29) − 5 − ns tR_GH_20A GH Rise Time under 20 A IOUT 10% GH to 90% GH, IOUT = 20 A − 9 − ns tF_GH_20A GH Fall Time under 20 A IOUT 90% GH to 10% GH, IOUT = 20 A − 9 − ns tR_GL_20A GL Rise Time under 20 A IOUT 10% GL to 90% GL, IOUT = 20 A − 9 − ns tF_GL_20A GL Fall Time under 20 A IOUT 90% GL to 10% GL, IOUT = 20 A − 6 − ns tPD_TSGHH Exiting 3−State Propagation Delay PWM (from 3−State) Going HIGH to GH Going HIGH, VIH_PWM to 10% GH − − 45 ns tPD_TSGLH Exiting 3−State Propagation Delay PWM (from 3−State) Going LOW to GL Going HIGH, VIL_PWM to 10% GL − − 45 ns Output Impedance, Sourcing Source Current = 100 mA − 0.68 − W Output Impedance, Sinking Sink Current = 100 mA − 0.9 − W tR_GH GH Rise Time 10% GH to 90% GH, CLOAD = 1.3 nF − 4 − ns tF_GH GH Fall Time 90% GH to 10% GH, CLOAD = 1.3 nF − 3 − ns HIGH−SIDE DRIVER (HDRV, VCC = PVCC = 5 V) RSOURCE_GH RSINK_GH WEAK LOW−SIDE DRIVER (LDRV2 Only under CCM2 Mode Operation, VCC = PVCC = 5 V) RSOURCE_GL Output Impedance, Sourcing Source Current = 100 mA − 0.82 − W ISOURCE_GL Output Sourcing Peak Current GL = 2.5 V − 2 − A RSINK_GL Output Impedance, Sinking Sink Current = 100 mA − 0.86 − W ISINK_GL Output Sinking Peak Current GL = 2.5 V − 2 − A 0.47 − W LOW−SIDE DRIVER (Paralleled LDRV1 + LDRV2 under CCM1 Mode Operation, VCC = PVCC = 5 V) RSOURCE_GL Output Impedance, Sourcing Source Current = 100 mA − ISOURCE_GL Output Sourcing Peak Current GL = 2.5 V − 4 − A RSINK_GL Output Impedance, Sinking Sink Current = 100 mA − 0.29 − W ISINK_GL Output Sinking Peak Current GL = 2.5 V − 7 − A tR_GL GL Rise Time 10% GL to 90% GL, CLOAD = 7.0 nF − 9 − ns tF_GL GL Fall Time 90% GL to 10% GL, CLOAD = 7.0 nF − 6 − ns Measured on the driver IC with TJ = TA − 125 − °C − 110 − °C IPLD_THWN = 1 mA − 100 − W THERMAL WARNING FLAG (125°C) TACT_THWN_125 Activation Temperature TRST_THWN_125 Reset Temperature RPLD_THWN Pull−Down Resistance THERMAL SHUTDOWN (150°C) TACT_THDN Activation Temperature Measured on the driver IC with TJ = TA − 150 − °C RPLD_EN−THDN Pull−Down Resistance IPLD_EN−THDN = 1 mA − 50 − W www.onsemi.com 7 FDMF5833 ELECTRICAL CHARACTERISTICS (continued) (Typical value is under VIN = 12 V, VCC = PVCC = 5 V and TA = TJ = +25°C unless otherwise noted. Minimum and maximum values are under VIN = 12 V, VCC = PVCC = 5 V ±10% and TJ = TA = −40°C ~ +125°C) Symbol Parameter Test Conditions Min Typ Max Unit CATASTROPHIC FAULT (SW Monitor) VSW_MON SW Monitor Reference Voltage − 1.3 2 V tD_FAULT Propagation Delay to Pull EN / FAULT# Signal = LOW − 20 − ns BOOT DIODE VF Forward−Voltage Drop IF = 10 mA − 0.4 − V VR Breakdown Voltage IR = 1 mA 30 − − V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. GH = Gate High, internal gate pin of the high−side MOSFET. TYPICAL PERFORMANCE CHARACTERISTICS 55 55 50 50 45 45 40 Module Output Current, I OUT [A] Module Output Current, I OUT [A] Test Conditions: VIN = 12 V, VCC = PVCC = 5 V, VOUT = 1.8 V, LOUT = 250 nH, TA = 25°C and natural convection cooling, unless otherwise noted. FSW = 300 kHz 35 FSW = 1000 kHz 30 25 20 15 10 5 40 0 25 50 75 100 PCB Temperature, T PCB [oC] FSW = 1000 kHz 30 25 20 15 10 5 VIN = 12 V, PVCC & VCC = 5 V, VOUT = 1.8 V 0 FSW = 300 kHz 35 VIN = 19 V, PVCC & VCC = 5 V, VOUT = 1.8 V 0 125 150 0 25 Figure 4. Safe operating Area 12 VIN 11 12Vin, 300 kHz 11 PVCC & VCC = 5 V, VOUT = 1.8 V 12Vin, 800 kHz 8 150 19Vin, 300 kHz PVCC & VCC = 5 V, VOUT = 1.8 V 10 12Vin, 500 kHz 9 125 Figure 5. Safe operating Area 19 VIN Module Power Loss, PL MOD [W] Module Power Loss, PL MOD [W] 10 50 75 100 PCB Temperature, T PCB [oC] 12Vin, 1000 kHz 7 6 5 4 3 2 1 0 19Vin, 500 kHz 9 19Vin, 800 kHz 8 19Vin, 1000 kHz 7 6 5 4 3 2 1 0 0 5 10 15 20 25 30 35 40 Module Output Current, I OUT [A] 45 50 55 0 Figure 6. Power Loss vs. Output Current with 12 VIN 5 10 15 20 25 30 35 40 Module Output Current, I OUT [A] 45 50 Figure 7. Power Loss vs. Output Current with 19 VIN www.onsemi.com 8 55 FDMF5833 TYPICAL PERFORMANCE CHARACTERISTICS Test Conditions: VIN = 12 V, VCC = PVCC = 5 V, VOUT = 1.8 V, LOUT = 250 nH, TA = 25°C and natural convection cooling, unless otherwise noted. 1.20 1.4 VIN = 12 V, PVCC & VCC = 5 V, VOUT = 1.8 V, IOUT = 30 A PVCC & VVCC = 5 V, VOUT = 1.8 V, FSW = 500 kHz, IOUT = 30 A Normalized Module Power Loss Normalized Module Power Loss 1.3 1.2 1.1 1.0 0.9 0.8 200 300 400 500 600 700 800 900 Module Switching Frequency, FSW [kHz] 1000 1.15 1.10 1.05 1.00 0.95 1100 4 6 Figure 8. Power Loss vs. Switching Frequency 18 20 1.6 VIN = 12 V, PVCC & VVCC = 5 V, FSW = 500 kHz, IOUT = 30 A VIN = 12 V, VOUT = 1.8 V, FSW = 500 kHz, IOUT = 30 A 1.10 1.5 Normalized Module Power Loss Normalized Module Power Loss 10 12 14 16 Module Input Voltage, V IN [V] Figure 9. Power Loss vs. Input Voltage 1.12 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 4.0 4.5 5.0 5.5 Driver Supply Voltage, PV CC & V CC [V] 1.4 1.3 1.2 1.1 1.0 0.9 6.0 0.5 1.0 Figure 10. Power Loss vs. Driver Supply Voltage 1.002 0.045 Driver Supply Current, I PVCC + I VCC [A] 0.998 0.996 0.994 0.992 0.990 0.988 0.986 200 250 300 350 400 Output Inductor, L OUT [nH] 450 1.5 2.0 2.5 Module Output Voltage, V OUT [V] 3.0 3.5 Figure 11. Power Loss vs. Output Voltage VIN = 12 V,PVCC & VVCC = 5 V, FSW = 500 kHz, VOUT = 1.8 V, IOUT = 30 A 1.000 Normalized Module Power Loss 8 VIN = 12 V,PVCC & VCC = 5 V, VOUT = 1.8 V, IOUT = 0 A 0.04 0.035 0.03 0.025 0.02 0.015 0.01 200 500 Figure 12. Power Loss vs. Output Inductor 300 400 500 600 700 800 900 1000 Module Switching Frequency, F SW [kHz] 1100 Figure 13. Driver Supply Current vs. Switching Frequency www.onsemi.com 9 FDMF5833 TYPICAL PERFORMANCE CHARACTERISTICS Test Conditions: VIN = 12 V, VCC = PVCC = 5 V, VOUT = 1.8 V, LOUT = 250 nH, TA = 25°C and natural convection cooling, unless otherwise noted. 1.06 0.026 VIN = 12 V, PVCC & VVCC = 5 V, VOUT = 1.8 V 1.04 0.024 Normalized Driver Supply Current Driver Supply Current, I PVCC + I VCC [A] VIN = 12 V, VOUT = 1.8 V, FSW = 500 kHz, IOUT = 0 A 0.022 0.02 0.018 0.016 4.0 4.5 5.0 5.5 Driver Supply Voltage, PV CC & V VCC [V] 1.02 1.00 0.98 0.96 FSW = 300 kHz 0.94 0.92 0.90 6.0 0 Figure 14. Driver Supply Current vs. Driver Supply Voltage 5 10 15 20 25 30 35 40 Module Output Current, I OUT [A] 45 50 55 Figure 15. Driver Supply Current vs. Output Current 4.0 4.0 TA = 25 C PWM Threshold Voltage, V PWM [V] UVLOUP 3.9 Driver Supply Voltage, V CC [V] FSW = 1000 kHz 3.8 3.7 3.6 3.5 UVLODN 3.4 VIH_PWM 3.5 VTRI_HI 3.0 2.5 VHIZ_PWM 2.0 1.5 VTRI_LO 1.0 VIL_PWM 0.5 4.50 3.3 −55 0 25 55 100 Driver IC Junction Temperature, T J [oC] 125 Figure 16. UVLO Threshold vs. Temperature 1.8 VCC = 5 V VIH_PWM 3.5 3.0 2.5 VHIZ_PWM 2.0 1.5 VTRI_LO 1.0 VIL_PWM 0.5 0 25 55 100 Driver IC Junction Temperature, T J [oC] TA = 25 C 1.7 VTRI_HI −55 5.50 Figure 17. PWM Threshold vs. Driver Supply Voltage ZCD# Threshold Voltage, V ZCD# [V] PWM Threshold Voltage, V PWM [V] 4.0 4.75 5.00 5.25 Driver Supply Voltage, V CC [V] VIH_ZCD# 1.6 1.5 1.4 1.3 1.2 VIL_ZCD# 1.1 1.0 4.50 125 Figure 18. PWM Threshold vs. Temperature 4.75 5.00 5.25 Driver Supply Voltage, V CC [V] 5.50 Figure 19. ZCD# Threshold vs. Driver Supply Voltage www.onsemi.com 10 FDMF5833 TYPICAL PERFORMANCE CHARACTERISTICS Test Conditions: VIN = 12 V, VCC = PVCC = 5 V, VOUT = 1.8 V, LOUT = 250 nH, TA = 25°C and natural convection cooling, unless otherwise noted. ZCD# Threshold Voltage, V ZCD# [V] 1.9 0.22 VCC = 5 V VCC = 5 V ZCD# Pull−Up Current, I PLU [mA] 2 1.8 1.7 1.6 1.5 VIH_ZCD# 1.4 1.3 1.2 VIL_ZCD# 1.1 0.2 0.18 0.16 0.14 0.12 0.1 1 −55 0 25 55 100 −55 125 Driver IC Junction Temperature, T J [oC] Figure 20. ZCD# Threshold vs. Temperature 2.0 TA = 25 C 1.9 1.8 100 125 1.6 1.4 VIL_EN 1.2 4.75 5.00 5.25 Driver Supply Voltage, V CC [V] VCC = 5 V 1.7 1.6 1.5 VIH_EN 1.4 1.3 1.2 VIL_EN 1.1 1.0 5.50 −55 Figure 22. EN Threshold vs. Driver Supply Voltage 0 25 55 100 Driver IC Junction Temperature, T J [oC] 125 Figure 23. EN Threshold vs. Temperature 500 0.43 IF = 10 mA Boot Diode Forward Voltage, V F [mV] VCC = 5 V EN Pull−Down Current, I PLD [mA] 55 1.8 EN Threshold Voltage, V EN [V] EN Threshold Voltage, V EN [V] VIH_EN 1.0 4.50 25 Figure 21. ZCD# Pull−Up Current vs. Temperature 2.2 2.0 0 Driver IC Junction Temperature, T J [oC] 0.42 0.41 0.4 0.39 0.38 450 400 350 300 0.37 −55 0 25 55 100 Driver IC Junction Temperature, T J [oC] −55 125 Figure 24. EN Pull−Down Current vs. Temperature 0 25 55 100 Driver IC Junction Temperature, T J [oC] 125 Figure 25. Boot Diode Forward Voltage vs. Temperature www.onsemi.com 11 FDMF5833 TYPICAL PERFORMANCE CHARACTERISTICS Test Conditions: VIN = 12 V, VCC = PVCC = 5 V, VOUT = 1.8 V, LOUT = 250 nH, TA = 25°C and natural convection cooling, unless otherwise noted. 1.25 PVCC & VCC = 5 V, ZCD# = 5 V, EN = 5 V Driver Quiescent Current, I Q [mA] Driver Shut−Down Current, I SHDN [mA] PVCC & VCC = 5 V, PWM = 0 V, ZCD# = 0 V, EN = 0 V 2 1.5 1 0.5 0 −0.5 −1 1.2 1.15 PWM = 0 V PWM = Float 1.1 PWM = 5 V 1.05 1 0.95 0.9 −55 0 25 55 100 Driver IC Junction Temperature, T J [oC] 125 −55 Figure 26. Driver Shutdown vs. Temperature 0 25 55 100 Driver IC Junction Temperature, T J [oC] 125 Figure 27. Driver Quiescent Current vs. Temperature FUNCTIONAL DESCRIPTION implemented to ensure the internal circuitry is biased, stable, and ready to operate. Two VCC pins are provided: PVCC and VCC. The gate driver circuitry is powered from the PVCC rail. The user connects PVCC to VCC through a low−pass R−C filter. This provides a filtered 5 V bias to the analog circuitry on the IC. The SPS FDMF5833 is a driver−plus−MOSFET module optimized for the synchronous buck converter topology. A PWM input signal is required to properly drive the high−side and the low−side MOSFETs. The part is capable of driving speed up to 1.5 MHz. Power−On Reset (POR) The PWM input stage should incorporate a POR feature to ensure both LDRV and HDRV are forced inactive (LDRV = HDRV = 0) until UVLO > ~3.8 V (rising threshold). After all gate drive blocks are fully powered on and have finished the startup sequence, the internal driver IC EN_PWM signal is released HIGH, enabling the driver outputs. Once the driver POR has finished (< 20 ms maximum), the driver follows the state of the PWM signal (it is assumed that at startup the controller is either in a high−impedance state or forcing the PWM signal to be within the driver 3−state window). Three conditions below must be supported for normal startup / power−up. • VCC rises to 5 V, then EN goes HIGH: • EN pin is tied to the VCC pin: • EN is commanded HIGH prior to 5 V VCC reaching the UVLO rising threshold. The POR method is to increase the VCC over than UVLO > rising threshold and EN = HIGH. Driver State Enable Disable 3. 4 3. 8 VCC [ V] * EN pin keeps HIGH Figure 28. UVLO on VCC EN / FAULT# (Enable / Fault Flag) The driver can be disabled by pulling the EN / FAULT# pin LOW (EN < VIL_EN), which holds both GL and GH LOW regardless of the PWM input state. The driver can be enabled by raising the EN / FAULT# pin voltage HIGH (EN > VIH_EN). The driver IC has less than 3 mA shutdown current when it is disabled. Once the driver is re−enabled, it takes a maximum of 20 ms startup time. EN / FAULT# pin is an open−drain output for fault flag with an internal 250 kW pull−down resistor. Logic HIGH signal from PWM controller or ~10 kW external pull−up resistor from EN / FAULT# pin to VCC is required to start driver operation. Under−Voltage Lockout (UVLO) UVLO is performed on VCC only, not on PVCC or VIN. When the EN is set HIGH and VCC is rising over the UVLO threshold level (3.8 V), the part starts switching operation after a maximum 20 ms POR delay. The delay is www.onsemi.com 12 FDMF5833 3−State PWM Input Table 1. UVLO AND DRIVER STATE UVLO EN 0 X Disabled (GH & GL = 0) 1 0 Disabled (GH & GL = 0) 1 1 Enabled (see Table 2) 1 Open The FDMF5833 incorporates a 3−state 5 V PWM input gate drive design. The 3−state gate drive has both logic HIGH and LOW levels, along with a 3−state shutdown window. When the PWM input signal enters and remains within the 3−state window for a defined hold−off time (t ), D_HOLD−OFF both GL and GH are pulled LOW. This feature enables the gate drive to shut down both the high−side and the low−side MOSFETs to support features such as phase shedding, a common feature on multi−phase voltage regulators. Driver State Disabled (GH & GL = 0) The EN / FAULT# pin has two functions; enabling / disabling driver and fault flag. The fault flag signal is active LOW. When the driver detects a fault condition during operation, it turns on the open−drain on the EN / FAULT# pin and the pin voltage is pulled LOW. The fault conditions are: • High−side MOSFET false turn−on or VIN ~ SW short during low−side MOSFET turn on: • THDN by 150°C of driver TJ. When the driver detects a fault condition and disables itself, a POR event on VCC is required to restart the driver operation. Table 2. EN / PWM / 3−STATE / ZCD# LOGIC STATES EN PWM ZCD# GH GL 0 X X 0 0 1 3−State X 0 0 1 0 0 0 1 (IL > 0), 0 (IL < 0) 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 VIH_PWM VIL_PWM PWM GL GH−PHASE (intenal) 90% 90% 10% 10% 90% 90% 10% 10% BOOT−GND PVCC − VF_DBOOT − 1 V 90% SW tPD_PHGLL tD_DEADON tRISE_GH tFALL_GL tPD_PLGHL tD_DEADOFF tRISE_GL tFALL_GH tPD_PLGLH tPD_PHGLL = PWM HI to GL LO, VIH_PWM to 90% GL tFALL_GL = 90% GL to 10% GL tD_DEADON = LS Off to HS On Dead Time, 10% GL to VBOOT−GND ≤ PVCC − VF_DBOOT − 1V or BOOT−GND dip start point tRISE_GH = 10% GH to 90% GH, VBOOT−GND ≤ PVCC − VF_DBOOT − 1V or BOOT−GND dip start point to GL bounce start point tPD_PLGHL = PWM LO to GH LO, VIL_PWM to 90% GH or BOOT−GND decrease start point, tPD_PLGLH − tD_DEADOFF − tFALL_GH tFALL_GH = 90% GH to 10% GH, BOOT−GND decrease start point to 90% VSW or GL dip start point tD_DEADOFF = HS Off to LS On Dead Time, 90% VSW or GL dip start point to 10% GL tRISE_GL = 10% GL to 90% GL tPD_PLGLH = PWM LO to GL HI, VIL_PWM to 10% GL Figure 29. PWM Timing Diagram www.onsemi.com 13 FDMF5833 (7) (7) V IH_PWM (11) V IH_PWM V TRI_HI V TRI_HI (9) V TRI_LO (10) V TRI_LO V IL_PWM PWM V IL_PWM (12) 3−State Window 3−State Window (8) (8) GH−PHASE GL Figure 30. PWM Threshold Definition NOTE: 7. The timing diagram in Figure 30 assumes very slow ramp on PWM. 8. Slow ramp of PWM implies the PWM signal remains within the 3−state window for a time >>> tD_HOLD−OFF. 9. VTRI_HI = PWM trip level to enter 3−state on PWM falling edge. 10. VTRI_LO = PWM trip level to enter 3−state on PWM rising edge. 11. VIH_PWM = PWM trip level to exit 3−state on PWM rising edge and enter the PWM HIGH logic state. 12. VIL_PWM = PWM trip level to exit 3−state on PWM falling edge and enter the PWM LOW logic state. Power Sequence through the internal bootstrap diode. When the PWM input goes HIGH, HDRV begins to charge the gate of the high−side MOSFET (internal GH pin). During this transition, the charge is removed from the CBOOT and delivered to the gate of Q1. As Q1 turns on, SW rises to VIN, forcing the BOOT pin to VIN + VBOOT, which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling HDRV to SW. CBOOT is then recharged to PVCC when the SW falls to PGND. HDRV output is in phase with the PWM input. The high−side gate is held LOW when the driver is disabled or the PWM signal is held within the 3−state window for longer than the 3−state hold−off time, tD_HOLD−OFF. SPS FDMF5833 requires four (4) input signals to conduct normal switching operation: VIN, VCC / PVCC, PWM, and EN. PWM should not be applied before VCC and the amplitude of PWM should not be higher than VCC. All other combinations of their power sequences are allowed. The below example of a power sequence is for a reference application design: • From no input signals ♦ VIN On: Typical 12 VDC ♦ VCC / PVCC On: Typical 5 VDC ♦ EN HIGH: Typical 5 VDC ♦ PWM Signaling: 5 V HIGH / 0 V LOW The VIN pins are tied to the system main DC power rail. PVCC and VCC pins are tied together to supply gate driving and logic circuit powers from the system VCC rail. Or the PVCC pin can be directly tied to the system VCC rail, and the VCC pin is powered by PVCC pin through a filter resistor located between PVCC pin and VCC pin. The filter resistor reduces switching noise impact from PVCC to VCC. The EN pin can be tied to the VCC rail with an external pull−up resistor and it will maintain HIGH once the VCC rail turns on. Or the EN pin can be directly tied to the PWM controller for other purposes. Low−Side Driver The low−side driver (LDRV) is designed to drive the gate−source of a ground−referenced, low−RDS(ON), N−channel MOSFET (Q2). The bias for LDRV is internally connected between the PVCC and AGND. When the driver is enabled, the driver output is 180° out of phase with the PWM input. When the driver is disabled (EN = 0 V), LDRV is held LOW. Continuous Current Mode 2 (CCM2) Operation A main feature of the low−side driver design in SPS FMDF5833 is the ability to control the part of the low− side gate driver upon detection of negative inductor current, called CCM2 operation. This is accomplished by using the ZCD comparator signal. The primary reason for scaling back on the drive strength is to limit the peak VDS stress when the low−side MOSFET hard−switches inductor current. This peak VDS stress has been an issue with High−Side Driver The high−side driver (HDRV) is designed to drive a floating N−channel MOSFET (Q1). The bias voltage for the high−side driver is developed by a bootstrap supply circuit, consisting of the internal Schottky diode and external bootstrap capacitor (CBOOT). During startup, the SW node is held at PGND, allowing CBOOT to charge to PVCC www.onsemi.com 14 FDMF5833 CCM2 alters the gate drive impedance while operating the power MOSFETs in a different mode versus CCM1 / DCM. Altered dead−time operation must be considered. applications with large amounts of load transient and fast and wide output voltage regulation. The MOSFET gate driver in SPS FDMF5833 operates in one of three modes, described below. Low−Side MOSFET Off to High−Side MOSFET On Dead Time in CCM1 / DCM To prevent overlap during the low−side MOSFET off to high−side MOSFET on switching transition, an adaptive circuitry monitors the voltage at the GL pin. When the PWM signal goes HIGH, GL goes LOW after a propagation delay (tPD_PHGLL). Once the GL pin is discharged below ~ 1 – 2 V, GH is pulled HIGH after an adaptive delay, tD_DEADON. Some situations where the ZCD# rising−edge signal leads the PWM rising edge by tens of nanoseconds, can cause GH and GL overlap. This event can occur when the PWM controller sends PWM and ZCD# signals that lead, lag, or are synchronized. To avoid this phenomenon, a secondary fixed propagation delay (tFD_ON1) is added to ensure there is always a minimum delay between low−side MOSFET off to high−side MOSFET on. Continuous Current Mode 1 (CCM1) with Positive Inductor Current In this mode, inductor current is always flowing towards the output capacitor, typical of a heavily loaded power stage. The high−side MOSFET turns on with the low−side body diode conducting inductor current and SW is approximately VF below ground, meaning hard−switched turn on and off the high−side MOSFET. Discontinuous Current Mode (DCM) Typical of lightly loaded power stage; the high−side MOSFET turns on with zero inductor current, ramps the inductor current, then returns to zero every switching cycle. When the high−side MOSFET turns on under DCM operation, the SW node may be at any voltage from a VF below ground to a VF above VIN. This is because after the low−side MOSFET turns off, the SW node capacitance resonates with the inductor current. The level shifter in driver IC should be able to turn on the high−side MOSFET regardless of the SW node voltage. In this case, the high−side MOSFET turns off a positive current. During this mode, both LDRV1 and LDRV2 operate in parallel and the low−side gate driver pull−up and pull− down resistors are operating at full strength. Low−Side MOSFET Off to High−Side MOSFET On Dead Time in CCM2 As noted in the CCM2 Operation section, the low−side driver strength is scale−able upon detection of CCM2. CCM2 feature slows the charge and discharge of the low−side MOSFET gate to minimize peak switching voltage overshoots during low−side MOSFET hardswitching (negative inductor current). To avoid cross− conduction, the slowing of the low−side gate also requires an adjustment (increase) of the dead time between low−side MOSFET off to high−side MOSFET on. A fairly long fixed dead time (tFD_ON2) is implemented to ensure there is no cross conduction during this CCM2 operation. Continuous Current Mode 2 (CCM2) with Negative Inductor Current This mode is typical in a synchronous buck converter pulling energy from the output capacitors and delivering the energy to the input capacitors (Boost Mode). In this mode, the inductor current is negative (meaning towards the MOSFETs) when the low−side MOSFET is turned off (may be negative when the high−side MOSFET turns on as well). This situation causes the low−side MOSFET to hard switch while the high−side MOSFET acts as a synchronous rectifier (temporarily operated in synchronous Boost Mode). During this mode, only the “weak” LDRV2 is used for low−side MOSFET turn−on and turn−off. The intention is to slow down the low−side MOSFET switching speed when it is hard switching to reduce peak VDS stress. High−Side MOSFET Off to Low−Side MOSFET On Dead Time in CCM1 / DCM To get very short dead time during high−side MOSFET off to low−side MOSFET on transition, a fixed dead time method is implemented in the SPS gate driver. The fixed−dead−time circuitry monitors the internal HS signal and adds a fixed delay long enough to gate on GL after a desired tD_DEADOFF (~5 ns, tD_DEADOFF = tFD_OFF1) regardless of SW node state. Exiting 3−State Condition When exiting a valid 3−state condition, the gate driver of the FDMF5833 follows the PWM input command. If the PWM input goes from 3−state to LOW, the low−side MOSFET is turned on. If the PWM input goes from 3− state to HIGH, the high−side MOSFET is turned on. This is illustrated in Figure 31 below. Dead−Times in CCM1 / DCM / CCM2 The driver IC design ensures minimum MOSFET dead times, while eliminating potential shoot−through (cross− conduction) currents. To ensure optimal module efficiency, body diode conduction times must be reduced to the low nano−second range during CCM1 and DCM operation. www.onsemi.com 15 FDMF5833 V IH_PWM V IH_PWM PWM V IL_PWM V IH_PWM VTRI_HI V TRI_HI V TRI_LO 3−State Window V IL_PWM V IL_PWM 90% GH to SW GL V TRI_HI V TRI_LO 10% 10% 90% 90% 10% tPD_PHGLL tD_DEADON 10% 10% tPD_PLGHL 10% tPD_THGHH tPD_PHGLL tD_DEADON2 tD_DEADOFF 10% tPD_TLGLH tD_HOLD−OFF tD_HOLD−OFF 3−State GL / GH t HOLD_OFF off Window 3−State GL / GH t HOLD_OFF off Window SW Inductor Current Less than tD_HOLD−OFF Less than tD_HOLD−OFF NOTES: tPD_XXX = propagation delay from external signal (PWM, ZCD#, etc.) to IC generated signal. Example : tPD_PHGLL – PWM going HIGH to low−side MOSFET VGS (GL) going LOW tD_XXX = delay from IC generated signal to IC generated signal. Example : tD_DEADON – low−side MOSFET VGS LOW to high−side MOSFET VGS HIGH PWM tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (ZCD# held LOW) ZCD# tPD_ZLGLL = ZCD# fall to LS VGS fall, VIL_ZCD# to 90% LS VGS tPD_ZHGLH = ZCD# rise to LS VGS rise, VIH_ZCD# to 10% LS VGS Exiting 3−State tPD_TSGHH = PWM 3−State to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS tPD_TSGLH = PWM 3−State to LOW to LS VGS rise, VIL_PWM to 10% LS VGS Dead Times tD_DEADON = LS VGS fall to HS VGS rise, LS−Comp trip value to 10% HS VGS tD_DEADOFF = SW fall to LS VGS rise, SW−Comp trip value to 10% LS VGS Figure 31. PWM HIGH / LOW / 3−State Timing Diagram Exiting 3−State with Low BOOT−SW Voltage BOOT−SW voltage, a 100 ns minimum GL on time is output regardless of the PWM input. This ensures the boot capacitor is adequately charged to a safe operating level and has minimal impact on transient response of the system. Scenarios of exiting 3−state condition are listed below. • If the part exits 3−state with a low BOOT−SW voltage condition and the controller commands PWM=HIGH, the SPS outputs a 100 ns GL pulse and follows the PWM=HIGH command (see Figure 32). • If the part exits 3−state with a low BOOT−SW voltage condition and the controller commands PWM=LOW for 100 ns or more, the SPS follows the PWM input. If PWM=LOW for less than 100 ns, GL remains on for 100 ns then follows the PWM input (see Figure 33 and Figure 34). The SPS module is used in multi−phase VR topologies requiring the module to wait in 3−state condition for an indefinite time. These long idle times can bleed the boot capacitor down until eventual clamping occurs based on PVCC and VOUT. Low BOOT−SW can cause increased propagation delays in the level−shift circuit as well as all HDRV floating circuitry, which is biased from the BOOT−SW rail. Another issue with a depleted BOOT−SW capacitor voltage is the voltage applied to the HS MOSFET gate during turn−on. A low BOOT−SW voltage results in a very weak HS gate drive, hence, much larger HS RDS(ON) and increased risk for unreliable operation since the HS MOSFET may not turn−on if BOOT−SW falls too low. To address this issue, the SPS monitors for a low BOOT−SW voltage when the module is in 3−state condition. When the module exits 3−state condition with a low www.onsemi.com 16 FDMF5833 • If no low BOOT−SW condition is detected, the SPS This adaptive dead time mode lasts for no more than two (2) consecutive switching cycles, giving the boot capacitor ample time to recharge to a safe level. The module switches back to fixed dead time control for maximum efficiency. follows the PWM command when exiting 3−state (see Figure 35). The SPS momentarily stays in an adaptive dead time mode when exiting 3−state condition or at initial power−up. PWM LOW > 100 ns VIH_PWM PWM PWM GH to PHASE GH to PHASE GL GL LOW BOOT−SW detect GL / GH off 100 ns GL pulse > 100 ns GL pulse Low BOOT−SW voltage detected Figure 32. Low BOOT−SW Voltage Detected and PWM from 3−State to HIGH Figure 33. Low BOOT−SW Voltage Detected and PWM from 3−State to LOW for more than 100 ns PWM LOW < 100 ns VIH_PWM VIL_PWM I VIL_PWM PWM GH to PHASE GH to PHASE GL LOW BOOT−SW detect GL / GH off LOW BOOT−SW detect Low BOOT−SW voltage detected PWM VIL_PWM GL GL / GH off 100 ns GL pulse LOW BOOT−SW detect Low BOOT−SW voltage detected GL / GH off GL / GH off Low BOOT−SW voltage NOT detected Figure 34. Low BOOT−SW voltage Detected and PWM from 3−State to LOW for Less than 100 ns Figure 35. Low BOOT−SW Voltage NOT Detected and PWM from 3−State to HIGH or LOW www.onsemi.com 17 FDMF5833 Zero Cross Detect (ZCD) Operation negative offset is to ensure the inductor current never reverses; some small body−diode conduction is preferable to having negative current. The comparator is switched on after the rising edge of the low−side gate drive and turned off by the signal at the input to the low−side gate driver. In this way, the zero−current comparator is connected with a break−before−make connection, allowing the comparator to be designed with all low−voltage transistors. The ZCD control block houses the circuitry that determines when the inductor current reverses direction and controls when to turn off the low−side MOSFET. A low offset comparator monitors the SW−to−PGND voltage of the low−side MOSFET during the LS MOSFET on−time. When the sensed voltage switches polarity from negative to positive, the comparator changes state and reverse current has been detected. This comparator offset must sense the negative VSW within a 0.5 mV worst−case range. The VIH_ZCD# ZCD# PWM VIL_ZCD# VIH_PWM VIH_PWM VIH_PWM VIL_PWM 90% GH to SW 10% 90% 90% 90% GL 10% 10% tPD_PHGLL tPD_PLGHL tD_DEADON 90% 10% 10% 10% tPD_PHGLL CCM CCM (Negative inductor current) tPD_PHGHH tPD_ZHGLH Delay from PWM going HIGH to HS VGS HIGH (HS turn−on in DCM) tD_DEADON2 tD_DEADOFF SW tPD_ZCD DCM tPD_ZLGLL Delay from ZCD# going Delay from ZCD# going HIGH to LS VGS HIGH LOW to LS VGS LOW VIN DCM VOUT Inductor Current (simplified slopes) SW (zoom) VZCD_OFF : −0.5 mV CCM operation with positive inductor current DCM operation: Diode Emulation using the GL (LS MOSFET VGS) to eliminate negative inductor current CCM operation with negative inductor current DCM operation: Diode Emulation using the GL (LS MOSFET VGS) to eliminate negative inductor current ZCD# used to control negative inductor current (fault condition) Figure 36. FZCD# & PWM Timing Diagram Thermal Warning Flag (THWN#) Recycling 5 V VCC (POR event) is required to re−enable the driver IC. The FDMF5833 provides a thermal warning (THWN) for over−temperature conditions. The THWN flag pulls THWN# pin LOW (to AGND) if the driver IC detects the 125°C activation temperature. The THWN# pin output returns to high−impedance state once the temperature falls to the 110°C reset temperature. Figure 37 shows the THWN# operation. THWN does not disable the SPS module and works independently of other features. The THWN mode of operation requires a pull−up resistor to VCC rail. THWN# flag is active LOW. VTHWN# [V] 5 0 Thermal Shutdown (THDN) A programmed thermal shutdown engages once the driver TJ reaches 150°C. The shutdown event is a latched shut down, where the THDN signal clocks the fault latch and physically pulls down the EN pin. 110 125 T [°C] * RTHWN# = 10 kW to 5 VCC Figure 37. Gate Driver TJ vs. VTHWN# www.onsemi.com 18 FDMF5833 Catastrophic Fault The 150°C THDN feature is combined with a 125°C THWN# flag. If the driver temperature reaches 125°C, the THWN# pin is pulled LOW. If the driver continues operation and its temperature increases up to 150°C, thermal shutdown is activated. The SPS module is shut down by EN LOW and the THWN# flag is de−asserted, so the VTHWN# returns HIGH. Figure 38 shows the relationship among THWN#, EN, and driver temperature. SPS FDMF5833 includes a catastrophic fault feature. If a HS MOSFET short is detected, the driver internally pulls the EN / FAULT# pin LOW and shuts down the SPS driver. The intention is to implement a basic circuit to test the HS MOSFET short by monitoring LDRV and the state of SW node. If a HS short fault is detected, the SPS module clocks the fault latch shutting down the module. The module requires a VCC POR event to restart. VTHWN# [V] 5 0 VEN [V] 5 0 125 150 TJ [°C] * RTHWN# = 10 kW to 5 VCC * REN = 10 kW to 5 VCC Figure 38. VTHWN#, VEN vs. Driver Temperature PWM LDRV (internal) HS FET short during LS FET turning on SW Potential noise from adjacent phases switching SW−Fault (internal) FAULT false trigger (internal) EN/FAULT# Normal switching operation Figure 39. Catastrophic Fault Waveform www.onsemi.com 19 EN/FAULT# pulled LOW and driver IC disabled FDMF5833 APPLICATION INFORMATION Decoupling Capacitor for PVCC & VCC PWM (Input) For the supply inputs (PVCC and VCC pins), local decoupling capacitors are required to supply the peak driving current and to reduce noise during switching operation. Use at least 0.68 ~ 1 mF / 0402 ~ 0603 / X5R ~ X7R multi−layer ceramic capacitors for both power rails. Keep these capacitors close to the PVCC and VCC pins and PGND and AGND copper planes. If they need to be located on the bottom side of board, put through−hole vias on each pads of the decoupling capacitors to connect the capacitor pads on bottom with PVCC and VCC pins on top. The supply voltage range on PVCC and VCC is 4.5 V ~ 5.5 V, and typically 5 V for normal applications. The PWM pin recognizes three different logic levels from PWM controller: HIGH, LOW, and 3−state. When the PWM pin receives a HIGH command, the gate driver turns on the high−side MOSFET. When the PWM pin receives a LOW command, the gate driver turns on the low−side MOSFET. When the PWM pin receives a voltage signal inside of the 3−state window (VTRI_Window) and exceeds the 3−state hold−off time, the gate driver turns off both high−side and low−side MOSFETs. To recognize the high−impedance 3−state signal from the controller, the PWM pin has an internal resistor divider from VCC to PWM to AGND. The resistor divider sets a voltage level on the PWM pin inside the 3−state window when the PWM signal from the controller is high−impedance. R−C Filter on VCC The PVCC pin provides power to the gate drive of the high−side and low−side power MOSFETs. In most cases, PVCC can be connected directly to VCC, which is the pin that provides power to the analog and logic blocks of the driver. To avoid switching noise injection from PVCC into VCC, a filter resistor can be inserted between PVCC and VCC decoupling capacitors. Recommended filter resistor value range is 0 ~ 10 W, typically 0 W for most applications. ZCD# (Input) When the ZCD# pin sets HIGH, the ZCD function is disabled and high−side and low−side MOSFETs switch in CCM (or FCCM, Forced CCM) by PWM signal. When the ZCD# pin is LOW, the low−side MOSFET turns off when the SPS driver detects negative inductor current during the low−side MOSFET turn−on period. This ZCD feature allows higher converter efficiency under light− load condition and PFM / DCM operation. The ZCD# pin has an internal current source from VCC, so it may not need an external pull−up resistor. Once VCC is supplied and the driver is enabled, the ZCD# pin holds logic HIGH without external components and the driver operates switching in CCM or FCCM. The ZCD# pin can be grounded for automatic diode emulation in DCM by the SPS itself, or it can be connected to the controller or system to follow the command from them. The typical pull−up resistor value on ZCD# ~ VCC is 10 kW for stable ZCD# HIGH level. If not using the ZCD feature, tie the ZCD# pin to VCC with a pull−up resistor. Do not add any noise filter capacitor on the ZCD# pin. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBOOT). A bootstrap capacitor of 0.1 ~ 0.22 mF / 0402 ~ 0603 / X5R ~ X7R is usually appropriate for most switching applications. A series bootstrap resistor may be needed for specific applications to lower high−side MOSFET switching speed. The boot resistor is required when the SPS is switching above 15 V VIN; when it is effective at controlling VSW overshoot. RBOOT value from zero to 6 W is typically recommended to reduce excessive voltage spike and ringing on the SW node. A higher RBOOT value can cause lower efficiency due to high switching loss of high−side MOSFET. Do not add a capacitor or resistor between the BOOT pin and GND. THWN# (Output) / THDN The THWN# pin is an open−drain, so needs an external pull−up resistor to VCC. If the driver temperature reaches 125°C, the VTHWN# is pulled LOW. When the driver TJ cools to less than 110°C, the VTHWN# returns HIGH. This THWN# flag operates when the driver TJ is below 150°C. If the driver TJ continuously increases over 150°C after asserting the 125°C THWN flag, the thermal shutdown feature activates and the SPS module is turned off. This shutdown is a latch function, so the driver remains shut down even if its temperature cools down to 25°C. The SPS module needs to be re−enabled by VCC POR once the THDN is activated. EN / FAULT# (Input / Output) The driver in SPS is enabled by pulling the EN pin HIGH. The EN pin has internal 250 kW pull−down resistor, so it needs to be pulled−up to VCC with an external resistor or connected to the controller or system to follow up the command from them. If the EN pin is floated, it cannot turn on the driver. The fault flag LOW signal is asserted on the EN / FAULT# pin when the driver temperature reaches THDN temperature or a high−side MOSFET fault occurs. Then the driver shuts down. The typical pull−up resistor value on EN ~ VCC is 10 kW. Do not add a noise filter capacitor on the EN pin. www.onsemi.com 20 FDMF5833 Power loss calculation and equation examples: PIN = (VIN ∗ IIN) + (VCC ∗ ICC) PSW = VSW ∗ IOUT POUT = VOUT ∗ IOUT PLOSS_MODULE = PIN – PSW PLOSS_TOTAL = PIN – POUT EFFIMODULE = (PSW / PIN) ∗ 100 EFFITOTAL = (POUT / PIN) ∗ 100 A typical pull−up resistor on THWN# ~ VCC is 10 kW. If not using THWN#/THDN features, tie THWN# to GND. Do not add a noise filter capacitor on the THWN# pin. Power Loss and Efficiency Figure 40 shows an example diagram for power loss and efficiency measurement. [W] [W] [W] [W] [W] [%] [%] Pulse Generator PW M Power Supply 1 Power Supply 2 VIN / IIN VIN HS VCC / ICC GD PVCC VSW / IOUT LS VCC Electronic Load VOUT V OUT / I OUT ON Semiconductor SPS Evaluation Board Figure 40. Power Loss and Efficiency Measurement Diagram PCB LAYOUT GUIDELINE An output inductor should be located close to the FDMF5833 to minimize the power loss due to the SW copper trace. Care should also be taken so the inductor dissipation does not heat the SPS. POWERTRENCH MOSFETs are used in the output stage and are effective at minimizing ringing due to fast switching. In most cases, no RC snubber on SW node is required. If a snubber is used, it should be placed close to the SW and PGND pins. The resistor and capacitor of the snubber must be sized properly to not generate excessive heating due to high power dissipation. Decoupling capacitors on PVCC, VCC, and BOOT capacitors should be placed as close as possible to the PVCC ~ PGND, VCC ~ AGND, and BOOT ~ PHASE pin pairs to ensure clean and stable power supply. Their routing traces should be wide and short to minimize parasitic PCB resistance and inductance. The board layout should include a placeholder for small− value series boot resistor on BOOT ~ PHASE. The boot−loop size, including series RBOOT and CBOOT, should be as small as possible. A boot resistor may be required when the SPS is operating above 15 V VIN and it is effective to control the high−side MOSFET turn−on slew rate and SW voltage overshoot. RBOOT can improve noise operating margin in synchronous buck designs that may have noise issues due to ground Figure 41 through Figure 44 provide examples of single− phase and multi−phase layouts for the FDMF5833 and critical components. All of the high−current paths; such as VIN, SW, VOUT, and GND coppers; should be short and wide for low parasitic inductance and resistance. This helps achieve a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance. Input ceramic bypass capacitors must be close to the VIN and PGND pins. This reduces the high−current power loop inductance and the input current ripple induced by the power MOSFET switching operation. The SW copper trace serves two purposes. In addition to being the high−frequency current path from the SPS package to the output inductor, it serves as a heat sink for the low−side MOSFET. The trace should be short and wide enough to present a low−impedance path for the high−frequency, high−current flow between the SPS and the inductor. The short and wide trace minimizes electrical losses and SPS temperature rise. The SW node is a high−voltage and high−frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. Since this copper trace acts as a heat sink for the low−side MOSFET, balance using the largest area possible to improve SPS cooling while maintaining acceptable noise emission. www.onsemi.com 21 FDMF5833 lead to excess current flow through the BOOT diode, causing high power dissipation. The ZCD# and EN pins have weak internal pull−up and pull−down current sources, respectively. These pins should not have any noise filter capacitors. Do not float these pins unless absolutely necessary. Put multiple vias on the VIN and VOUT copper areas to interconnect top, inner, and bottom layers to evenly distribute current flow and heat conduction. Do not put too many vias on the SW copper to avoid extra parasitic inductance and noise on the switching waveform. As long as efficiency and thermal performance are acceptable, place only one SW node copper on the top layer and put no vias on the SW copper to minimize switch node parasitic noise. Vias should be relatively large and of reasonably low inductance. Critical high−frequency components; such as RBOOT, CBOOT, RC snubber, and bypass capacitors; should be located as close to the respective SPS module pins as possible on the top layer of the PCB. If this is not feasible, they can be placed on the board bottom side and their pins connected from bottom to top through a network of low− inductance vias. bounce or high positive and negative VSW ringing. Inserting a boot resistance lowers the SPS module efficiency. Efficiency versus switching noise must be considered. RBOOT values from 0.5 W to 0.6 W are typically effective in reducing VSW overshoot. The VIN and PGND pins handle large current transients with frequency components greater than 100 MHz. If possible, these pins should be connected directly to the VIN and board GND planes. The use of thermal relief traces in series with these pins is not recommended since this adds extra parasitic inductance to the power path. This added inductance in series with either the VIN or PGND pin degrades system noise immunity by increasing positive and negative VSW ringing. PGND pad and pins should be connected to the GND copper plane with multiple vias for stable grounding. Poor grounding can create a noisy and transient offset voltage level between PGND and AGND. This could lead to faulty operation of gate driver and MOSFETs. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add any additional capacitors between BOOT to PGND. This may PCB LAYOUT GUIDELINE Figure 41. Single−Phase Board Layout Example – Top View www.onsemi.com 22 FDMF5833 PCB LAYOUT GUIDELINE (continued) Figure 42. Single−Phase Board Layout Example – Bottom View (Mirrored) Figure 43. 6−Phase Board Layout Example with 6 mm x 6 mm Inductor – Top View www.onsemi.com 23 FDMF5833 PCB LAYOUT GUIDELINE (continued) Figure 44. 6−Phase Board Layout Example with 6 mm x 6 mm Inductor – Bottom View (Mirrored) PACKAGE MARKING AND ORDERING INFORMATION Part Number Top Marking Current Rating Package Shipping (Qty / Packing)† FDMF5833 5833 50 A 31−Lead, Clip Bond PQFN31 5x5, 0.5P (Pb−Free/Halogen Free) 3000 / Tape & Reel FDMF5833−F085 5833 F085 50 A 31−Lead, Clip Bond PQFN31 5x5, 0.5P (Pb−Free/Halogen Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. POWERTRENCH is registered trademark and SyncFET is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 24 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PQFN31 5X5, 0.5P CASE 483BR ISSUE C DATE 28 SEP 2022 SCALE 2.5:1 GENERIC MARKING DIAGRAM* XXXXXXXX XXXXXXXX AWLYYWWG G DOCUMENT NUMBER: DESCRIPTION: XXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) 98AON13680G PQFN31 5X5, 0.5P *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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