FDMF6821A

Extra-Small, High-Performance, High-Frequency DrMOS Module FDMF6821A Description The XS™ DrMOS family is ON Semiconductor’s next−generation, fully optimized, ultra−compact, integrated MOSFET plus driver power stage solution for high−current, high− frequency, synchronous buck DC−DC applications. The FDMF6821A integrates a driver IC, two power MOSFETs, and a bootstrap Schottky diode into a thermally enhanced, ultra−compact 6x6 mm package. With an integrated approach, the complete switching power stage is optimized with regard to driver and MOSFET dynamic performance, system inductance, and power MOSFET RDS(ON). XS DrMOS uses ON Semiconductor’s high−performance POWERTRENCH ® MOSFET technology, which dramatically reduces switch ringing, eliminating the need for snubber circuit in most buck converter applications. A driver IC with reduced dead times and propagation delays further enhances the performance. A thermal warning function warns of a potential over−temperature situation. The FDMF6821A also incorporates a Skip Mode (SMOD#) for improved light−load efficiency. The FDMF6821A also provides a 3−state 3.3 V PWM input for compatibility with a wide range of PWM controllers. Features • • • • • • • • • • • • • • • • • Over 93% Peak−Efficiency High−Current Handling: 60 A High−Performance PQFN Copper−Clip Package 3−State 3.3 V PWM Input Driver Skip−Mode SMOD# (Low−Side Gate Turn Off) Input Thermal Warning Flag for Over−Temperature Condition Driver Output Disable Function (DISB# Pin) Internal Pull−Up and Pull−Down for SMOD# and DISB# Inputs, Respectively ON Semiconductor PowerTrench Technology MOSFETs for Clean Voltage Waveforms and Reduced Ringing ON Semiconductor SyncFET (Integrated Schottky Diode) Technology in Low−Side MOSFET Integrated Bootstrap Schottky Diode Adaptive Gate Drive Timing for Shoot−Through Protection Under−Voltage Lockout (UVLO) Optimized for Switching Frequencies up to 1 MHz Low−Profile SMD Package Based on the Intel® 4.0 DrMOS Standard This Device is Pb−Free, Halogen Free/BFR Free and is RoHS Compliant © Semiconductor Components Industries, LLC, 2012 January, 2020 − Rev. 2 1 www.onsemi.com PQFN40 6X6, 0.5P CASE 483AN MARKING DIAGRAM $Y&Z&3&K FDMF 6821A $Y &Z &3 &K FDMF6821A = ON Semiconductor Logo = Assembly Plant Code = Numeric Date Code = Lot Code = Specific Device Code ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. Publication Order Number: FDMF6821A/D FDMF6821A • Compact Blade Servers, V−Core and Non−V−Core Benefits • Ultra−Compact 6x6 mm PQFN, 72% Space−Saving • • • Compared to Conventional Discrete Solutions Fully Optimized System Efficiency Clean Switching Waveforms with Minimal Ringing High−Current Handling • • • • Applications • High−Performance Gaming Motherboards • DC−DC Converters Desktop Computers, V−Core and Non−V−Core DC−DC Converters Workstations High−Current DC−DC Point−of−Load Converters Networking and Telecom Microprocessor Voltage Regulators Small Form−Factor Voltage Regulator Modules ORDERING INFORMATION Part Number Current Rating Package Top Mark FDMF6821A 60 A 40−Lead, Clipbond PQFN DrMOS, 6.0 mm x 6.0 mm Package FDMF6821A Typical Application Circuit VIN 3V ~ 16V V5V CVIN CVDRV VDRV DISB# VCIN VIN RBOOT DISB# BOOT PWM Input PWM OFF ON Open-Drain Output CBOOT FDMF6821A PHASE SMOD# VOUT VSWH LOUT THWN# CGND COUT PGND Figure 1. Typical Application Circuit www.onsemi.com 2 FDMF6821A DrMOS Block Diagram VDRV VIN BOOT UVLO VCIN Q1 HS Power MOSFET DBoot DISB# GH Level−Shift 10 mA 30 kW PHASE VCIN RUP_PWM Dead−Time Input 3−State Logic PWM Control VSWH VDRV RDN_PWM GL GL Logic THWN# VCIN 30 kW Temp. Sense Q2 LS Power MOSFET 10 mA CGND SMOD# PGND Figure 2. DrMOS Block Diagram Pin Configuration Figure 3. Bottom View Figure 4. Top View www.onsemi.com 3 FDMF6821A PIN DEFINITIONS Pin # 1 Name Description SMOD# When SMOD# = HIGH, the low−side driver is the inverse of the PWM input. When SMOD# = LOW, the low−side driver is disabled. This pin has a 10 mA internal pull−up current source. Do not add a noise filter capacitor. 2 3 VCIN VDRV IC bias supply. Minimum 1 mF ceramic capacitor is recommended from this pin to CGND. 4 BOOT Bootstrap supply input. Provides voltage supply to the high−side MOSFET driver. Connect a bootstrap capacitor from this pin to PHASE. 5, 37, 41 CGND IC ground. Ground return for driver IC. Power for the gate driver. Minimum 1 mF ceramic capacitor is recommended to be connected as close as possible from this pin to CGND. 6 GH 7 8 PHASE NC Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin. 9 − 14, 42 VIN VSWH Power input. Output stage supply voltage. PGND Power ground. Output stage ground. Source pin of the low−side MOSFET. 15, 29 − 35, 43 16 – 28 36 38 39 40 For manufacturing test only. This pin must float; it must not be connected to any pin. No connect. The pin is not electrically connected internally, but can be connected to VIN for convenience. Switch node input. Provides return for high−side bootstrapped driver and acts as a sense point for the adaptive shoot−through protection. GL For manufacturing test only. This pin must float; it must not be connected to any pin. THWN# Thermal warning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW. THWN# does not disable the module. DISB# Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are held LOW). This pin has a 10 mA internal pull−down current source. Do not add a noise filter capacitor. PWM PWM signal input. This pin accepts a three−state 3.3 V PWM signal from the controller. www.onsemi.com 4 FDMF6821A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min. Max. Unit VCIN Supply Voltage Referenced to CGND −0.3 6.0 V VDRV Drive Voltage Referenced to CGND −0.3 6.0 V VDISB# Output Disable Referenced to CGND −0.3 6.0 V VPWM PWM Signal Input Referenced to CGND −0.3 6.0 V Skip Mode Input Referenced to CGND −0.3 6.0 V Low Gate Manufacturing Test Pin Referenced to CGND −0.3 6.0 V Thermal Warning Flag Referenced to CGND −0.3 6.0 V Power Input Referenced to PGND, CGND −0.3 25.0 V Bootstrap Supply Referenced to VSWH, PHASE −0.3 6.0 V Referenced to CGND −0.3 25.0 V Referenced to VSWH, PHASE −0.3 6.0 V Referenced to CGND −0.3 25.0 V VSMOD# VGL VTHWN# VIN VBOOT VGH High Gate Manufacturing Test Pin VPHS PHASE Referenced to CGND −0.3 25.0 V VSWH Switch Node Input Referenced to PGND, CGND (DC Only) −0.3 25.0 V Referenced to PGND, VIH_DISB). Exiting Three−State Condition UVLO DISB# Driver State 0 X Disabled (GH, GL = 0) 1 0 Disabled (GH, GL = 0) When exiting a valid three−state condition, the FDMF6821A follows the PWM input command. If the PWM input goes from three−state to LOW, the low−side MOSFET is turned on. If the PWM input goes from three−state to HIGH, the high−side MOSFET is turned on. This is illustrated in Figure 27. The FDMF6821A design allows for short propagation delays when exiting the three−state window (see Electrical Characteristics). 1 1 Enabled (see Table 2) Low−Side Driver 1 Open Disabled (GH, GL = 0) The low−side driver (GL) is designed to drive a ground− referenced, low−RDS(ON), N−channel MOSFET. The bias for GL is internally connected between the VDRV and CGND pins. When the driver is enabled, the driver’s output is 180° out of phase with the PWM input. When the driver is disabled (DISB# = 0 V), GL is held LOW. Table 1. UVLO AND DISABLE LOGIC 3. DISB# internal pull−down current source is 10 mA. Thermal Warning Flag (THWN#) The FDMF6821A provides a thermal warning flag (THWN#) to warn of over−temperature conditions. The thermal warning flag uses an open−drain output that pulls to CGND when the activation temperature (150°C) is reached. The THWN# output returns to a high− impedance state once the temperature falls to the reset temperature (135°C). For use, the THWN# output requires a pull−up resistor, which can be connected to VCIN. THWN# does NOT disable the DrMOS module. HIGH THWN# Logic State 135°C Reset Temperature High−Side Driver The high−side driver (GH) is designed to drive a floating N−channel MOSFET. The bias voltage for the high−side driver is developed by a bootstrap supply circuit consisting of the internal Schottky diode and external bootstrap capacitor (CBOOT). During startup, VSWH is held at PGND, allowing CBOOT to charge to VDRV through the internal diode. When the PWM input goes HIGH, GH begins to charge the gate of the high−side MOSFET (Q1). During this transition, the charge is removed from CBOOT and delivered to the gate of Q1. As Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to VIN + VBOOT, which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling GH to VSWH. CBOOT is then recharged to VDRV when VSWH falls to PGND. GH output is in−phase with the PWM input. The high−side gate is held LOW when the driver is disabled or the PWM signal is held within the three−state window for longer than the three−state hold−off time, tD_HOLD−OFF. 150°C A p Normal Operation Thermal Warning LOW TJ_driver IC Figure 26. THWN Operation www.onsemi.com 13 FDMF6821A Adaptive Gate Drive Circuit propagation delay (tPD_PHGLL). Once the GL pin is discharged below 1.0 V, Q1 begins to turn on after adaptive delay tD_DEADON. To preclude overlap during the HIGH−to−LOW transition (Q1 off to Q2 on), the adaptive circuitry monitors the voltage at the GH−to−PHASE pin pair. When the PWM signal goes LOW, Q1 begins to turn off after a propagation delay (tPD_PLGHL). Once the voltage across GH−to−PHASE falls below 2.2 V, Q2 begins to turn on after adaptive delay tD_DEADOFF. The driver IC advanced design ensures minimum MOSFET dead−time, while eliminating potential shoot− through (cross−conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive adaptively to ensure they do not conduct simultaneously. Figure 27 provides the relevant timing waveforms. To prevent overlap during the LOW−to−HIGH switching transition (Q2 off to Q1 on), the adaptive circuitry monitors the voltage at the GL pin. When the PWM signal goes HIGH, Q2 begins to turn off after a V IH_PWM tD_HOLD-OFF V IH_PWM V TRI_HI V IH_PWM V IH_PWM V TRI_HI V TRI_LO V IL_PWM V IL_PWM tR_GH PWM tF_GH 90% GH to VSWH 10% V IN DCM DCM CCM V OUT 2.2V VSWH tR_GL GL tF_GL 90% 90% 1.0V tPD_PHGLL tD_DEADON 10% 10% tPD_PLGHL tPD_TSGHH tD_HOLD-OFF t PD_TSGHH tD_HOLD-OFF tPD_TSGLH tD_DEADOFF NOTES: tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal. tD_xxx = delay from IC generated signal to IC generated signal. PWM tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (SMOD# held LOW) SMOD# tPD_SLGLL = SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS Example (tPD_PHGLL – PWM going HIGH to LS VGS (GL) going LOW) Example (tD_DEADON – LS VGS (GL) LOW to HS VGS (GH) HIGH) Exiting 3−state tPD_TSGHH = PWM 3−state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS tPD_TSGLH = PWM 3−state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS Dead Times tD_DEADON = LS VGS fall to HS VGS rise, LS−comp trip value (~1.0 V GL) to 10% HS VGS tD_DEADOFF = VSWH fall to LS VGS rise, SW−comp trip value (~2.2 V VSWH) to 10% LS VGS Figure 27. PWM and 3−StateTiming Diagram www.onsemi.com 14 FDMF6821A Skip Mode (SMOD#) allows for gating on the Low Side MOSFET. When the SMOD# pin is pulled LOW, the low−side MOSFET is gated off. If the SMOD# pin is connected to the PWM controller, the controller can actively enable or disable SMOD# when the controller detects light−load condition from output current sensing. Normally this pin is active LOW. See Figure 28 for timing delays. The Skip Mode function allows for higher converter efficiency when operated in light−load conditions. When SMOD# is pulled LOW, the low−side MOSFET gate signal is disabled (held LOW), preventing discharge of the output capacitors as the filter inductor current attempts reverse current flow – known as “Diode Emulation” Mode. When the SMOD# pin is pulled HIGH, the synchronous buck converter works in Synchronous Mode. This mode Table 2. SMOD# LOGIC DISB# PWM SMOD# GH GL 0 X X 0 0 1 3−State X 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 4. The SMOD# feature is intended to have a short propagation delay between the SMOD# signal and the low−side FET VGS response time to control diode emulation on a cycle−by−cycle basis. SMOD# V IH_SMOD V IL_SMOD V IH_PWM V IH_PWM V IL_PWM PWM 90% GH to VSWH 10% 10% DCM CCM CCM 2.2V V OUT VSWH GL 90% 1.0V tPD_PHGLL tD_DEADON 10% tPD_PLGHL tD_DEADOFF 10% tPD_PHGHH tPD_SLGLL Delay from SMOD# going LOW to LS VGS LOW HS turn -on with SMOD# LOW Figure 28. SMOD# Timing Diagram www.onsemi.com 15 tPD_SHGLH Delay from SMOD# going HIGH to LS VGS HIGH FDMF6821A APPLICATION INFORMATION Supply Capacitor Selection can be connected directly to VCIN, the pin that provides power to the logic section of the driver. For additional noise immunity, an RC filter can be inserted between the VDRV and VCIN pins. Recommended values would be 10 W and 1 mF. For the supply inputs (VCIN), a local ceramic bypass capacitor is recommended to reduce noise and to supply the peak current. Use at least a 1 mF X7R or X5R capacitor. Keep this capacitor close to the VCIN pin and connect it to the GND plane with vias. Power Loss and Efficiency Bootstrap Circuit Measurement and Calculation Refer to Figure 30 for power loss testing method. Power loss calculations are: PIN = (VIN × IIN) + (V5V × I5V) (W) (1) (2) PSW = VSW × IOUT (W) POUT = VOUT × IOUT (W) (3) (4) PLOSS_MODULE = PIN - PSW (W) (5) PLOSS_BOARD = PIN - POUT (W) EFFMODULE = 100 × PSW/PIN (%) (6) EFFBOARD = 100 × POUT/PIN (%) (7) The bootstrap circuit uses a charge storage capacitor (CBOOT), as shown in Figure 30. A bootstrap capacitance of 100 nF X7R or X5R capacitor is usually adequate. A series bootstrap resistor may be needed for specific applications to improve switching noise immunity. The boot resistor may be required when operating above 15 VIN and is effective at controlling the high−side MOSFET turn−on slew rate and VSHW overshoot. RBOOT values from 0.5 to 3.0 W are typically effective in reducing VSWH overshoot. VCIN Filter The VDRV pin provides power to the gate drive of the high−side and low−side power MOSFET. In most cases, it V5V A I5V RVCIN CVDRV VDRV DISB# VIN VCIN VIN DISB# PWM Input C VIN C VCIN A IIN RBOOT BOOT PWM FDMF6821A FDM 67 5 OFF CBOOT IOUT VSWH SMOD# ON Open A LOUT PHASE VOUT THWN# Output V VSW PGND CGND COUT Figure 29. Block Diagram With VCIN Filter V5V A I5V CVIN CVDRV VDRV DISB# PWM Input A IIN VIN VIN VCIN DISB# RBOOT BOOT PWM OFF FDMF6821A FDM 5 CBOOT IOUT VSWH ON SMOD# Open A LOUT PHASE THWN# Output CGND V VSW PGND COUT Figure 30. Power Loss Measurement www.onsemi.com 16 FDMF6821A PCB LAYOUT GUIDELINES when operating above 15 VIN and is effective at controlling the high−side MOSFET turn−on slew rate and VSHW overshoot. RBOOT can improve noise operating margin in synchronous buck designs that may have noise issues due to ground bounce or high positive and negative VSWH ringing. Inserting a boot resistance lowers the DrMOS efficiency. Efficiency versus noise trade−offs must be considered. RBOOT values from 0.5 W to 3.0 W are typically effective inreducing VSWH overshoot 8. The VIN and PGND pins handle large current transients with frequency components greater than 100 MHz. If possible, these pins should be connected directly to the VIN and board GND planes. The use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. This added inductance in series with either the VIN or PGND pin degrades system noise immunity by increasing positive and negative VSWH ringing 9. GND pad and PGND pins should be connected to the GND copper plane with multiple vias for stable grounding. Poor grounding can create a noise transient offset voltage level between CGND and PGND. This could lead to faulty operation of the gate driver and MOSFETs 10. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add an additional BOOT to the PGND capacitor. This may lead to excess current flow through the BOOT diode 11. The SMOD# and DISB# pins have weak internal pull−up and pull−down current sources, respectively. These pins should not have any noise filter capacitors. Do not to float these pins unless absolutely necessary 12. Use multiple vias on the VIN and VOUT copper areas to interconnect top, inner, and bottom layers to distribute current flow and heat conduction. Do not put many vias on the VSWH copper to avoid extra parasitic inductance and noise on the switching waveform. As long as efficiency and thermal performance are acceptable, place only one VSWH copper on the top layer and use no vias on the VSWH copper to minimize switch node parasitic noise. Vias should be relatively large and of reasonably low inductance. Critical high− frequency components, such as RBOOT, CBOOT, RC snubber, and bypass capacitors; should be located as close to the respective DrMOS module pins as possible on the top layer of the PCB. If this is not feasible, they can be connected from the backside through a network of low−inductance vias Figure 31 and Figure 32 provide an example of a proper layout for the FDMF6821A and critical components. All of the high−current paths, such as VIN, VSWH, VOUT, and GND copper, should be short and wide for low inductance and resistance. This aids in achieving a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance. Recommendations for PCB Designers 1. Input ceramic bypass capacitors must be placed close to the VIN and PGND pins. This helps reduce the high−current power loop inductance and the input current ripple induced by the power MOSFET switching operation 2. The VSWH copper trace serves two purposes. In addition to being the high−frequency current path from the DrMOS package to the output inductor, it serves as a heat sink for the low−side MOSFET in the DrMOS package. The trace should be short and wide enough to present a low−impedance path for the high−frequency, high−current flow between the DrMOS and inductor. The short and wide trace minimizes electrical losses as well as the DrMOS temperature rise. Note that the VSWH node is a high− voltage and high−frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. Since this copper trace acts as a heat sink for the lower MOSFET, balance using the largest area possible to improve DrMOS cooling while maintaining acceptable noise emission 3. An output inductor should be located close to the FDMF6821A to minimize the power loss due to the VSWH copper trace. Care should also be taken so the inductor dissipation does not heat the DrMOS 4. POWERTRENCH MOSFETs are used in the output stage and are effective at minimizing ringing due to fast switching. In most cases, no VSWH snubber is required. If a snubber is used, it should be placed close to the VSWH and PGND pins. The selected resistor and capacitor need to be the proper size for power dissipation 5. VCIN, VDRV, and BOOT capacitors should be placed as close as possible to the VCIN−to−CGND, VDRV−to−CGND, and BOOT−to−PHASE pin pairs to ensure clean and stable power. Routing width and length should be considered as well 6. Include a trace from the PHASE pin to the VSWH pin to improve noise margin. Keep this trace as short as possible 7. The layout should include the option to insert a small−value series boot resistor between the boot capacitor and BOOT pin. The boot−loop size, including RBOOT and CBOOT, should be as small as possible. The boot resistor may be required www.onsemi.com 17 FDMF6821A Figure 31. PCB Layout Example (Top View) Figure 32. PCB Layout Example (Bottom View) XS DrMOS are trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. Intel is a registered trademark of Intel Corporation in the U.S. and/or other countries. www.onsemi.com 18 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PQFN40 6X6, 0.5P CASE 483AN ISSUE A DOCUMENT NUMBER: DESCRIPTION: 98AON13663G PQFN40 6X6, 0.5P DATE 08 JUN 2021 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative