FDMS3660S

FDMS3660S PowerTrench) Power Stage Asymmetric Dual N−Channel MOSFET Description This device includes two specialized N−Channel MOSFETs in a dual PQFN package. The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous SyncFET (Q2) have been designed to provide optimal power efficiency. www.onsemi.com Features Q1: N−Channel • Max rDS(on) = 8 mW at VGS = 10 V, ID = 13 A • Max rDS(on) = 11 mW at VGS = 4.5 V, ID = 11 A Q2: N−Channel • Max rDS(on) = 1.8 mW at VGS = 10 V, ID = 30 A • Max rDS(on) = 2.2 mW at VGS = 4.5 V, ID = 27 A • Low Inductance Packaging Shortens Rise/Fall Times, Resulting in Lower Switching Losses • MOSFET Integration Enables Optimum Layout for Lower Circuit Inductance and Reduced Switch Node Ringing • These Devices are Pb−Free and are RoHS Compliant D1 D1 D1 D1 PHASE (S1/D2) G2 S2 S2 S2 Applications • • • • G1 Pin 1 PQFN8 POWER 56 CASE 483AJ Computing Communications General Purpose Point of Load Notebook VCORE S2 5 S2 6 S2 7 G2 8 Q2 4 D1 PHASE 3 D1 2 D1 Q1 1 G1 ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2012 November, 2017 − Rev. 3 1 Publication Order Number: FDMS3660S/D FDMS3660S MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Symbol VDS Bvdsst VGS ID Q1 Q2 Unit Drain to Source Voltage Rating 30 30 V Bvdsst (Transient) < 100 ns 36 36 V Gate to Source Voltage (Note 3) ±20 ±12 V Drain Current − Continuous (Package limited) (TC = 25°C) 30 60 A Drain Current − Continuous (Silicon limited) (TC = 25°C) 60 145 13 (Note 6a) 30 (Note 6b) 40 120 33 (Note 4) 86 (Note 5) mJ W Drain Current − Continuous (TA = 25°C) Drain Current − Pulsed EAS Single Pulse Avalanche Energy PD Power Dissipation for Single Operation (TA = 25°C) 2.2 (Note 6a) 2.5 (Note 6b) Power Dissipation for Single Operation (TA = 25°C) 1 (Note 6c) 1 (Note 6d) TJ, TSTG Operating and Storage Junction Temperature Range °C −55 to +150 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL CHARACTERISTICS Symbol Parameter Q1 Q2 Unit RqJA Thermal Resistance, Junction−to−Ambient 57 (Note 6a) 50 (Note 6b) °C/W RqJA Thermal Resistance, Junction−to−Ambient 125 (Note 6c) 120 (Note 6d) °C/W RqJC Thermal Resistance, Junction−to−Case 2.9 2.2 °C/W PACKAGE MARKING AND ORDERING INFORMATION Device Device Marking Package Reel Size Tape Width Quantity FDMS3660S 22CF 07OD Power 56 13″ 12 mm 3000 Units Table 1. ELECTRICAL CHARACTERISTICS TJ = 25°C unless otherwise noted Symbol Parameter Test Conditions Type Min 30 30 Typ Max Units OFF CHARACTERISTICS Drain to Source Breakdown Voltage ID = 250 mA, VGS = 0 V ID = 1 mA, VGS = 0 V Q1 Q2 DBVDSS/ DTJ Breakdown Voltage Temperature Coefficient ID = 250 mA, referenced to 25°C ID = 10 mA, referenced to 25°C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V Q1 Q2 1 500 mA mA IGSS Gate to Source Leakage Current VGS = 20 V, VDS = 0 V VGS = 12 V, VDS = 0 V Q1 Q2 100 100 nA nA 2.7 2.2 V BVDSS V 16 24 mV/°C ON CHARACTERISTICS VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 mA VGS = VDS, ID = 1 mA Q1 Q2 DVGS(th)/ DTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 mA, referenced to 25°C ID = 10 mA, referenced to 25°C Q1 Q2 −6 −3 Drain to Source On Resistance VGS = 10 V, ID = 13 A VGS = 4.5 V, ID = 11 A VGS = 10 V, ID = 13 A, TJ =125°C Q1 4 6 5.7 8 11 8.7 VGS = 10 V, ID = 30 A VGS = 4.5 V, ID = 27 A VGS = 10 V, ID = 30 A, TJ = 125°C Q2 1.3 1.5 1.86 1.8 2.2 2.6 rDS(on) www.onsemi.com 2 1.1 1.1 1.9 1.5 mV/°C mW FDMS3660S Table 1. ELECTRICAL CHARACTERISTICS TJ = 25°C unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units ON CHARACTERISTICS gFS Forward Transconductance VDS = 5 V, ID = 13 A VDS = 5 V, ID = 30 A Q1 Q2 62 231 S Q1: VDS = 15 V, VGS = 0 V, f = 1 MHZ Q1 Q2 1325 4130 1765 5493 pF Q1 Q2 466 915 620 1220 pF 46 124 70 185 pF 0.6 0.8 2 3 W Q1 Q2 7.7 11 15 20 ns Q1 Q2 2.2 5 10 10 ns Turn−Off Delay Time Q1 Q2 19 40 34 64 ns Fall Time Q1 Q2 1.8 3.9 10 10 ns Q1 Q2 21 62 29 87 nC Q1 Q2 9.5 29 13 41 nC DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Q1 Q2 Gate Resistance Q1 Q2 Rg Q2: VDS = 15 V, VGS = 0 V, f = 1 MHZ 0.2 0.2 SWITCHING CHARACTERISTICS td(on) tr td(off) tf Turn−On Delay Time Rise Time Q1: VDD = 15 V, ID = 13 A, RGEN = 6 W Q2: VDD = 15 V, ID = 30 A, RGEN = 6 W Q1 VDD = 15 V, ID = 13 A Q2 VDD = 15 V, ID = 30 A Qg Total Gate Charge VGS = 0 V to 10 V Qg Total Gate Charge VGS = 0 V to 4.5 V Qgs Gate to Source Gate Charge Q1 Q2 3.9 9 nC Qgd Gate to Drain “Miller” Charge Q1 VDD = 15 V, ID = 13 A Q2 VDD = 15 V, ID = 30 A Q1 Q2 2.6 7 nC Source to Drain Diode Forward Voltage VGS = 0 V, IS = 13 A (Note 2) VGS = 0 V, IS = 2 A (Note 2) VGS = 0 V, IS = 30 A (Note 2) VGS = 0 V, IS = 2 A (Note 2) Q1 Q1 Q2 Q2 0.8 0.7 0.8 0.6 1.2 1.2 1.2 1.2 V trr Reverse Recovery Time Q1 Q2 26 29 42 46 ns Qrr Reverse Recovery Charge Q1 IF = 13 A, di/dt = 100 A/ms Q2 IF = 30 A, di/dt = 300 A/ms Q1 Q2 10 32 20 50 nC DRAIN−SOURCE DIODE CHARACTERISTICS VSD Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. RqJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. RqJC is guaranteed by design while RqCA is determined by the user’s board design. 2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%. 3. As an N−ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied with the negative Vgs rating. 4. EAS of 33 mJ is based on starting TJ = 25°C; N−ch: L = 1.9 mH, IAS = 6 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 16 A. 5. EAS of 86 mJ is based on starting TJ = 25°C; N−ch: L = 0.6 mH, IAS = 17 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 31 A. www.onsemi.com 3 FDMS3660S (Note 6a) (Note 6b) SS SF DS DF G SS SF DS DF G (Note 6c) (Note 6d) SS SF DS DF G SS SF DS DF G 6. a) 57°C/W when mounted on a 1 in2 pad of 2 oz copper b) 50°C/W when mounted on a 1 in2 pad of 2 oz copper c) 125°C/W when mounted on a minimum pad of 2 oz copper d) 120°C/W when mounted on a minimum pad of 2 oz copper www.onsemi.com 4 FDMS3660S TYPICAL CHARACTERISTICS (Q1 N−Channel) TJ = 25°C unless otherwise noted 40 4 30 VGS = 6 V VGS = 4.5 V 20 VGS = 4 V VGS = 3.5 V 10 PULSE DURATION = 80ms DUTY CYCLE = 0.5% MAX 0 0.0 0.2 0.4 0.6 0.8 PULSE DURATION = 80ms DUTY CYCLE = 0.5% MAX NORMALIZED DRAIN TO SOURCE ON−RESISTANCE ID, DRAIN CURRENT (A) VGS = 10 V 3 VGS = 3.5 V VGS = 4 V 2 1 0 1.0 0 10 Figure 1. On Region Characteristics 30 40 Figure 2. Normalized On−Resistance vs. Drain Current and Gate Voltage 20 ID = 13 A VGS = 10 V rDS(on) , DRAIN TO 1.4 1.2 1.0 0.8 SOURCE ON−RESISTANCE(mW) 1.6 NORMALIZED DRAIN TO SOURCE ON−RESISTANCE 20 VGS = 10 V ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 16 TJ = 125 oC 8 4 TJ = 25 oC 0 0.6 −75 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE o (C) 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 4. On−Resistance vs. Gate to Source Voltage 40 40 IS, REVERSE DRAIN CURRENT (A) PULSE DURATION = 80 m s DUTY CYCLE = 0.5% MAX 30 VDS = 5 V TJ = 150 oC 20 TJ = 25 oC 10 TJ = −55oC 0 ID = 13 A 12 Figure 3. Normalized On Resistance vs. Junction Temperature ID, DRAIN CURRENT (A) VGS = 6 V VGS = 4.5 V 1.5 2.0 2.5 3.0 3.5 VGS = 0 V 10 TJ = 150 oC 1 TJ = 25 oC 0.1 TJ = −55oC 0.01 0.001 0.0 4.0 VGS, GATE TO SOURCE VOLTAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs. Source Current www.onsemi.com 5 FDMS3660S TYPICAL CHARACTERISTICS (Q1 N−Channel) TJ = 25°C unless otherwise noted 2000 ID = 13 A VDD = 10 V Ciss 1000 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 15 V 6 VDD = 20 V 4 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 5 10 15 20 10 0.1 25 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs. Drain to Source Voltage 100 80 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) o RqJC = 2.9 C/W TJ = 25 oC 10 TJ = 100 oC 60 VGS = 10 V 40 VGS = 4.5 V 20 Limited by Package TJ = 125 oC 1 0.001 0.01 0.1 1 10 0 25 100 50 tAV, TIME IN AVALANCHE (ms) Figure 9. Unclamped Inductive Switching Capability P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 10 1 ms THIS AREA IS LIMITED BY rDS(on) 10 ms 100 ms SINGLE PULSE TJ = MAX RATED 1s 10 s DC RqJA = 125 oC/W TA = 25 oC 0.01 0.01 125 150 1000 100 m s 0.1 100 Figure 10. Maximum Continuous Drain Current vs. Case Temperature 100 1 75 TC, CASE TEMPERATURE ( o C) 0.1 1 10 SINGLE PULSE o RqJA = 125 C/W 100 10 1 0.1 −4 10 100 200 VDS, DRAIN to SOURCE VOLTAGE (V) −3 10 −2 10 −1 10 1 10 100 1000 t, PULSE WIDTH (sec) Figure 11. Forward Bias Safe Operating Area Figure 12. Single Pulse Maximum Power Dissipation www.onsemi.com 6 FDMS3660S TYPICAL CHARACTERISTICS (Q1 N−Channel) TJ = 25°C unless otherwise noted 2 DUTY CYCLE−DESCENDING ORDER NORMALIZED THERMAL IMPEDANCE, ZqJA 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t 2 PEAK TJ = PDM x ZqJA x RqJA + TA o RqJA = 125 C/W (Note 1c) 0.001 −4 10 −3 10 −2 10 −1 10 11 0 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction−to−Ambient Transient Thermal Response Curve www.onsemi.com 7 100 1000 FDMS3660S TYPICAL CHARACTERISTICS (Q2 N−Channel) TJ = 25°C unless otherwise noted 120 4 ID, DRAIN CURRENT (A) 100 VGS = 4.5 V VGS = 3.5 V 80 VGS = 3 V 60 40 PULSE DURATION = 80m s DUTY CYCLE = 0.5% MAX 20 VGS = 2.5 V 0 0.0 0.2 0.4 0.6 0.8 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX NORMALIZED DRAIN TO SOURCE ON−RESISTANCE VGS = 10 V 3 VGS = 2.5 V VGS = 3 V 2 1 0 1.0 0 20 Figure 14. On Region Characteristics rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 SOURCE ON−RESISTANCE(mW) NORMALIZED DRAIN TO SOURCE ON−RESISTANCE 100 120 8 ID = 30 A VGS = 10 V PULSE DURATION = 80m s DUTY CYCLE = 0.5% MAX 6 ID = 30 A 4 TJ = 125 oC 2 TJ = 25 oC 0 0.6 −75 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 16. Normalized On−Resistance vs. Junction Temperature Figure 17. On−Resistance vs. Gate to Source Voltage 120 100 PULSE DURATION = 80ms DUTY CYCLE = 0.5% MAX IS, REVERSE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 80 Figure 15. Normalized On−Resistance vs. Drain Current and Gate Voltage 1.6 VDS = 5 V 80 TJ = 125 oC 60 TJ = 25 oC 40 TJ = −55oC 20 0 1.0 60 ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) 100 40 VGS = 10 V VGS = 4.5 V VGS = 3.5 V 1.5 2.0 2.5 VGS = 0 V 10 1 0.1 TJ = 25 oC 0.01 0.001 3.0 TJ = 125 oC VGS, GATE TO SOURCE VOLTAGE (V) TJ = −55oC 0.0 0.2 0.4 0.6 0.8 1.0 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 18. Transfer Characteristics Figure 19. Source to Drain Diode Forward Voltage vs. Source Current www.onsemi.com 8 FDMS3660S TYPICAL CHARACTERISTICS (Q2 N−Channel) TJ = 25°C unless otherwise noted 10000 ID = 30 A 8 Ciss VDD = 10 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 6 VDD = 15 V 4 VDD = 20 V 1000 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 10 20 30 40 50 60 10 0.1 70 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 20. Gate Charge Characteristics Figure 21. Capacitance vs. Drain to Source Voltage 100 160 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) o TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 1 0.001 0.01 0.1 1 120 VGS = 4.5 V 80 40 Limited by Package 10 100 0 1000 25 50 tAV, TIME IN AVALANCHE (ms) P(PK), PEAK TRANSIENT POWER (W) 100 m s 10 1 ms 10 ms THIS AREA IS LIMITED BY rDS(on) 0.1 100 ms SINGLE PULSE TJ = MAX RATED 1s 10s RqJA = 120 oC/W DC o TA = 25 C 0.01 0.01 0.1 1 100 125 150 Figure 23. Maximum Continuous Drain Current vs. Case Temperature 200 100 1 75 TC, CASE TEMPERATURE ( oC) Figure 22. Unclamped Inductive Switching Capability ID, DRAIN CURRENT (A) RqJC = 2.2 C/W VGS = 10 V 10 100 200 2000 1000 SINGLE PULSE o RqJA = 120 C/W 100 10 1 0.5 −4 10 VDS, DRAIN to SOURCE VOLTAGE (V) −3 10 −2 10 −1 10 1 10 100 1000 t, PULSE WIDTH (sec) Figure 24. Forward Bias Safe Operating Area Figure 25. Single Pulse Maximum Power Dissipation www.onsemi.com 9 FDMS3660S TYPICAL CHARACTERISTICS (Q2 N−Channel) TJ = 25°C unless otherwise noted NORMALIZED THERMAL IMPEDANCE, ZqJA 2 1 0.1 0.01 DUTY CYCLE−DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE 0.0001 −4 10 NOTES: DUTY FACTOR: D = t 1 /t 2 PEAK TJ = PDM x Z qJA x RqJA + TA o 0.001 R qJA = 120 C/W (Note 1d) −3 10 −2 10 −1 10 1 10 t, RECTANGULAR PULSE DURATION (sec) Figure 26. Junction−to−Ambient Transient Thermal Response Curve www.onsemi.com 10 100 1000 FDMS3660S TYPICAL CHARACTERISTICS (continued) SyncFET Schottky Body Diode Characteristics Figure 27 shows the reverses recovery characteristic of the FDMS001N025DSD. Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. ON Semiconductor’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. −2 10 IDSS, REVERSE LEAKAGE CURRENT (A) 35 30 CURRENT (A) 25 didt = 300 A/m s 20 15 10 5 0 −5 0 100 200 300 400 TJ = 125 oC −3 10 TJ = 100 oC −4 10 −5 10 TJ = 25 oC −6 10 0 TIME (ns) 5 10 15 20 25 VDS, REVERSE VOLTAGE (V) Figure 27. FDMS3660S SyncFET Body Diode Reverse Recovery Characteristic Figure 28. SyncFET Body Diode Reverse Leakage vs. Drain−Source Voltage Application Information Switch Node Ringing Suppression ON Semiconductor’s Power Stage products incorporate a proprietary design that minimizes the peak overshoot, ringing voltage on the switch node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the Figure 29, the Power Stage solution rings significantly less than competitor solutions under the same set of test conditions. Power Stage Device Competitors Solution Figure 29. Power Stage Phase Node Rising Edge, High Side Turn On www.onsemi.com 11 FDMS3660S Figure 30. Shows the Power Stage in a Buck Converter Topology Recommended PCB Layout Guidelines PHASE (S1/D2) and GND (S2), should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout procedure is discussed below to maximize the electrical and thermal performance of the part. As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), Figure 31. Recommended PCB Layout www.onsemi.com 12 FDMS3660S Following is a guideline, not a requirement which the PCB designer should consider: within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen the high−frequency ringing. 5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the MOSFET and turns the devices on and off as efficiently as possible. At higher−frequency operation this impedance can limit the gate current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses. Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This provides a very compact path for the drive signals and improves efficiency of the part. 6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET. 7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction. Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected from the backside via a network of low inductance vias. 1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected depending upon the application. 2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in Figure 31 shows a good balance between the thermal and electrical performance of Power Stage. 3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be directly in line (as shown in Figure 31) with the inductor for space savings and compactness. 4. The PowerTrench Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the part to operate well PowerTrench is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) www.onsemi.com 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PQFN8 5X6, 1.27P (SAWN TYPE) CASE 483AJ ISSUE A DOCUMENT NUMBER: DESCRIPTION: 98AON13659G PQFN8 5X6, 1.27P DATE 08 FEB 2021 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PQFN8 5X6, 1.27P (PUNCHED TYPE) CASE 483AJ ISSUE A DATE 08 FEB 2021 D 0.10 C (2X) SEE DETAIL B PKG CL 8 c 5 L2 PKG CL E 1 E1 (SCALE: 2X) 0.10 C (2X) 4 b1 (8X) TOP VIEW 0.10 C D1 SEE DETAIL C c A 8X 0.08 C SIDE VIEW (SCALE: 2X) D2 0.10 0.05 e/2 z1 1 2 3 E3 (6X) C 4 SEATING PLANE C A B C L1 (3X) E4 k e4 E2 e3 D3 k1 8 L (5X) z (3X) 6 7 5 b (8X) e e1 BOTTOM VIEW DOCUMENT NUMBER: DESCRIPTION: 98AON13659G PQFN8 5X6, 1.27P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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