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FDMS8095AC
Dual N & P-Channel PowerTrench® MOSFET
N-Channel: 150 V, 27 A, 30 mΩ P-Channel: -150 V, -2.2 A, 1200 mΩ
Features
General Description
Q1: N-Channel
These dual N and P-Channel enhancement mode Power
MOSFETs are produced using Fairchild Semiconductor’s
advanced PowerTrench® process that has been especially
tailored to minimize on-state resistance and yet maintain
superior switching performance. Shrinking the area needed for
implementation of active clamp topology; enabling best in class
power density.
Max rDS(on) = 30 mΩ at VGS = 10 V, ID = 6.2 A
Max rDS(on) = 41 mΩ at VGS = 6 V, ID = 5.2 A
Q2: P-Channel
Max rDS(on) = 1200 mΩ at VGS = -10 V, ID = -1 A
Max rDS(on) = 1400 mΩ at VGS = -6 V, ID = -0.9 A
Applications
Optimised for active clamp forward converters
DC-DC Converter
RoHS Compliant
Active Clamp
Bottom
Top
S2 S2 S2 G2
G1
D2
Pin 1
D1
Power 56
S1 S1 S1 G1
1
S1
2
S1
3
S1
4
Contact to D1 Contact to D2
(backside)
(backside)
8
7
Q1
Q2
G2
S2
6
S2
5
S2
Pin 1
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
Drain to Source Voltage
VGS
Gate to Source Voltage
ID
Parameter
Q1
150
Drain Current -Continuous
TC = 25 °C
(Note 5)
Drain Current -Continuous
TC = 100 °C
(Note 5)
-Pulsed
Single Pulse Avalanche Energy
EAS
PD
TJ, TSTG
Units
V
±20
±25
V
27
-2.2
17
-1.4
6.2 1a
-1 1b
(Note 4)
143
-8.8
(Note 3)
216
6
2.3 1a
2.3 1b
TA = 25 °C
-Continuous
Q2
-150
mJ
Power Dissipation for Single Operation
TA = 25 °C
Power Dissipation for Single Operation
TA = 25 °C
0.9 1c
0.9 1d
Power Dissipation for Single Operation
TC = 25 °C
50
12.5
Operating and Storage Junction Temperature Range
A
-55 to +150
W
°C
Thermal Characteristics
RθJA
55 1a
Thermal Resistance, Junction to Ambient
RθJA
Thermal Resistance, Junction to Ambient
RθJC
Thermal Resistance, Junction to Case
138
1c
2.5
55 1b
138 1d
°C/W
10
Package Marking and Ordering Information
Device Marking
FDMS8095AC
Device
FDMS8095AC
©2015 Fairchild Semiconductor Corporation
FDMS8095AC Rev.1.0
Package
Power 56
1
Reel Size
13”
Tape Width
12 mm
Quantity
3000 units
www.fairchildsemi.com
FDMS8095AC Dual N & P-Channel PowerTrench® MOSFET
August 2015
Symbol
Parameter
Test Conditions
Type
Min
150
-150
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
ID = -250 μA, VGS = 0 V
Q1
Q2
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
ID = -250 μA, referenced to 25 °C
Q1
Q2
IDSS
Zero Gate Voltage Drain Current
VDS = 120 V, VGS = 0 V
VDS = -120 V, VGS = 0 V
Q1
Q2
1
-1
μA
IGSS
Gate to Source Leakage Current
VGS = ±20 V, VDS = 0 V
VGS = ±25 V, VDS = 0 V
Q1
Q2
±100
±100
nA
nA
4.0
-4.0
V
V
103
122
mV/°C
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
VGS = VDS, ID = -250 μA
Q1
Q2
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
ID = -250 μA, referenced to 25 °C
Q1
Q2
-11
-6
VGS = 10 V, ID = 6.2 A
VGS = 6 V, ID = 5.2 A
VGS = 10 V, ID = 6.2 A, TJ = 125 °C
Q1
25
33
48
30
41
58
VGS = -10 V, ID = -1 A
VGS = -6 V, ID = -0.9 A
VGS = -10 V, ID = -1 A, TJ = 125 °C
Q2
840
940
1520
1200
1400
2171
VDD = 10 V, ID = 6.2 A
VDD = -10 V, ID = -1 A
Q1
Q2
19
0.75
Q1
VDS = 75 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
1441
162
2020
230
pF
Q1
Q2
127
13
180
25
pF
Q1
Q2
4.4
0.6
10
5
pF
1.3
3.3
3.3
8.3
Ω
Q1
Q2
12
5.2
22
11
ns
Q1
Q2
2.7
1.6
10
10
ns
Q2
VDD = -75 V, ID = -1 A,
VGS = -10 V, RGEN = 6 Ω
Q1
Q2
18
7.4
33
15
ns
Q1
Q2
4
6.3
10
13
ns
VGS = 0 V to 10 V
Q1
VGS = 0 V to -10 V
VDD = 75 V,
VGS = 0 V to 6 V
I = 6.2 A
VGS = 0 V to -6 V D
Q1
Q2
21
2.8
30
4
nC
Q1
Q2
13
1.8
19
2.6
nC
Q1
Q2
6.7
0.8
nC
Q1
Q2
3.9
0.7
nC
rDS(on)
gFS
Static Drain to Source On Resistance
Forward Transconductance
2.0
-2.0
3.2
-3.2
mV/°C
mΩ
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate Resistance
Q2
VDS = -75 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
0.1
0.1
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
Fall Time
Qg(TOT)
Total Gate Charge
Qg(TOT)
Total Gate Charge
Qgs
Gate to Source Charge
Qgd
Gate to Drain “Miller” Charge
©2015 Fairchild Semiconductor Corporation
FDMS8095AC Rev.1.0
Q1
VDD = 75 V, ID = 6.2 A,
VGS = 10 V, RGEN = 6 Ω
Q2
VDD = -75 V
ID = -1 A
2
www.fairchildsemi.com
FDMS8095AC Dual N & P-Channel PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Q1
Q2
0.8
-0.9
1.3
-1.3
V
Q1
Q2
69
44
111
71
ns
Q1
Q2
106
68
170
109
nC
Drain-Source Diode Characteristics
VSD
Source-Drain Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = 6.2 A
VGS = 0 V, IS = -1 A
(Note 2)
(Note 2)
Q1
IF = 6.2 A, di/dt = 100 A/s
Q2
IF = -1 A, di/dt = 100 A/s
Notes:
1. RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθCA is determined by the user's board design.
a.55 °C/W when mounted on
a 1 in2 pad of 2 oz copper
b.55 °C/W when mounted on
a 1 in2 pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
c. 138 °C/W when mounted on a
minimum pad of 2 oz copper
d. 138 °C/W when mounted on a
minimum pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. Q1: EAS of 216 mJ is based on starting TJ = 25 oC, L = 3 mH, IAS = 12 A, VDD = 150 V, VGS = 10 V. 100% test at L = 0.3 mH, IAS = 28 A.
Q2: EAS of 6 mJ is based on starting TJ = 25 oC, L = 3 mH, IAS = -2 A, VDD = -150 V, VGS = -10 V. 100% test at L = 0.3 mH, IAS = -6.9 A.
4. Pulsed Id please refer to Fig 11 SOA graph for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
©2015 Fairchild Semiconductor Corporation
FDMS8095AC Rev.1.0
3
www.fairchildsemi.com
FDMS8095AC Dual N & P-Channel PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted
100
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
2.4
ID, DRAIN CURRENT (A)
VGS = 10 V
80
VGS = 8 V
VGS = 7 V
60
VGS = 6 V
40
VGS = 5.5 V
20
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0
1
2
3
4
VGS = 5.5 V
2.2
2.0
VGS = 6 V
1.8
1.6
VGS = 7 V
1.4
1.2
VGS = 10 V
1.0
0.8
5
VGS = 8 V
0
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
rDS(on), DRAIN TO
2.0
1.5
1.0
0.5
-75
-50
-25
0
25
50
75
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
100
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID = 6.2 A
100
TJ = 125 oC
50
TJ = 25 oC
0
100 125 150
4
TJ, JUNCTION TEMPERATURE (oC)
IS, REVERSE DRAIN CURRENT (A)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VDS = 5 V
60
TJ = 150 oC
TJ = 25 oC
20
TJ = -55
3
4
5
6
oC
7
200
100
7
8
9
10
VGS = 0 V
10
TJ = 150 oC
1
TJ = 25 oC
0.1
TJ = -55 oC
0.01
0.001
0.0
8
VGS, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
©2015 Fairchild Semiconductor Corporation
FDMS8095AC Rev.1.0
6
Figure 4. On-Resistance vs Gate to
Source Voltage
100
40
5
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
ID, DRAIN CURRENT (A)
80
150
ID = 6.2 A
VGS = 10 V
2
60
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
2.5
0
40
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
80
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
4
www.fairchildsemi.com
FDMS8095AC Dual N & P-Channel PowerTrench® MOSFET
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
VGS, GATE TO SOURCE VOLTAGE (V)
10
10000
ID = 6.2 A
Ciss
8
CAPACITANCE (pF)
VDD = 50 V
VDD = 75 V
6
VDD = 100 V
4
2
0
1000
Coss
100
Crss
10
f = 1 MHz
VGS = 0 V
0
5
10
15
20
1
0.1
25
Figure 7. Gate Charge Characteristics
100
30
ID, DRAIN CURRENT (A)
TJ = 25 oC
10
TJ = 100
oC
TJ = 125 oC
24
VGS = 10 V
18
VGS = 6 V
12
6
o
RθJC = 2.5 C/W
1
0.001
0.01
0.1
1
10
0
25
100
50
100
10000
P(PK), PEAK TRANSIENT POWER (W)
20000
10 μs
10
0.1
0.01
0.1
100 μs
1 ms
SINGLE PULSE
TJ = MAX RATED
RθJC = 2.5 oC/W
TC = 25 oC
1
10 ms
CURVE BENT TO
MEASURED DATA
10
DC
100
1000
150
SINGLE PULSE
RθJC = 2.5 oC/W
TC = 25 oC
1000
100
10
-5
10
-4
10
-3
10
-2
10
-1
10
1
t, PULSE WIDTH (sec)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
©2015 Fairchild Semiconductor Corporation
FDMS8095AC Rev.1.0
125
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
300
1
100
TC, CASE TEMPERATURE ( C)
Figure 9. Unclamped Inductive
Switching Capability
THIS AREA IS
LIMITED BY rDS(on)
75
o
tAV, TIME IN AVALANCHE (ms)
ID, DRAIN CURRENT (A)
10
Figure 8. Capacitance vs Drain
to Source Voltage
100
IAS, AVALANCHE CURRENT (A)
1
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 12. Single Pulse Maximum Power
Dissipation
5
www.fairchildsemi.com
FDMS8095AC Dual N & P-Channel PowerTrench® MOSFET
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
2
1
0.1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
t2
0.01
NOTES:
SINGLE PULSE
0.001
-5
10
ZθJC(t) = r(t) x RθJC
RθJC = 2.5 oC/W
Peak TJ = PDM x ZθJC(t) + TC
Duty Cycle, D = t1 / t2
-4
10
-3
-2
10
10
-1
10
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Case Transient Thermal Response Curve
©2015 Fairchild Semiconductor Corporation
FDMS8095AC Rev.1.0
6
www.fairchildsemi.com
FDMS8095AC Dual N & P-Channel PowerTrench® MOSFET
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
4
1.8
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
-ID, DRAIN CURRENT (A)
VGS = -10 V
VGS = -7 V
3
VGS = -6 V
VGS = -5.5 V
2
VGS = -5 V
1
0
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
1
2
3
4
-VDS, DRAIN TO SOURCE VOLTAGE (V)
5
VGS = -5.5 V
1.4
1.2
1.0
0.8
0
2
3
4
3000
rDS(on), DRAIN TO
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
-75
-50
-25
0
25
50
75
SOURCE ON-RESISTANCE (mΩ)
ID = -1 A
VGS = -10 V
2.0
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
2500
ID = -1 A
2000
TJ = 125 oC
1500
TJ = 25 oC
1000
4
100 125 150
TJ, JUNCTION TEMPERATURE (oC)
5
6
7
8
9
10
-VGS, GATE TO SOURCE VOLTAGE (V)
Figure 17. On-Resistance vs Gate to
Source Voltage
Figure 16. Normalized On-Resistance
vs Junction Temperature
4
-IS, REVERSE DRAIN CURRENT (A)
5
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
-ID, DRAIN CURRENT (A)
1
VGS = -10 V
VGS = -7 V
VGS = -6 V
Figure 15. Normalized on-Resistance vs Drain
Current and Gate Voltage
2.2
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
1.6
-ID, DRAIN CURRENT (A)
Figure 14. On- Region Characteristics
3
VDS = -5 V
2
TJ = 150 oC
TJ = 25 oC
1
TJ = -55 oC
0
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = -5 V
2
3
4
5
6
TJ = 150 oC
0.1
TJ = 25 oC
0.01
TJ = -55 oC
0.001
0.0
7
-VGS, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
1.2
-VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 18. Transfer Characteristics
©2015 Fairchild Semiconductor Corporation
FDMS8095AC Rev.1.0
VGS = 0 V
1
Figure 19. Source to Drain Diode
Forward Voltage vs Source Current
7
www.fairchildsemi.com
FDMS8095AC Dual N & P-Channel PowerTrench® MOSFET
Typical Characteristics (Q2 P-Channel) TJ = 25 °C unless otherwise noted
ID = -1 A
Ciss
8
VDD = -75 V
VDD = -50 V
6
VDD = -100 V
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
100
CAPACITANCE (pF)
-VGS, GATE TO SOURCE VOLTAGE (V)
1000
10
Coss
10
Crss
1
f = 1 MHz
VGS = 0 V
0.1
0.1
3.5
100
2.5
-ID, DRAIN CURRENT (A)
20
-IAS, AVALANCHE CURRENT (A)
10
Figure 21. Capacitance vs Drain
to Source Voltage
Figure 20. Gate Charge Characteristics
10
TJ =
25 oC
TJ = 100 oC
TJ = 125 oC
2.0
VGS = -10 V
1.5
VGS = -6 V
1.0
0.5
o
RθJC = 10 C/W
1
0.001
0.01
0.1
0.0
25
1
75
100
125
150
TC, CASE TEMPERATURE ( C)
Figure 23. Maximum Continuous Drain
Current vs Case Temperature
Figure 22. Unclamped Inductive
Switching Capability
20
300
1
P(PK), PEAK TRANSIENT POWER (W)
10
100 μs
THIS AREA IS
LIMITED BY rDS(on)
0.1
1 ms
SINGLE PULSE
TJ = MAX RATED
o
RθJC = 10 C/W
0.01
50
o
tAV, TIME IN AVALANCHE (ms)
-ID, DRAIN CURRENT (A)
1
-VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
TC = 25 oC
1
CURVE BENT TO
MEASURED DATA
10
10 ms
DC
100
600
TC = 25 oC
100
10
-4
10
-3
10
-2
10
-1
10
1
t, PULSE WIDTH (sec)
-VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 24. Forward Bias Safe
Operating Area
©2015 Fairchild Semiconductor Corporation
FDMS8095AC Rev.1.0
SINGLE PULSE
RθJC = 10 oC/W
Figure 25. Single Pulse Maximum Power
Dissipation
8
www.fairchildsemi.com
FDMS8095AC Dual N & P-Channel PowerTrench® MOSFET
Typical Characteristics (Q2 P-Channel) TJ = 25°C unless otherwise noted
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
0.1
t2
NOTES:
SINGLE PULSE
ZθJC(t) = r(t) x RθJC
RθJC = 10 oC/W
Peak TJ = PDM x ZθJC(t) + TC
Duty Cycle, D = t1 / t2
0.01
-4
10
-3
-2
10
10
-1
10
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 26. Junction-to-Case Transient Thermal Response Curve
©2015 Fairchild Semiconductor Corporation
FDMS8095AC Rev.1.0
9
www.fairchildsemi.com
FDMS8095AC Dual N & P-Channel PowerTrench® MOSFET
Typical Characteristics (Q2 P-Channel) TJ = 25 °C unless otherwise noted
5.00
0.10 C
A
B
2X
4.41 (2X)
4.10 (2X)
0.67 (6X)
7
6
8
5
0.50
1.75(2X)
6.00
2.26
PIN#1
IDENT
6.30
1.15 2X
0.50 (2X)
0.65(8X)
0.10 C
TOP VIEW
2X
2
1
4
0.60(8X)
1.27
8X
0.10 C
3
0.635
0.80 MAX
(0.20)
RECOMMENDED LAND PATTERN
0.08 C
0.05
0.00
SIDE VIEW
C
SEATING
PLANE
0.635
1.27
8X
(0.35)4X
PIN#1
IDENT
(0.77) 6X
1
3
2
4
0.25(4X)
0.15
1.80 (2)X
1.70
1.125 2X
0.55(8X)
0.45
(0.50)3X
0.55 8X
0.45
0.10
0.05
C A B
C
8
7
6
(3.04) 2X
4.15 (2X)
4.05
BOTTOM VIEW
5
NOTES:
A. DOES NOT FULLY CONFORM TO JEDEC
REGISTRATION, MO-229.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY.
E. DRAWING FILENAME: MKT-MLP08Zrev1.
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