FND43060T2

Motion SPM) 45 Series FND43060T2 General Description FND43060T2 is an advanced Motion SPM 45 module providing a fully−featured, high−performance inverter output stage for AC Induction, BLDC, and PMSM motors. These modules integrate optimized gate drive of the built−in IGBTs to minimize EMI and losses, while also providing multiple on−module protection features including under−voltage lockouts, over−current shutdown, thermal monitoring, and fault reporting. The built−in, high−speed HVIC requires only a single supply voltage and translates the incoming logic−level gate inputs to the high−voltage, high−current drive signals required to properly drive the module’s robust short−circuit−rated IGBTs. Separate negative IGBT terminals are available for each phase to support the widest variety of control algorithms. www.onsemi.com Features • UL Certified No. E209204 (UL1557) • 600 V − 30 A 3−Phase IGBT Inverter with Integral Gate Drivers • • • • • • • • and Protection Low Thermal Resistance Using Ceramic Substrate Low−Loss, Short−Circuit Rated IGBTs Built−In Bootstrap Diodes and Dedicated Vs Pins Simplify PCB Layout Built−In NTC Thermistor for Temperature Monitoring Separate Open−Emitter Pins from Low−Side IGBTs for Three−Phase Current Sensing Single−Grounded Power Supply Isolation Rating: 4000 Vrms/min Remove Dummy Pin SPMAA−C26 CASE MODFC Figure 1. Package Overview (Click to Activate 3D Content) MARKING DIAGRAM Applications • Motion Control − Home Appliance/Industrial Motor XXXXXXXXXXX ZZZ ATYWW NNNNNNN Related Resources • AN−9084 − Smart Power Module, Motion SPM® 45 H V3 Series User’s Guide • AN−9072 − Smart Power Module, Motion SPM® in SPM45H • • Thermal Performance Information AN−9071 − Smart Power Module Motion SPM® in SPM45H Mounting Guidance AN−9760 − PCB Design Guidance for SPM® Integrated Power Functions power conversion (Refer to Figure 3) January, 2021 − Rev. 4 = Specific Device Code = Lot ID = Assembly and Test Location = Year = Work Week = Serial Number ORDERING INFORMATION • 600 V−30 A IGBT inverter for three−phase DC/AC © Semiconductor Components Industries, LLC, 2017 XXXX ZZZ AT Y WW NNN 1 Device Package Shipping FND43060T2 SPMAA−J26 12 Units/Rail Publication Order Number: FND43060T2/D FND43060T2 Integrated Drive, Protection and System Control Functions • For inverter high−side IGBTs: gate drive circuit, • • Fault signaling: corresponding to UVLO (low−side high−voltage isolated high−speed level shifting control circuit Under−Voltage Lock−Out (UVLO) protection For inverter low−side IGBTs: gate drive circuit, Short−Circuit Protection (SCP) control supply circuit, Under−Voltage Lock−Out (UVLO) protection supply) and SC faults • Input interface: active−HIGH interface, works with 3.3/5 V logic, Schmitt−trigger input PIN CONFIGURATION VB(U) (26) VTH (1) VS(U) (25) RTH (2) VB(V) (24) VS(V) (23) P (3) VB(W) (22) VS(W) (21) U (4) Case temperature (TC) Detecting Point INUH (20) INVH (19) INWH (18) V (5) VCC(H) (17) VCC(L) (16) W (6) COM (15) IN(UL) (14) NU (7) IN(VL) (13) IN(WL) (12) NV (8) VFO (11) CSC (10) NW (9) Figure 2. Top View www.onsemi.com 2 FND43060T2 PIN DESCRIPTIONS Pin Number Pin Name Pin Description 1 VTH Thermistor Bias Voltage 2 RTH Series Resistor for the Use of Thermistor (Temperature Detection) 3 P Positive DC−Link Input 4 U Output for U−Phase 5 V Output for V−Phase 6 W Output for W−Phase 7 NU Negative DC−Link Input for U−Phase 8 NV Negative DC−Link Input for V−Phase 9 NW Negative DC−Link Input for W−Phase 10 CSC Capacitor (Low−Pass Filter) for Short−circuit Current Detection Input 11 VFO Fault Output 12 IN(WL) Signal Input for Low−Side W−Phase 13 IN(VL) Signal Input for Low−Side V−Phase 14 IN(UL) Signal Input for Low−Side U−Phase 15 COM Common Supply Ground 16 VDD(L) Low−Side Common Bias Voltage for IC and IGBTs Driving 17 VDD(H) High−Side Common Bias Voltage for IC and IGBTs Driving 18 IN(WH) Signal Input for High−Side W−Phase 19 IN(VH) Signal Input for High−Side V−Phase 20 IN(UH) Signal Input for High−Side U−Phase 21 VS(W) High−Side Bias Voltage Ground for W−Phase IGBT Driving 22 VB(W) High−Side Bias Voltage for W−Phase IGBT Driving 23 VS(V) High−Side Bias Voltage Ground for V−Phase IGBT Driving 24 VB(V) High−Side Bias Voltage for V−Phase IGBT Driving 25 VS(U) High−Side Bias Voltage Ground for U−Phase IGBT Driving 26 VB(U) High−Side Bias Voltage for U−Phase IGBT Driving www.onsemi.com 3 FND43060T2 INTERNAL EQUIVALENT CIRCUIT AND INPUT/OUTPUT PINS VTH (1) Thermister VB(U) (26) VS(U) (25) VB(V) (24) VS(V) (23) VB(W) (22) VS(W) (21) INUH (20) INVH (19) INWH (18) VDD(H) (17) P (3) UVB UVS OUT(UH) VVB UVS COM (15) IN(UL) (14) IN(VL) (13) IN(WL) (12) VFO (11) CSC (10) U (4) VVS WVB WVS OUT(VH) IN(UH) IN(VH) IN(WH) VDD VVS V (5) OUT(WH) COM VDD(L) (16) RTH (2) WVS VDD W (6) OUT(UL) COM NU (7) IN(UL) IN(VL) OUT(VL) IN(WL) NV (8) VFO C(SC) OUT(WL) NW (9) NOTES: 1. Inverter high−side is composed of three IGBTs, freewheeling diodes, and one control IC for each IGBT. 2. Inverter low−side is composed of three IGBTs, freewheeling diodes, and one control IC for each IGBT. It has gate drive and protection functions. 3. Inverter power side is composed of four inverter DC−link input terminals and three inverter output terminals. Figure 3. Internal Block Diagram www.onsemi.com 4 FND43060T2 ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise specified) Symbol Parameter Conditions Rating Unit INVERTER PART VPN VPN(Surge) VCES Supply Voltage Applied between P−NU, NV, NW 450 V Supply Voltage (Surge) Applied between P−NU, NV, NW 500 V 600 V Collector−Emitter Voltage ±IC Each IGBT Collector Current TC = 25°C, TJ < 150°C 30 A ±ICP Each IGBT Collector Current (Peak) TC = 25°C, TJ < 150°C, Under 1 ms Pulse Width (Note 1) 60 A PC Collector Dissipation TC = 25°C per One Chip (Note 1) 59 W TJ Operating Junction Temperature −40 ∼ 150 °C CONTROL PART VDD Control Supply Voltage Applied between VDD(H), VDD(L) − COM 20 V VBS High−Side Control Bias Voltage Applied between VB(U) − VS(U), VB(V) − VS(V), VB(W) − VS(W) 20 V VIN Input Signal Voltage Applied between IN(UH), IN(VH), IN(WH), IN(UL), IN(VL), IN(WL) − COM −0.3 ∼ VDD+0.3 V VFO Fault Output Supply Voltage Applied between VFO − COM −0.3 ∼ VDD+0.3 V IFO Fault Output Current Sink Current at VFO pin 1 mA VSC Current Sensing Input Voltage Applied between CSC − COM −0.3∼ VDD+0.3 V 600 V BOOTSTRAP DIODE PART VRRM Maximum Repetitive Reverse Voltage IF Forward Current TC = 25°C, TJ < 150°C 0.50 A IFP Forward Current (Peak) TC = 25°C, TJ < 150°C, Under 1 ms Pulse Width (Note 1) 2.0 A TJ Operating Junction Temperature −40 ∼ 150 °C 400 V −40 ∼ 125 °C TOTAL SYSTEM VPN(PROT) Self−Protection Supply Voltage Limit (Short−Circuit Protection Capability) VDD = VBS = 13.5 V ∼ 16.5 V TJ = 150°C, Non−repetitive, < 2 ms TC Module Case Operation Temperature See Figure 2 TSTG Storage Temperature VISO Isolation Voltage −40 ∼ 125 °C 4000 Vrms 60 Hz, Sinusoidal, AC 1 minute, Connect Pins to Heat Sink Plate (Note 3) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE Symbol Rth(j−c)Q Rth(j−c)F Parameter Junction to Case Thermal Resistance (Note 2) Conditions Min. Typ. Max. Unit Inverter IGBT Part (per 1/6 module) − − 2.1 °C/W Inverter FWDi Part (per 1/6 module) − − 2.8 °C/W 1. These values had been made an acquisition by the calculation considered to design factor. 2. For the measurement point of case temperature (TC), please refer to Figure 2. 3. For Recommended Heat−Sink Design, please see Figure 11. If do not follow Recommended, Viso is 2000 Vrms. www.onsemi.com 5 FND43060T2 ELECTRICAL CHARACTERISTICS − INVERTER PART (TJ = 25°C unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit VCE(SAT) Collector − Emitter Saturation Voltage VDD = VBS = 15 V, VIN = 5 V IC = 30 A, TJ = 25°C − 1.65 2.25 V FWDi Forward Voltage VIN = 0 V IF = 30 A, TJ = 25°C − 2.00 2.60 V Switching Times VPN = 300 V, VDD = VBS = 15 V, IC = 30 A, TJ = 25°C VIN = 0 V ⇔ 5 V, Inductive Load (Note 4) 0.45 0.85 1.35 ms − 0.20 0.50 ms − 0.70 1.20 ms tC(OFF) − 0.15 0.45 ms trr − 0.10 − ms 0.5 0.90 1.40 ms − 0.30 0.60 ms − 0.80 1.30 ms tC(OFF) − 0.15 0.45 ms trr − 0.15 − ms − − 1 mA VF HS tON Conditions tC(ON) tOFF LS VPN = 300 V, VDD = VBS = 15 V, IC = 30 A, TJ = 25°C VIN = 0 V ⇔ 5 V, Inductive Load (Note 4) tON tC(ON) tOFF ICES Collector−Emitter Leakage Current VCE = VCES Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. tON and tOFF include the propagation delay of the internal drive IC. tC(ON) and tC(OFF) are the switching time of IGBT itself under the given gate driving condition internally. For the detailed information, please see Figure 4. 100% IC 100% IC trr IC VCE IC VIN VIN tON 10% IC VIN(ON) VCE tOFF tc(ON) tc(OFF) VIN(OFF) 90% IC 10% VCE (a) turn − on 10% VCE (b) turn − off Figure 4. Switching Time Definition www.onsemi.com 6 10% IC FND43060T2 Inductive Load, VPN = 300 V, VDD = 15 V, TJ = 25°C 2000 IGBT Turn−ON, Eon IGBT Turn−OFF, Eoff IGBT Turn−OFF, Erec 1600 1400 1200 1000 800 600 1600 1400 1200 1000 800 600 400 400 200 200 0 0 5 10 IGBT Turn−ON, Eon IGBT Turn−OFF, Eoff IGBT Turn−OFF, Erec 1800 SWITCHING LOSS, ESW [mJ] SWITCHING LOSS, ESW [mJ] 1800 Inductive Load, VPN = 300 V, VDD = 15 V, TJ = 150°C 2000 15 20 25 0 30 0 COLLECTOR CURRENT, IC [AMPERES] 5 10 15 20 25 30 COLLECTOR CURRENT, IC [AMPERES] Figure 5. Switching Loss Characteristics (Typical) CONTROL PART Symbol Parameter IQDDH Quiescent VDD Supply Current IQDDL IPDDH Operating VDD Supply Current IPDDL Conditions Min. Typ. Max. Unit VDD(H) = 15 V, IN(UH,VH.WH) = 0 V VDD(H) − COM − − 0.10 mA VDD(L) = 15 V, IN(UL,VL,WL) = 0 V VDD(L) − COM − − 2.65 mA VDD(H) = 15 V, fPWM = 20 kHz, duty = 50%, Applied to one PWM Signal Input for High−Side VDD(H) − COM − − 0.15 mA VDD(L) = 15 V, fPWM = 20 kHz, duty = 50%, Applied to one PWM Signal Input for Low−Side VDD(L) − COM − − 4.00 mA IQBS Quiescent VBS Supply Current VBS = 15 V, IN(UH,VH.WH) = 0 V VB(U) − VS(U), VB(V) − VS(V), VB(W) − VS(W), − − 0.30 mA IPBS Operating VBS Supply Current VDD = VBS = 15 V, fPWM = 20 kHz, duty = 50%, Applied to one PWM Signal Input for High−Side VB(U) − VS(U), VB(V) − VS(V), VB(W) − VS(W), − − 2.00 mA VFOH Fault Output Voltage VSC = 0 V, VFO Circuit: 4.7 kW to 5 V Pull−up 4.5 − − V VSC = 1 V, VFO Circuit: 4.7 kW to 5 V Pull−up − − 0.5 V 0.45 0.50 0.55 V 10.5 − 13.0 V VFOL VSC(ref) Short Circuit Trip Leve VDD = 15 V (Note 5) UVDDD Supply Circuit Under−Voltage Protection Detection Level UVDDR CSC−COM Reset Level 11.0 − 13.5 V UVBSD Detection Level 10.0 − 12.5 V UVBSR Reset Level 10.5 − 13.0 V 30 − − ms − − 2.6 V 0.8 − − V @ TTH = 25°C (Note 6) − 47 − kW @ TTH = 100°C − 2.9 − kW tFOD Fault−Out Pulse Width VIN(ON) ON Threshold Voltage VIN(OFF) OFF Threshold Voltage RTH Resistance of Thermistor Applied between IN(UH), IN(VH), IN(WH), IN(UL), IN(VL), IN(WL) − COM 5. Short−circuit current protection os functioning only at the low−sides. 6. TTH is the temperature of thermister itself. To know case temperature (TC), please make the experiment considering your application. www.onsemi.com 7 FND43060T2 R−T Curve 600 R−T Curve in 505C ~ 1255C 550 20 500 16 Resistance [kW] 450 Resistance [kW] 400 350 300 12 8 4 250 0 50 200 60 70 80 90 100 110 120 100 110 Temperature [5C] 150 100 50 0 −20 −10 0 10 20 30 40 50 60 70 80 90 120 Temperature, TTH [5C] Figure 6. R−T Curve of the Built−In Thermistor BOOTSTRAP DIODE PART Symbol Parameter Conditions Min. Typ. Max. Unit VF Forward Voltage IF = 0.1 A, TC = 25°C − 2.5 − V trr Reverse−Recovery Time IF = 0.1 A, dIF/dt = 50 A/ms, TJ = 25°C − 80 − ns Built−In Bootstrap Diode VF−IF Characteristic 1.0 0.9 0.8 0.7 IF [A] 0.6 0.5 0.4 0.3 0.2 0.1 0.0 TC = 25°C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VF [V] NOTE: Built−in bootstrap diode includes around 15 W resistance characteristic. Figure 7. Built−In Bootstrap Diode Characteristics www.onsemi.com 8 FND43060T2 RECOMMENDED OPERATING CONDITIONS Parameter Symbol Conditions Min. Typ. Max. Unit − 300 400 V VPN Supply Voltage Applied between P − NU, NV, NW VDD Control Supply Voltage Applied between VDD(H) − COM, VDD(L) − COM 13.5 15.0 16.5 V VBS High−Side Bias Voltage Applied between VB(U) − VS(U), VB(V) − VS(V), VB(W) − VS(W) 13.0 15.0 18.5 V dVDD/dt, dVBS/dt Control Supply Variation −1 − 1 V/ms 1.0 − − ms tdead Blanking Time for Preventing Arm−Short For Each Input Signal fPWM PWM Input Signal −40°C ≤ TC ≤ 150°C, −40°C ≤ TJ ≤ 150°C − − 20 kHz VSEN Voltage for Current Sensing Applied between NU, NV, NW − COM (Including Surge Voltage) −4 − 4 V PWIN(ON) Minimum Input Pulse Width VDD = VBS = 15 V, IC ≤ 60 A, Wiring Inductance between NU, NV, NW and DC Link N < 10 nH (Note 7) 1.2 − − ms 1.2 − − −40 − 150 PWIN(OFF) TJ Junction Temperature °C 7. This product might not make response if input pulse width is less than the recommended value. Allowable Maximum Output Current Allowable Output Current, IOrms [Arms] 18 fSW = 5 kHz 16 14 12 10 fSW = 15 kHz 8 6 VDC = 300 V, VDD = VBS = 15 V, TJ = 150°C, TC = 125°C M.I. = 0.9, P.F. = 0.8 Sinusoidal PWM 4 2 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Case Temperature, TC [5C] NOTE: This allowable output current value is the reference data for the safe operation of this product. This may be different from the actual application and operating condition Figure 8. Allowable Maximum Output Current MECHANICAL CHARACTERISTICS AND RATINGS Value Parameter Conditions Device Flatness See Figure 9 Mounting Torque Mounting Screw: M3 See Figure 10 Typ. Max. Unit 0 − +120 mm Recommended 0.7 N•m 0.6 0.7 0.8 N•m Recommended 7.1 kg•cm 6.2 7.1 8.1 kg•cm − 11.00 − g Weight www.onsemi.com 9 Min. FND43060T2 Figure 9. Flatness Measurement Position Pre−Screwing: 1 à 2 Final Screwing: 2 à 1 Figure 10. Mounting Screws Torque Order Figure 11. Recommended Heat−Sink Design NOTES: 8. Do not make over torque when mounting screws. Much mounting torque may cause ceramic cracks, as well as bolts and Al heat−sink destruction. 9. Avoid one side tightening stress. Figure 10 shows the recommended torque order for mounting screws. Uneven mounting can cause the ceramic substrate of the SPM 45 package to be damaged. The pre−screwing torque is set to 20 ∼ 30% of maximum torque rating. www.onsemi.com 10 FND43060T2 TIME CHARTS OF PROTECTIVE FUNCTION Input signal Protection Circuit State RESET UVDDR Control Supply Voltage SET a1 RESET a6 UVDDD a3 a2 a7 a4 Output Current a5 Fault Output Signal a1: Control supply voltage rises: after the voltage rises UVDDR, the circuits start to operate when next input is applied. a2: Normal operation: IGBT ON and carrying current. a3: Under voltage detection (UVDDD). a4: IGBT OFF in spite of control input condition. a5: Fault output operation starts. a6: Under voltage reset (UVDDR). a7: Normal operation: IGBT ON and carrying current. Figure 12. Under−Voltage Protection (Low−Side) Input signal Protection Circuit State RESET UVBSR Control Supply Voltage SET b1 UVBSD b3 RESET b5 b6 b2 b4 Output Current Fault Output Signal High−level (no fault output) b1: Control supply voltage rises: after the voltage reaches UVBSR, the circuits start to operate when next input is applied. b2: Normal operation: IGBT ON and carrying current. b3: Under voltage detection (UVBSD). b4: IGBT OFF in spite of control input condition, but there is no fault output signal. b5: Under voltage reset (UVBSR). b6: Normal operation: IGBT ON and carrying current.. Figure 13. Under−Voltage Protection (High−Side) www.onsemi.com 11 FND43060T2 Lower Arms Control Input c6 Protection Circuit State SET Internal IGBT Gate−Emitter Voltage c2 c3 c7 RESET c4 SC c1 c8 Output Current SC Reference Voltage Sensing Voltage of Shunt Resistance Fault Output Signal c5 CR Circuit Time Constant Delay (with the external sense resistance and CR connection) c1: Normal operation: IGBT ON and carrying current. c2: Short−circuit current detection (SC trigger). c3: Hard IGBT gate interrupt. c4: IGBT turns OFF. c5: Input “LOW”:IGBT OFF state. c6: Input “HIGH”: IGBT ON state, but during the active period of fault output the IGBT doesn’t turn ON. c7: IGBT OFF state. c8: Normal operation: IGBT ON and carrying current. Figure 14. Short−Circuit Protection (Low−Side Operation Only) INPUT/OUTPUT INTERFACE CIRCUIT +5 V (for MCU and Control power) SPM (WH) RPF = 10 kΩ IN(UH), IN(VH), IN(WH) IN(UL), IN(VL), IN(WL) MCU VFO COM NOTE: 10. RC coupling at each input (parts shown dotted) might change depending on the PWM control scheme in the application and the wiring impedance of the application’s printed circuit board. The input signal section of the Motion SPM 45 product integrates a 5 kW (typ.) pull−down resistor. Therefore, when using an external filtering resistor, pay attention to the signal voltage drop at input terminal. Figure 15. Recommended MCU I/O Interface Circuit www.onsemi.com 12 FND43060T2 (26) V B(U) CBS CBSC RS (25) V S(U) (20) IN (UH) Gating UH (24) V B(V) CBSC CBS RS (23) V S(V) (19) IN(VH) Gating VH (22) V B(W) CBSC CBS M C U RS Gating WH (18) IN (WH) (17) VDD(H) +15 V CPS (21) V S(W) CPS CPS CSPC15 CSP15 +5 V (15) COM (17) VDD(L) HVIC VS(U) VS(V) IN(VH) Gating WL OUT(VH) VS(V) V (5) M VB(W) VS(W) IN(WH) VCC CDCS OUT(WH) VS(W) VDC W (6) COM LVIC VDD NU (7) CSPC05 CSP05 (11) V FO Fault Gating VL U (4) VS(U) VB(V) OUT(UL) RS Gating UL OUT(UH) IN(UH) RPF CBPF P (3) VB(U) RSU VFO CPF RS (14) IN (UL) RS (13) IN (VL) RS (12) IN (WL) CSC (10) CSC CPS CPS CPS RF RTH Input Signal for Short−Circuit Protection OUT(VL) IN(UL) NV (8) RSV IN(VL) IN(WL) COM OUT(WL) CSC NW (9) RSW (1) VTH (2) RTH THERMISTOR Temp. Monitoring U−Phase Current V−Phase Current W−Phase Current NOTES: 11. To avoid malfunction, the wiring of each input should be as short as possible. (less than 2−3 cm). 12. VFO output is open−drain type. The signal line should be pulled up to the positive side of the MCU or control power supply with a resistor that makes IFO up to 1 mA. 13. CSP15 of around seven times larger than bootstrap capacitor CBS is recommended. 14. Input signal is active−HIGH type. There is a 5 kW resistor inside the IC to pull−down each input signal line to GND. RC coupling circuits is recommended for the prevention of input signal oscillation. RSCPS time constant should be selected in the range 50 ∼ 150 ns (recommended RS = 100 W, CPS = 1 nF). 15. To prevent errors of the protection function, the wiring around RF and CSC should be as short as possible 16. In the short−circuit protection circuit, please select the RFCSC time constant in the range 1.5 ∼ 2 ms. Do enough evaluation on the real system because short−circuit protection time may vary wiring pattern layout and value of the RFCSC time constant. 17. The connection between control GND line and power GND line which includes the NU, NV, NW must be connected to only one point. Please do not connect the control GND to the power GND by the broad pattern. Also, the wiring distance between control GND and power GND should be as short as possible. 18. Each capacitor should be mounted as close to the pins of the Motion SPM 45 product as possible. 19. To prevent surge destruction, the wiring between the smoothing capacitor and the P & GND pins should be as short as possible. The use of a high−frequency non−inductive capacitor of around 0.1 ∼ 0.22 ms between the P and GND pins is recommended. 20. Relays are used in almost every systems of electrical equipment in home appliances. In these cases, there should be sufficient distance between the MCU and the relays. 21. The zener diode or transient voltage suppressor should be adopted for the protection of ICs from the surge destruction between each pair of control supply terminals (recommended zener diode is 22 V/1 W. which has the lower zener impedance characteristic than about 15 W). 22. Please choose the electrolytic capacitor with good temperature characteristic in CBS. Also choose 0.1 ∼ 0.2 mF R−category ceramic capacitors with good temperature and frequency characteristics in CBSC. Figure 16. Typical Application Circuit SPM is registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SPMAA−C26 / 26LD, PDD STD CERAMIC TYPE, LONG LEAD DUAL FORM TYPE CASE MODFC ISSUE O DATE 31 JAN 2017 DOCUMENT NUMBER: DESCRIPTION: 98AON13555G Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. SPMAA−C26 / 26LD, PDD STD CERAMIC TYPE, LONG LEAD DUAL PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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