FOD0720R2

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This literature is subject to all applicable copyright laws and is not for resale in any manner. FOD0721, FOD0720, FOD0710 High CMR, 25Mbit/sec Logic Gate Optocoupler Features Description ■ 20kV/µs minimum CMR The FOD0721/0720/0710 family utilizes Fairchild’s proprietary coplanar packaging technology, Optoplanar,® and optimized IC design to guarantee minimum 20kV/µs Common Mode Noise Rejection (CMR) rating. ■ 40ns max. propagation delay ■ Data Rate, Non-Return Zero Coding ■ ■ ■ ■ – 25Mbit/sec (FOD0721 and FOD0720) – 12.5Mbit/sec (FOD0710) Pulse Width Distortion – 6ns (FOD0721) – 8ns (FOD0720 and FOD0710) +5V CMOS compatibility Extended industrial temperate range – -40 to 100°C temperature range Safety and regulatory approvals – UL1577, 3750 VACrms for 1 min. (File #E90700, Volume 2) – IEC60747-5-2 pending approval These high-speed logic gate optocouplers consist of a high-speed AlGaAs LED driven by a CMOS IC coupled to a CMOS detector IC, comprising an integrated photodiode, a high-speed transimpedance amplifier and a voltage comparator with an output driver. The CMOS technology coupled to the high efficiency of the LED achieves low power consumption as well as very high speed (40ns propagation delay, 6ns pulse width distortion). These devices are available in a compact 8-pin small outline package. Applications ■ Industrial fieldbus communications – Profibus, DeviceNet, CAN, RS485 ■ Programmable logic control ■ Isolated data acquisition system Functional Schematic 8 VDD2 VDD1 1 VI 2 7 NC 3 6 VO * GND1 4 5 GND2 *: Pin 3 must be left unconnected Truth Table LED VI OFF H ON L ©2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.9 VO H L www.fairchildsemi.com FOD0721, FOD0720, FOD0710 — High CMR, 25Mbit/sec Logic Gate Optocoupler December 2010 Pin Number Pin Name 1 VDD1 2 VI Pin Function Description Input Supply Voltage Input Data 3 LED Anode – must be left unconnected 4 GND1 Input Ground 5 GND2 Output Ground 6 VO 7 NC 8 VDD2 Output Data Not Connected Output Supply Voltage Absolute Maximum Ratings (TA = 25°C unless otherwise specified.) Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Value Units TSTG Storage Temperature Parameter -40 to +125 °C TOPR Operating Temperature -40 to +100 °C TSOL Lead Solder Temperature 260 for 10 sec °C Reflow Temperature Profile (Refer to Relow Profile) VDD1 Input Supply Voltage VI Input Voltage II Input DC Current VDD2 0 to 6.0 V -0.5 to VDD1 + 0.5 V -10 to +10 mA 0 to 6.0 V Output Supply Voltage VD Output Voltage -0.5 to VDD2 + 0.5 V IO Average Output Current 10 mA PD1 Input Power Dissipation 90 mW PD2 Output Power Dissipation 70 mW Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol TOPR VDD1, VDD2 Parameter Min. Max. Unit Ambient Operating Temperature -40 +100 °C Supply Voltages 4.5 5.5 V VIH Logic High Input Voltage 2.0 VDD1 V VIL Logic Low Input Voltage 0 0.8 V t r, t f Input Signal Rise and Fall Time 1.0 ms • A 0.1µF bypass capacitor must be connected between pins 1 and 4, and 5 and 8 • Pin 3 must be left unconnected ©2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.9 www.fairchildsemi.com 2 FOD0721, FOD0720, FOD0710 — High CMR, 25Mbit/sec Logic Gate Optocoupler Pin Definitions Symbol Parameter Test Conditions Min. Typ. Max. Unit INPUT CHARACTERISTICS IDD1L Logic Low Input Supply Current VI = 0V 6.5 10.0 mA IDD1H Logic High Input Supply Current VI = VDD1 0.8 3.0 mA IDD1 Input Supply Current 13.0 mA +10 µA II Input Current -10 OUTPUT CHARACTERISTICS IDD2L Logic Low Output Supply Current VI = 0V 5.5 9 mA IDD2H Logic High Output Supply Current VI = VDD1 5.3 9 mA Logic High Output Voltage IO = -20µA, VI = VIH 4.4 5.0 IO = -4mA, VI = VIH 4.0 4.8 VOH VOH VOL Logic Low Output Voltage VOL V V IO = 20µA, VI = VIL 0 0.1 V IO = 4mA, VI = VIL 0.5 1.0 V Isolation Characteristics (TA = -40°C to +100°C unless otherwise specified.) Symbol VISO RISO CISO Characteristics Input-Output Isolation Voltage Isolation Resistance Isolation Capacitance Test Conditions f = 60Hz, t = 1.0 min, II-O VI-O = 500V(1) VI-O = 0 , f = 1.0MHz(1) ≤ 10µA(1)(2) Min. Typ.* Max. Unit 3750 VacRMS 1011 Ω 0.2 pF *All typicals at TA = 25°C Notes: 1. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together. 2. 3,750 VAC RMS for 1 minute duration is equivalent to 4,500 VAC RMS for 1 second duration. ©2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.9 www.fairchildsemi.com 3 FOD0721, FOD0720, FOD0710 — High CMR, 25Mbit/sec Logic Gate Optocoupler Electrical Characteristics (TA = -40°C to 100°C and 4.5V ≤ VDD ≤ 5.5V, all typicals are at TA = 25°C, VDD = 5V) Symbol Parameter Test Conditions Min. Typ. Max. Unit tPHL Propagation Delay Time to Logic Low Output CL = 15pF 21 40 ns tPLH Propagation Delay Time to Logic High Output CL = 15pF 23 40 ns PWD Pulse Width Distortion, | tPHL – tPLH | PW = 80ns, CL = 15pF 2 8 ns FOD0720 PW = 40ns, CL = 15pF 2 8 ns FOD0721 PW = 40ns, CL = 15pF 2 6 ns 12.5 Mb/s 25 Mb/s 20 ns FOD0710 Data Rate FOD0710 FOD0720, FOD0721 tPSK Propagation Delay Skew CL = 15pF(3) tR Output Rise Time (10%–90%) 5 ns tF Output Fall Time (90%–10%) 4.5 ns |CMH| Common Mode Transient Immunity at Output High VI = VDD1, VO > 0.8 VDD2 VCM = 1000V(4) 20 40 kV/µs |CML| Common Mode Transient Immunity at Output Low VI = 0V, VO < 0.8, VCM = 1000V(4) 20 40 kV/µs Notes: 3. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 4. Common mode transient immunity at output high is the maximum tolerable (positive) dVcm/dt on the leading edge of the common mode impulse signal. Vcm, to assure that the output will remain high. Common mode transient immunity at output low is the maximum tolerable (negative dVcm/dt on the trailing edge of the common pulse signal, Vcm, to assure that the output will remain low. ©2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.9 www.fairchildsemi.com 4 FOD0721, FOD0720, FOD0710 — High CMR, 25Mbit/sec Logic Gate Optocoupler Switching Characteristics (TA = -40°C to 100°C and 4.5V ≤ VDD ≤ 5.5V, all typicals are at TA = 25°C, VDD = 5V) Figure 2. Typical Input Voltage Switching Threshold vs. Input Supply Voltage Figure 1. Typical Output Voltage vs. Input Voltage 1.9 VD D2 = 5.0V - Typical Input Voltage Switching Threshold (V) 5 3 O V - Output Voltage (V) 4 2 1.7 1.6 1.5 V ITH 1 1.8 0 0 1 2 3 V I - Input Voltage (V) 4 1.4 4.50 5 4 25 5.50 Frequency = 6.25MHz Duty Cycle = 50% VDD1 = VDD2 = 5.0V 3 PWD - Pulse Width Distortion (ns) 24 23 t PLH 22 PHL 21 P t - Propagation Delay (ns) 5.25 Figure 4. Typical Pulse Width Distortion vs. Ambient Temperature (FOD0710) 26 20 2 1 0 -1 -2 19 18 -40 -20 0 20 40 60 TA - Ambient Temperature (°C) 80 -3 -40 100 0 20 40 60 80 100 Figure 6. Typical Pulse Width Distortion vs. Ambient Temperature (FOD0721/FOD0720) 5 Frequency = 12.5MHz Duty Cycle = 50% V =V = 5.0V DD1 -20 TA - Ambient Temperature (°C) Figure 5. Typical Propogation Delay vs. Ambient Temperature (FOD0721/FOD0720) 28 5.00 VD D1 - Input Supply Voltage (V) Figure 3. Typical Propogation Delay vs. Ambient Temperature (FOD0710) t 4.75 4 DD2 Frequency = 12.5MHz Duty Cycle = 50% VD D1 = VDD 2 = 5.0V PWD - Pulse Width Distortion (ns) t P - Propagation Delay (ns) 26 t PLH 24 22 tPHL 3 2 1 0 -1 20 -2 18 -40 -3 -20 0 20 40 60 80 100 -40 TA - Ambient Temperature (°C) ©2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.9 -20 0 20 40 60 80 100 TA - Ambient Temperature (°C) www.fairchildsemi.com 5 FOD0721, FOD0720, FOD0710 — High CMR, 25Mbit/sec Logic Gate Optocoupler Typical Performance Curves Figure 8. Typical Propogation Delay vs. Output Load Capacitance (FOD0710) Figure 7. Typical Rise and Fall Time vs. Ambient Temperature 6.00 28 Frequency = 6.25MHz Duty Cycle = 50% VDD1 = VDD2 = 5.0V 27 5.50 26 tP - Propagation Delay (ns) tr, tf - Rise, Fall Time Frequency = 6.25MHz Duty Cycle = 50% VDD 1 = VDD2 = 5.0V 5.00 tr 4.50 tf 4.00 25 t PLH 24 tPHL 23 3.50 22 3.00 -40 21 -20 0 20 40 60 TA - Ambient Temperature (°C) 80 100 15 Figure 9. Typical Pulse Width Distortion vs. Output Load Capacitance (FOD0710) 1.6 25 30 35 40 45 CL - Output Load Capacitance (pF) 50 55 Figure 10. Typical Propogation Delay vs. Output Load Capacitance (FOD0721/FOD0720) 27 Frequency = 6.25MHz Duty Cycle = 50% V =V = 5.0V D D1 20 Frequency = 12.5MHz Duty Cycle = 50% V DD1 = VD D2 = 5.0V DD 2 26 t - Propagation Delay (ns) 1.2 1.0 25 tPLH 24 P PWD - Pulse Width Distortion (ns) 1.4 23 tPHL 0.8 22 0.6 21 15 20 25 30 35 40 45 50 55 15 20 25 30 35 40 45 50 55 CL - Output Load Capacitance (pF) CL - Output Load Capacitance (pF) Figure 11. Typical Pulse Width Distortion vs. Output Load Capacitance (FOD0721/FOD0720) Figure 12. Typical Rise and Fall Time vs. Output Load Capacitance (FOD0710) 1.4 12 Frequency = 12.5MHz Duty Cycle = 50% VDD 1 = VDD 2 = 5.0V Frequency = 6.25MHz Duty Cycle = 50% VDD1 = VDD2 = 5.0V 10 tf 1.2 tr, tf - Rise, Fall Time PWD - Pulse Width Distortion (ns) 1.3 1.1 8 tr 6 1.0 4 0.9 0.8 15 20 25 30 35 40 45 50 2 15 55 CL - Output Load Capacitance (pF) ©2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.9 20 25 30 35 40 45 CL - Output Load Capacitance (pF) 50 55 www.fairchildsemi.com 6 FOD0721, FOD0720, FOD0710 — High CMR, 25Mbit/sec Logic Gate Optocoupler Typical Performance Curves (Continued) Figure 13. Typical Rise and Fall Time vs. Output Load Capacitance (FOD0721/FOD0720) Figure 14. Typical Input Supply Current vs. Frequency 12 6.5 Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 5.0V VDD1 = 5.5V 6.0 I DD1 - Input Supply Current (mA) tr, tf - Rise, Fall Time 10 tf 8 tr 6 TA = 100°C 5.5 5.0 TA = 25°C 4.5 TA = -40°C 4.0 4 3.5 2 15 3.0 20 25 30 35 40 45 CL - Output Load Capacitance (pF) 50 0 55 2000 4000 6000 8000 f - Frequency (kHz) 10000 12000 Figure 15. Typical Output Supply Current vs. Frequency 6.0 V DD1 = VD D2 = 5.5V * Pin 6 Floating I DD2 - Output Supply Current (mA) 5.8 T = 25°C A 5.6 TA = -40°C 5.4 T = 100°C A 5.2 5.0 0 ©2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.9 2000 4000 6000 8000 f - Frequency (kHz) 10000 12000 www.fairchildsemi.com 7 FOD0721, FOD0720, FOD0710 — High CMR, 25Mbit/sec Logic Gate Optocoupler Typical Performance Curves (Continued) FOD0721, FOD0720, FOD0710 — High CMR, 25Mbit/sec Logic Gate Optocoupler Ordering Information Option Order Entry Identifier Description No Suffix FOD0721 Shipped in Tubes (50 units per tube) R2 FOD0721R2 Tape and Reel (2500 units per reel) All packages are lead free per JEDEC: J-STD-020B standard. Marking Information 1 721 X YY S1 3 2 5 4 Definitions 1 Fairchild logo 2 Device number 3 One digit year code, e.g., ‘8’ 4 Two digit work week ranging from ‘01’ to ‘53’ 5 Assembly package code ©2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.9 www.fairchildsemi.com 8 8.0 ± 0.10 3.50 ± 0.20 2.0 ± 0.05 Ø1.5 MIN 4.0 ± 0.10 0.30 MAX 1.75 ± 0.10 5.5 ± 0.05 12.0 ± 0.3 8.3 ± 0.10 5.20 ± 0.20 Ø1.5 ± 0.1/-0 6.40 ± 0.20 0.1 MAX User Direction of Feed Note: All dimensions are in millimeters. Reflow Profile 300 260°C 280 260 >245°C = 42 Sec 240 220 200 180 Temperature (°C) 160 Time above 140 183°C = 90 Sec 120 1.822°C/Sec Ramp up rate 100 80 60 40 33 Sec 20 0 0 60 120 180 270 360 Time (s) ©2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.9 www.fairchildsemi.com 9 FOD0721, FOD0720, FOD0710 — High CMR, 25Mbit/sec Logic Gate Optocoupler Carrier Tape Specification 8 2 7 3 6 0.1µF VDD1 = 5V 0.1µF 0V–5V VDD2 = 5V VO Pulse width = 40ns Duty Cycle = 50% CL 4 5 tPLH tPHL 5V Input 50% VIN VOH 90% Output 2.5V VOUT 10% VOL tR tF Figure 16. Test Circuit for Propogation Delay Time and Rise Time, Fall Time 1 8 2 7 3 6 0.1µF SW 0.1µF VDD2 = 5V B A VDD1 = 5V VO CL 4 5 + – VCM 1kV VCM GND VOH Switching Pos. (A) VIN = 5V CMH 0.8 x VDD 0.8V VOL Switching Pos. (B) VIN = 0V CML Figure 17. Test Circuit for Instantaneous Common Mode Rejection Voltage ©2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.9 www.fairchildsemi.com 10 FOD0721, FOD0720, FOD0710 — High CMR, 25Mbit/sec Logic Gate Optocoupler 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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