DATA SHEET
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2.5 A Output Current, IGBT
Drive Optocoupler with
Active Miller Clamp,
Desaturation Detection,
and Isolated Fault Sensing
SOIC16 W
CASE 751EN
MARKING DIAGRAM
FOD8318
ON
Description
The FOD8318 is an advanced 2.5 A output current IGBT drive
optocoupler capable of driving most 1200 V / 150 A IGBTs. It is
ideally suited for fast−switching driving of power IGBTs and
MOSFETs used in motor control inverter applications and
high−performance power systems. It consists of an integrated gate
drive optocoupler featuring low RDS(ON) CMOS transistors to drive
the IGBT from rail to rail and an integrated high−speed isolated
feedback for fault sensing. The FOD8318 has an active Miller clamp
fuction to shut off the IGBT during a high dv/dt situation without the
need of a negative supply voltage. It offers critical protection features
necessary for preventing fault conditions that lead to destructive
thermal runaway of IGBTs.
It utilizes onsemi’s proprietary OPTOPLANAR® coplanar
packaging technology and optimized IC design to achieve high noise
immunity, characterized by high common mode rejection and power
supply rejection specifications.
The device is housed in a compact 16−pin small outline plastic
package that meets the 8 mm creepage and clearance requirements.
• High Noise Immunity Characterized by Common Mode Rejection
35 kV / ms Minimum Common Mode Rejection
(Vcm = 1500 Vpeak)
2.5 A Peak Output Current Driving Capability for Most 1200 V /
150 A IGBT
Optically Isolated Fault Sensing Feedback
Active Miller Clamp to Shut Off the IGBT During High dv/dt
without Needing a Negative Supply Voltage
“Soft” IGBT Turn−off
Built−in IGBT Protection
♦ Desaturation Detection
♦ Under−voltage Lock Out (UVLO) Protection
Wide Supply Voltage Range from 15 V to 30 V
♦ Use of P−Channel MOSFETs at Output Stage Enables Output
Voltage Swing Close to the Supply Rail (Rail−to−rail Output)
3.3 V / 5 V, CMOS/TTL−compatible Inputs
High Speed
♦ 250 ns Max. Propagation Delay over Full Operating
Temperature Range
♦
•
•
•
•
•
•
•
© Semiconductor Components Industries, LLC, 2010
November, 2022 − Rev. 3
D X YY KK
J
8318 = Device Number, e.g., ‘8318’ for FOD8318
V
= DIN EN/IEC60747−5−5 Option (Only Appears
on Component Ordered with this Option)
D
= Plant code, e.g., ‘D’
X
= Last−digit Year Code, e.g., ‘B’ for 2011
YY = Two−digit Work Week Ranging from ‘01’ to ‘53’
KK = Lot Traceability Code
J
= Package Assembly Code, J
ORDERING INFORMATION
See detailed ordering and shipping information on page 27 of
this data sheet.
Features (continued)
Features
•
8318 V
1
• Extended Industrial Temperate Range,
−40°C to 100°C Temperature Range
• Safety and Regulatory Approvals
♦
UL1577, 4,243 VRMS for 1 min.
DIN EN/IEC 60747−5−5,1,414 Vpeak
Working Insulation Voltage, 8000 Vpeak
Transient Isolation Voltage Ratings
RDS(ON) of 1 W (Typ.) Offers Lower Power
Dissipation
User Configurable: Inverting, Non−inverting,
Auto−reset, Auto−shutdown
8 mm Creepage and Clearance Distances
♦
•
•
•
Applications
• Industrial Inverter
• Induction Heating
• Isolated IGBT Drive
Publication Order Number:
FOD8318/D
FOD8318
TRUTH TABLE
VIN+
VIN–
UVLO (VDD2 – VE)
DESAT Detected?
FAULT
VOUT*
X
X
Active
X
X
LOW
X
X
X
Yes
LOW
LOW
LOW
X
X
X
X
LOW
X
HIGH
X
X
X
LOW
HIGH
LOW
Not Active
No
HIGH
HIGH
*VOUT is always LOW with ‘clamp’ being active (gate voltage < 2 V above VSS).
PIN DEFINITIONS
Pin No.
Name
Description
1
VIN+
Non−inverting gate drive control input
2
VIN–
Inverting gate drive control input
3
VDD1
Positive input supply voltage (3 V to 5.5 V)
4
GND1
Input ground
5
RESET
Fault reset input
6
FAULT
Fault output
7
VLED1+
LED 1 anode (must be left unconnected)
8
VLED1−
LED 1 cathode (must be connected to ground)
9
VSS
10
VCLAMP
Output supply voltage (negative)
11
VO
Gate drive output voltage
12
VS
Source of pull−up PMOS transistor
13
VDD2
14
DESAT
Desaturation voltage input
15
VLED2+
LED 2 anode (must be left unconnected)
16
VE
Active Miller clamp supply voltage
Positive output supply voltage
Output supply voltage / IGBT emitter
VIN+
1
16 VE
VIN–
2
15 VLED2+
VDD1
3
14 DESAT
GND
4
13 VDD2
RESET
5
12 VS
FAULT
6
11 VO
VLED1+
7
10 VSS
VLED1− *
8
9
Figure 1.
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2
VSS
FOD8318
BLOCK DIAGRAM
VLED1+
7
Output IC
VDD1
3
VIN+
VIN–
1
2
6
FAULT
13
Input IC
12
11
UVLO
GND1
VLED1–
Driver
LED1
Gate Drive
Optocoupler
VS
VO
4
8
Shield
DESAT
9
RESET
VDD2
5
Fault
14
16
LED2
10
Miller
Clamp
Fault Sense
Optocoupler
VSS
Shield
15
VLED2+
Figure 2. Block Diagram
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3
VSS
DESAT
VE
VCLAMP
FOD8318
SAFETY AND INSULATION RATINGS (As per DIN EN/IEC 60747−5−5. This optocoupler is suitable for “safe electrical insulation”
only within the safety limit data. Compliance with the safety ratings shall be ensured by means of protective circuits.)
Parameter
Min.
Typ.
Max.
Installation Classifications per DIN VDE 0110/1.89 Table 1
For Rated Mains Voltage < 150 Vrms
−
I–IV
−
For Rated Mains Voltage < 300 Vrms
−
I–IV
−
For Rated Mains Voltage < 450 Vrms
−
I–IV
−
For Rated Mains Voltage < 600 Vrms
−
I–IV
−
For Rated Mains Voltage < 1000 Vrms
−
I–III
−
Climatic Classification
−
40/100/21
−
Pollution Degree (DIN VDE 0110/1.89)
−
2
−
175
−
−
Symbol
Unit
CTI
Comparative Tracking Index
VPR
Input to Output Test Voltage, Method b,
VIORM x 1.875 = VPR, 100 % Production Test with tm = 1 s,
Partial Discharge < 5 pC
2,651
−
−
Vpeak
Input to Output Test Voltage, Method a,
VIORM x 1.5 = VPR, Type and Sample Test with tm = 60 s,
Partial Discharge < 5 pC
2,121
−
−
Vpeak
VIORM
Maximum Working Insulation Voltage
1,414
−
−
Vpeak
VIOTM
Highest Allowable Over Voltage
8,000
−
−
Vpeak
External Creepage
8
−
−
mm
External Clearance
8
−
−
mm
Insulation Thickness
0.5
−
−
mm
Safety Limit Values – Maximum Values Allowed in the Event of a Failure Case
Temperature
150
−
−
°C
Input Power
100
−
−
mW
Output Power
600
−
−
mW
Insulation Resistance at TS, VIO = 500 V
109
−
−
W
TCase
PS,INPUT
PS,OUTPUT
RIO
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FOD8318
ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Symbol
Value
Unit
TSTG
Storage Temperature
−40 to +125
°C
TOPR
Operating Temperature
−40 to +100
°C
Junction Temperature
−40 to +125
°C
TSOL
Lead Wave Solder Temperature (No Solder Immersion)
Refer to page 26 for reflow temperature profile.
260 for 10 s
°C
IFAULT
Fault Output Current
15
mA
IO(PEAK)
Peak Output Current (Note 1)
3
A
VE – VSS
Negative Output Supply Voltage (Note 2)
0 to 15
V
VDD2 – VE
Positive Output Supply Voltage
TJ
VO(peak)
VDD2 – VSS
VDD1
VIN+, VIN− and VRESET
VFAULT
VS
Parameter
−0.5 to 35 – (VE – VSS)
V
Gate Drive Output Voltage
−0.5 to 35
V
Output Supply Voltage
−0.5 to 35
V
Positive Input Supply Voltage
−0.5 to 6
V
Input Voltages
−0.5 to VDD1
V
Fault Pin Voltage
−0.5 to VDD1
V
VSS + 6.5 to VDD2
V
VE to VE +25
V
1.7
A
−0.5 to VDD2
V
Source of Pull−up PMOS Transistor Voltage
VDESAT
DESAT Voltage
ICLAMP
Peaking Clamping Sinking Current
VCLAMP
Miller Clamping Voltage
PDI
Input Power Dissipation (Note 3, 5)
100
mW
PDO
Output Power Dissipation (Note 4, 5)
600
mW
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum pulse width = 10 ms, maximum duty cycle = 0.2 %.
2. This negative output supply voltage is optional. It’s only needed when negative gate drive is implemented. A schottky diode is recommended
to be connected between VE and VSS to protect against a reverse voltage greater than 0.5 V. Refer to application information, “Active Miller
Clamp Function” on page 24.
3. No derating required across temperature range.
4. Derate linearly above 64°C, free air temperature at a rate of 10.2 mW/°C.
5. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected to conditions outside
these ratings.
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Max
Unit
−40
+100
°C
Input Supply Voltage (Note 6)
3
5.5
V
Total Output Supply Voltage
15
30
V
VE – VSS
Negative Output Supply Voltage
0
15
V
VDD2 – VE
Positive Output Supply Voltage (Note 6)
15
30 – (VE – VSS)
V
VSS + 7.5
VDD2
V
TA
VDD1
VDD2 – VSS
VS
Parameter
Ambient Operating Temperature
Source of Pull−up PMOS Transistor Voltage
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. During power up or down, it is important to ensure that VIN+ remains LOW until both the input and output supply voltages reach the proper
recommended operating voltage to avoid any momentary instability at the output state. Refer to “Time to Good Power” section on page 24.
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FOD8318
ISOLATION CHARACTERISTICS (Apply over all recommended conditions, typical value is measured at TA = 25°C)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
4,243
−
−
VRMS
VI−O = 500 V (Note 7)
−
1011
−
W
VI−O = 0 V, freq = 1.0 MHz (Note 7)
−
1
−
pF
VISO
Input−Output Isolation Voltage
TA = 25°C, R.H.< 50 %, t = 1.0 min, II−O < 10 mA,
50 Hz (Note 7, 8, 9)
RISO
Isolation Resistance
CISO
Isolation Capacitance
7. Device is considered a two terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together.
8. 4,243 VRMS for 1−minute duration is equivalent to 5,091 VRMS for 1−second duration.
9. The Input−Output Isolation Voltage is a dielectric voltage rating as per UL1577. It should not be regarded as an input−output continuous
voltage rating. For the continuous working voltage rating, refer to the equipment level safety specification or DIN EN/IEC 60747−5−5 Safety
and Insulation Ratings Table on page 4.
ELECTRICAL CHARACTERISTICS (Apply over all recommended conditions, typical value is measured at VDD1 = 5 V,
VDD2 – VSS = 30 V, VE – VSS = 0 V, TA = 25°C unless otherwise specified.)
Symbol
Parameter
VIN+L,
VIN−L,
VRESETL
VIN+H,
VIN−H,
VRESETH
Min
Typ
Max
Unit
Logic Low Input Voltages
−
−
0.8
V
Logic High Input Voltages
2.0
−
−
V
VIN = 0.4 V
−0.5
−0.001
−
mA
IIN+L, IIN−L, Logic Low Input Currents
IRESETL
Conditions
Figure
I
FAULTL
FAULT Logic Low Output Current
VFAULT = 0.4 V
5.0
12.0
−
mA
IFAULTH
FAULT Logic High Output Current
VFAULT = VDD1
−40
0.002
−
mA
37
High Level Output Current
VO = VDD2 – 3 V
−1
−2.5
−
A
4, 9, 38
−2.5
−
−
A
1
3
−
A
VO = VSS + 6 V (Note 11)
2.5
−
−
A
70
125
170
mA
6, 43
−
V
7, 9, 40
IOH
VO = VDD2 – 6 V (Note 10)
IOL
Low Level Output Current
VO = VSS + 3 V
3, 37
5, 39
IOLF
Low Level Output Current During
Fault Condition
VO – VSS = 14 V
VOH
High Level Output Voltage
IO = –100 mA (Note 12, 13, 14) VS – 1.0 V VS – 0.5 V
VOL
Low Level Output Voltage
IO = 100 mA
−
0.1
0.5
V
8, 10,
40
IDD1H
High Level Supply Current
VIN+ = VDD1 = 5.5 V, VIN– = 0 V
−
14
17
mA
11, 41
IDD1L
Low Level Supply Current
VIN+ = VIN− = 0 V, VDD1 = 5.5 V
−
2
3
mA
IDD2H
High Level Output Supply Current
VO = Open (Note 14)
−
1.7
3
mA
IDD2L
12, 13,
42
Low Level Output Supply Current
VO = Open
−
1.8
2.8
mA
ISH
High Level Source Current
IO = 0 mA
−
0.65
1.5
mA
42
ISL
Low Level Source Current
IO = 0 mA
−
0.6
1.4
mA
42
IEL
VE Low Level Supply Current
−0.8
−0.5
−
mA
15, 42
IEH
VE High Level Supply Current
−0.5
−0.25
−
mA
−0.13
−0.25
−0.33
mA
ICHG
Blanking Capacitor Charge Current
VDESAT = 2 V (Note 14, 15)
IDSCHG
Blanking Capacitor Discharge Current
VDESAT = 7 V
10
36
−
mA
43
VUVLO+
Under−Voltage Lockout Threshold
(Note 14)
VO > 5 V at 25°C
10.8
11.7
12.7
V
VO < 5 V at 25°C
9.8
10.7
11.7
V
17, 31,
44
Under−Voltage Lockout Threshold
Hysteresis
At 25°C
0.4
1.0
−
V
DESAT Threshold (Note 14)
VDD2 – VE > VUVLO−, VO < 5 V
6.0
6.5
7.2
V
VUVLO−
UVLOHYS
VDESAT
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14, 43
18, 43
FOD8318
ELECTRICAL CHARACTERISTICS (Apply over all recommended conditions, typical value is measured at VDD1 = 5 V,
VDD2 – VSS = 30 V, VE – VSS = 0 V, TA = 25°C unless otherwise specified.) (continued)
Symbol
VCLAMP_
Parameter
Conditions
Clamping Threshold Voltage
Min
Typ
Max
Unit
Figure
−
2.2
−
V
35, 54
0.35
1.2
−
A
34, 53
THRES
ICLAMPL
Clamp Low Level Sinking Current
VO = VSS + 2.5 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10. Maximum pulse width = 10 ms, maximum duty cycle = 0.2 %.
11. Maximum pulse width = 4.99 ms, maximum duty cycle = 99.8 %.
12. VOH is measured with the DC load current in this testing (maximum pulse width = 1 ms, maximum duty cycle = 20 %). When driving capacitive
loads, VOH approaches VDD as IOH approaches zero units.
13. Positive output supply voltage (VDD2 – VE) should be at least 15 V. This ensures adequate margin in excess of the maximum under−voltage
lockout threshold VUVLO+ of 13.5 V.
14. When VDD2 – VE > VUVLO and output state VO of the FOD8318 is allowed to go HIGH, the DESAT detection feature is active and provides
the primary source of IGBT protection. UVLO is needed to ensure DESAT detection is functional.
15. The blanking time, tBLANK, is adjustable by an external capacitor (CBLANK) where tBLANK = CBLANK x (VDESAT / ICHG).
SWITCHING CHARACTERISTICS (Apply over all recommended conditions, typical value is measured at VDD1 = 5 V,
VDD2 – VSS = 30 V, VE – VSS = 0 V, TA = 25°C unless otherwise specified.)
Symbol
Parameter
tPHL
Propagation Delay Time to Logic Low
Output (Note 17)
tPLH
Propagation Delay Time to Logic High
Output (Note 18)
PWD
PDD Skew
Conditions
Min
Typ
Max
Unit
Figure
−
140
250
ns
−
160
250
ns
19, 20,
21, 22,
23, 24,
45, 53
Pulse Width Distortion, | tPHL – tPLH |
(Note 19)
−
20
100
ns
Propagation Delay Difference
between Any Two Parts or Channels,
(tPHL – tPLH) (Note 20)
–150
−
150
ns
Rg = 10 W Cg = 10 nF,
f = 10 kHz,
Duty Cycle = 50 % (Note 16)
45, 55
tR
Output Rise Time (10 % – 90 %)
−
25
−
ns
tF
Output Fall Time (90 % – 10 %)
−
25
−
ns
tDESAT(90 %)
DESAT Sense to 90 % VO Delay
(Note 21)
−
450
700
ns
25, 46
tDESAT(10 %)
DESAT Sense to 10 % VO Delay
(Note 21)
−
2.7
4.0
ms
26, 28,
29, 46
tDESAT(FAULT)
DESAT Sense to Low Level FAULT
Signal Delay (Note 22)
−
1.4
5.0
ms
27, 46,
56
tDESAT(LOW)
DESAT Sense to DESAT Low
Propagation Delay (Note 23)
−
250
−
ns
46
tRESET(FAULT)
RESET to High Level FAULT Signal
Delay (Note 24)
3
6
20
ms
30, 47,
56
tDESAT(MUTE)
DESAT Input Mute
10
22
35
ms
PWRESET
RESET Signal Pulse Width
1.2
−
−
ms
tUVLO ON
UVLO Turn On Delay (Note 25)
−
4
−
ms
tUVLO OFF
UVLO Turn Off Delay (Note 26)
−
3
−
ms
tGP
Time to Good Power (Note 27)
VDD2 = 0 to 30 V in 10 ms Ramp
−
2.5
−
ms
32, 33,
48
| CMH |
Common Mode Transient Immunity at
Output High
TA = 25°C, VDD1 = 5 V,
VDD2 = 25 V, VSS = Ground,
VCM = 1500 Vpeak (Note 28)
35
50
−
kV/ms
50, 51
| CML |
Common Mode Transient Immunity at
Output Low
TA = 25°C, VDD1 = 5 V,
VDD2 = 25 V, VSS = Ground,
VCM = 1500 Vpeak (Note 29)
35
50
−
kV/ms
49, 52
Rg = 10 W, Cg = 10 nF,
VDD2 – VSS = 30 V
VDD2 = 20 V in 1.0 ms Ramp
16. This load condition approximates the gate load of a 1200 V / 150 A IGBT.
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31, 48
FOD8318
17. tPHL propagation delay is measured from the 50 % level on the falling edge of the input pulse (VIN+, VIN−) to the 50 % level of the falling edge
of the VO signal. Refer to Figure 55.
18. tPHL propagation delay is measured from the 50 % level on the rising edge of the input pulse (VIN+, VIN−) to the 50 % level of the rising edge
of the VO signal. Refer to Figure 55.
19. PWD is defined as | tPHL – tPLH | for any given device.
20. The difference between tPHL and tPLH between any two FOD8318 parts under same operating conditions, with equal loads.
21. This is the amount of time the DESAT threshold must be exceeded before VO begins to go LOW. This is supply voltage dependent. Refer
to Figure 56.
22. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes LOW. Refer to Figure 56.
23. This is the amount of time the DESAT threshold must be exceeded before VO begins to go LOW and the FAULT output to go LOW. Refer
to Figure 56.
24. This is the amount of time from when RESET is asserted LOW, until FAULT output goes HIGH. Refer to Figure 56.
25. tUVLO ON UVLO turn−on delay is measured from VUVLO+ threshold voltage of the output supply voltage (VDD2) to the 5 V level of the rising
edge of the VO signal.
26. tUVLO OFF UVLO turn−off delay is measured from VUVLO– threshold voltage of the output supply voltage (VDD2) to the 5 V level of the falling
edge of the VO signal.
27. tGP time to good power is measured from 13.5 V level of the rising edge of the output supply voltage (VDD2) to the 5 V level of the rising edge
of the VO signal.
28. Common mode transient immunity at output HIGH state is the maximum tolerable negative dVcm / dt on the trailing edge of the common mode
pulse, VCM, to assure that the output remains in HIGH state (i.e., VO > 15 V or FAULT > 2 V).
29. Common mode transient immunity at output LOW state is the maximum positive tolerable dVcm / dt on the leading edge of the common mode
pulse, VCM, to assure that the output remains in a LOW state (i.e., VO < 1.0 V or FAULT < 0.8 V).
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FOD8318
IOH, HIGH LEVEL OUTPUT CURRENT (A)
TYPICAL PERFORMANCE CHARACTERISTICS
IFAULT, FAULT CURRENT (mA)
50
40
30
20
VDD1 = 5 V
VIN+ = 5 V
ILED2+ = 10 mA
TA = 25°C
10
0
0
1
2
3
4
VFAULTL, FAULT VOLTAGE (V)
5
7
6
VO = VSS + 6 V
5
4
VO = VSS + 3 V
3
2
1
0
−40
VDD2 − VSS = 30 V
VDD1 = 5 V
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
100
0.1
IO = −650 mA
IO = −100 mA
−0.1
−0.2
−0.3
−0.4
−0.5
−40
VDD2 − VSS = 30 V
VDD1 = 5 V
VIN+ = 5 V
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
5
VO = VDD2 − 6 V
4
3
VO = VDD2 − 3 V
2
1
0
−40
VDD2 − VSS = 30 V
VDD1 = 5 V
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
100
150
TA = −40 °C
125
TA = 25 °C
TA = 100 °C
100
75
VDD2 − VSS = 30 V
VDD1 = 5 V
50
0
5
10
15
20
25
VO, OUTPUT VOLTAGE (V)
30
Figure 6. Low Level Output Current During Fault
Condition (IOLF) vs. Output Voltage (VOL)
VOL, LOW LEVEL OUTPUT VOLTAGE (V)
VOH − VDD2, LOW LEVEL OUTPUT
VOLTAGE DROP (V)
Figure 5. Low Level Output Current (IOL) vs.
Temperature
0.0
6
Figure 4. High Level Output Current (IOH) vs.
Temperature
IOLF, LOW LEVEL OUTPUT CURRENT
DURING FAULT CONDITION (mA)
IOL, LOW LEVEL OUTPUT CURRENT (A)
Figure 3. FAULT Logic Low Output Current (IFAULTL)
vs. FAULT Logic Low Output Voltage (VFAULTL)
7
100
0.25
0.20
0.15
IO = 100 mA
0.10
0.05
0.00
−40
VDD2 − VSS = 30 V
VDD1 = 5 V
VIN+ = 0 V
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
100
Figure 8. Low Level Output Voltage (VOL) vs.
Temperature
Figure 7. High Level Output Voltage Drop
(VOH − VDD) vs. Temperature
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FOD8318
VOL, LOW LEVEL OUTPUT VOLTAGE (V)
VOH, HIGH LEVEL OUTPUT VOLTAGE (V)
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
30
29
TA = −40 °C
25 °C
28
100 °C
27
26
25
0.0
VDD2 − VSS = 30 V
VDD1 = 5 V
VIN+ = 5 V
2.0
0.5
1.0
1.5
2.5
IOH, HIGH LEVEL OUTPUT CURRENT (A)
IDD1, SUPPLY CURRENT (mA)
20
VDD1 = 5 V
VIN+ = 0 V (IDD1L) / 5 V (IDD1H)
15
IDD1H
10
5
IDD1L
0
−40
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
100
Figure 11. Supply Current (IDD1) vs. Temperature
3
TA = 100 °C
25 °C
2
−40 °C
1
0
0.0
0.5
1.0
1.5
2.0
2.5
IOL, LOW LEVEL OUTPUT CURRENT (A)
2.2
2.0
VDD2 − VSS = 30 V
VDD1 = 5 V
VIN+ = 0 V (IDD2L) / 5 V (IDD2H)
1.8
IDD2L
IDD2H
1.6
1.4
1.2
1.0
−40
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
100
Figure 12. Output Supply Current (IDD2) vs.
Temperature
2.2
−0.15
VDD1 = 5 V
VIN+ = 0 V (IDD2L) / 5 V (IDD2H)
2.0
ICHG, BLANKING CAPACITOR
CHARGING CURRENT (mA)
IDD2, OUTPUT SUPPLY CURRENT (mA)
VDD2 − VSS = 30 V
VDD1 = 5 V
VIN+ = 0 V
Figure 10. Low Level Output Voltage (VOL) vs.
Low Level Output Current (IOL)
IDD2, OUTPUT SUPPLY CURRENT (mA)
Figure 9. High Level Output Voltage (VOH) vs.
High Level Output Current (IOH)
4
IDD2L
1.8
IDD2H
1.6
1.4
1.2
1.0
15
20
25
VDD2, OUTPUT SUPPLY VOLTAGE (V)
−0.20
−0.25
−0.30
−40
30
VDD2 − VSS = 30 V
VDD1 = 5 V
VIN+ = 5 V
VDESAT = 0 to 6 V
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
100
Figure 14. Blanking Capacitor Charge Current
(ICHG) vs. Temperature
Figure 13. Output Supply Current (IDD2) vs.
Output Supply Voltage (VDD2)
www.onsemi.com
10
FOD8318
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
−0.2
3.0
VDD2 − VSS = 30 V
VDD1 = 5 V
VIN+ = 0 V (IEL) / 5 V (IEH)
IS, SOURCE CURRENT (mA)
IE, SUPPLY CURRENT (mA)
0.0
IEH
−0.4
IEL
−0.6
−0.8
−40
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
1.5
1.0
0.5
0.5
1.0
1.5
IO, OUTPUT CURRENT (mA)
2.0
7.0
VDESAT, DESAT THRESHOLD (V)
VUVLO, UNDER VOLTAGE LOCKOUT
THRESHOLD (V)
VDD2 − VSS = 30 V
VDD1 = 5 V
VIN+ = 5 V
Figure 16. Source Current (IS) vs.
Output Current (IO)
VUVLO+
10
VUVLO−
5
VDD1 = 5 V
VIN+ = 5 V
0
−40
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
100
6.8
6.6
6.4
6.2
6.0
−40
VDD2 − VSS = 30 V
VDD1 = 5 V
VIN+ = 5 V
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
100
Figure 18. DESAT Threshold (VDESAT) vs.
Temperature
Figure 17. Under Voltage Lockout Threshold
(VUVLO) vs. Temperature
0.25
0.25
tP, PROPAGATION DELAY (ms)
tP, PROPAGATION DELAY (ms)
100°C
0.0
0.0
100
15
0.20
tPLH
0.15
tPHL
0.05
−40
25°C
2.0
Figure 15. Supply Current (IE) vs. Temperature
0.10
−40°C
2.5
VDD2 − VSS = 30 V
VDD1 = 5 V
f = 10 kHz 50% Duty Cycle
RL = 10 W CL = 10 nF
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
0.20
tPLH
0.15
tPHL
0.10
0.05
15
100
Figure 19. Propagation Delay (tP) vs. Temperature
VDD1 = 5 V
f = 10 kHz 50% Duty Cycle
RL = 10 W CL = 10 nF
20
25
VDD2, SUPPLY VOLTAGE (V)
Figure 20. Propagation Delay (tP) vs.
Supply Voltage (VDD2)
www.onsemi.com
11
30
FOD8318
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
0.18
VDD2 − VSS = 30 V
f = 10 kHz 50% Duty Cycle
RL = 10 W CL = 10 nF
0.18
tPHL, PROPAGATION DELAY (ms)
tPLH, PROPAGATION DELAY (ms)
0.20
0.16
0.14
0.12
−40
VDD1 = 4.5 V
VDD1 = 5.0 V
VDD1 = 5.5 V
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
100
Figure 21. Propagation Delay Time to Logic High
Output (tPLH) vs. Temperature
0.14
0.12
0.10
−40
VDD1 = 4.5 V
VDD1 = 5.0 V
VDD1 = 5.5 V
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
100
0.20
tP, PROPAGATION DELAY (ms)
tP, PROPAGATION DELAY (ms)
0.16
Figure 22. Propagation Delay Time to Logic Low
Output (tPHL) vs. Temperature
0.20
0.18
tPLH
0.16
tPHL
0.14
VDD2 − VSS = 30 V
VDD1 = 5 V
f = 10 kHz 50% Duty Cycle
RL = 10 W
0.12
0.10
0
0.18
0.16
0.12
100
0
tPHL
50
10
20
30
40
RL, LOAD RESISTANCE (W)
Figure 24. Propagation Delay (tP) vs.
Load Resistance (RL)
4.0
tDESAT(10%), DESAT SENSE TO
10% VO DELAY (ms)
VDD2 − VSS = 30 V
VDD1 = 5 V
VIN+ = 5 V
RL = 10 W CL = 10 nF
0.4
0.2
0.0
−40
VDD2 − VSS = 30 V
VDD1 = 5 V
f = 10 kHz 50% Duty Cycle
CL = 10 nF
0.10
20
40
60
80
CL, LOAD CAPACITANCE (nF)
0.8
0.6
tPLH
0.14
Figure 23. Propagation Delay (tP) vs.
Load Capacitance (CL)
tDESAT(90%), DESAT SENSE TO
90% VO DELAY (ms)
VDD2 − VSS = 30 V
f = 10 kHz 50% Duty Cycle
RL = 10 W CL = 10 nF
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
3.5
VDD2 − VSS = 30 V
3.0
2.5
2.0
VDD2 − VSS = 15 V
1.5
1.0
−40
100
VDD1 = 5 V
VIN+ = 5 V
RL = 10 W CL = 10 nF
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
Figure 26. DESAT Sense to 10% VO Delay
(tDESAT(10%)) vs. Temperature
Figure 25. DESAT Sense to 90% VO Delay
(tDESAT(90%)) vs. Temperature
www.onsemi.com
12
100
FOD8318
1.8
10
VDD2 − VSS = 30 V
VDD1 = 5 V
VIN+ = 5 V
RL = 10 W CL = 10 nF
1.6
tDESAT(10%), DESAT SENSE
TO 10% VO DELAY (ms)
tDESAT(FAULT), DESAT SENSE TO LOW
LEVEL FAULT SIGNAL DELAY (ms)
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
1.4
VE − VSS = 0 V
1.2
VE − VSS = 15 V
1.0
0.8
−40
0
20
40
60
TA, TEMPERATURE (°C)
80
VDD2 − VSS = 30 V
VDD2 − VSS = 15 V
1.5
1.0
0.5
0.0
10
20
30
40
RL, LOAD RESISTANCE (W)
50
Figure 29. DESAT Sense to 10% VO Delay
(tDESAT(10%)) vs. Load Resistance (RL)
5.0
VDD2 − VSS = 20 V
VDD1 = 5 V
VIN+ = 5 V
f = 50 Hz 50% Duty Cycle
tUVLO ON
3.5
tUVLO OFF
3.0
2.5
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
25
5
10
15
20
CL, LOAD CAPACITANCE (nF)
30
9
VDD2 − VSS = 30 V
VIN+ = VDD1
RL = 10 W CL = 10 nF
8
7
VDD1 = 4.5 V
6
5
VDD1 = 5.5 V
VDD1 = 5.0 V
4
3
−40
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
100
Figure 30. RESET to High Level FAULT Signal Delay
(tRESET(FAULT)) vs. Temperature
tGP, TIME TO GOOD POWER (ms)
tUVLO, UNDER VOLTAGE LOCKOUT
THRESHOLD DELAY (ms)
VDD2 − VSS = 15 V
Figure 28. DESAT Sense to 10% VO Delay
(tDESAT(10%)) vs. Load Capacitance (CL)
2.0
2.0
−40
2
0
2.5
4.0
VDD2 − VSS = 30 V
4
tRESET(FAULT), RESET TO HIGH LEVEL
FAULT SIGNAL DELAY (ms)
tDESAT(10%), DESAT SENSE
TO 10% VO DELAY (ms)
VDD1 = 5 V
VIN+ = 5 V
CL = 10 nF
4.5
6
100
4.0
3.0
8
0
−20
Figure 27. DESAT Sense to Low Level FAULT
Signal Delay (tDESAT(FAULT)) vs. Temperature
3.5
VDD1 = 5 V
VIN+ = 5 V
RL = 10 W
100
5
VDD1 = 5 V
VIN+ = 5 V
f = 50 Hz 50% Duty Cycle
4
3
2
1
0
15
20
25
VDD2, SUPPLY VOLTAGE (V)
Figure 32. Time to Good Power (tGP) vs.
Supply Voltage (VDD2)
Figure 31. Under Voltage Lockout Threshold Delay
(tUVLO) vs. Temperature
www.onsemi.com
13
30
FOD8318
5
4
3.0
VDD2 − VSS = 30 V
VDD1 = 5 V
VIN+ = 5 V
f = 50 Hz 50% Duty Cycle
ICLAMP, CLAMP LOW LEVEL
SINKING CURRENT (A)
tGP, TIME TO GOOD POWER (ms)
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
3
2
1
0
−40
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
2.0
1.8
1.6
0
20
40
60
TA, TEMPERATURE (°C)
0.5
3.0
VDD2 – VSS = 30 V
VDD1 = 5 V
VIN+ = 0 V
−20
1.0
80
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
100
Figure 34. Clamp Low Level Sinking Current
(ICLAMPL) vs. Temperature
2.2
1.4
−40
1.5
0
−40
ICLAMP, CLAMP LOW LEVEL
SINKING CURRENT (A)
VCLAMP, CLAMP PIN THRESHOLD
VOLTAGE (V)
2.4
2.0
100
Figure 33. Time to Good Power (tGP) vs.
Temperature
2.6
VDD2 – VSS = 30 V
VDD1 = 5 V
VIN+ = 5 V
VCLAMP = 2.5 V
2.5
2.5
2.0
1.5
1.0
0.5
0
100
Figure 35. Clamping Threshold Voltage (VCLAMP)
vs. Temperature
VDD2 – VSS = 30 V
VDD1 = 5 V
VIN+ = 0 V
0
0.5
1.0
1.5
2.0
2.5
VCLAMP, CLAMP VOLTAGE (V)
Figure 36. Clamp Low Level Sinking Current
(ICLAMPL) vs. Clamp Voltage (VCLAMP)
www.onsemi.com
14
3.0
FOD8318
TEST CIRCUITS
FOD8318
+
5V –
1
VIN+
VE
2
VIN–
VLED2+ 15
3
VDD1
4
GND1
5
0.1 mF
16
DESAT
14
VDD2
13
RESET
VS
12
6
FAULT
VO
11
IFAULT
7
VLED1+
VCLAMP
10
VFAULT = 0.4 V for IFAULTL
VFAULT = 5.0 V for IFAULTH
8
VLED1−*
VSS
9
VFAULT
–
+
A
0.1 mF
10 mA
Switch A closed for IFAULTL
Switch A opened for IFAULTH
Figure 37. Fault Output Current (IFAULTL) and (IFAULTH) Test Circuit
FOD8318
Pulse Gen
PW = 10 ms
Period = 5 ms
+
–
0.1 mF
–
5V +
1
VIN+
VE
2
VIN–
VLED2+ 15
3
VDD1
4
GND1
5
16
DESAT
14
VDD2
13
RESET
VS
12
6
FAULT
VO
11
7
VLED1+
VCLAMP
10
8
VLED1−*
VSS
9
+
–
0.1 mF
0.1 mF 47 mF
VE
0.1 mF 47 mF
+ VO
–
+
– 30 V
3 kW
Figure 38. High Level Output Current (IOH) Test Circuit
FOD8318
Pulse Gen
PW = 4.99 ms
Period = 5 ms
+
–
0.1 mF
–
5V +
1
VIN+
VE
2
VIN–
VLED2+ 15
3
VDD1
4
GND1
5
16
DESAT
14
VDD2
13
RESET
VS
12
6
FAULT
VO
11
7
VLED1+
VCLAMP
10
8
VLED1−*
VSS
9
0.1 mF
0.1 mF 47 mF
3 kW
Figure 39. Low Level Output Current (IOL) Test Circuit
www.onsemi.com
15
+
– VE
+
– 30 V
+
–
VO
0.1 mF 47 mF
FOD8318
TEST CIRCUITS (Continued)
A
FOD8318
B
0.1 mF
+
–
5V
1
V IN+
VE
16
2
V IN–
V LED2+
15
3
V DD1
DESAT
14
4
GND1
V DD2
13
5
RESET
VS
12
6
FAULT
VO
11
7
V LED1+
V CLAMP
10
8
V LED1−*
V SS
9
0.1 mF
+
–
100 mA
pulsed
VO
B
A
3 kW
Switch A for VOH test
Switch B for VOL test
VE
0.1 mF
30 V +
–
100 mA
pulsed
Figure 40. High Level (VOH) and Low Level (VOL) Output Voltage Test Circuit
A
FOD8318
B
0.1 mF
5V
+
–
1
V IN+
VE
16
2
V IN–
V LED2+
15
3
V DD1
DESAT
14
4
GND1
V DD2
13
5
RESET
VS
12
6
FAULT
VO
11
7
V LED1+
V CLAMP
10
8
V LED1−*
V SS
9
IDD1
Switch A for IDD1H test
Switch B for IDD1L test
Figure 41. High Level (IDD1H) and Low Level (IDD1L) Supply Current Test Circuit
A
B
0.1 mF
5V
+
–
IE
FOD8318
1
V IN+
VE
16
2
V IN–
V LED2+
15
3
V DD1
DESAT
14
4
GND1
V DD2
13
5
RESET
VS
12
6
FAULT
VO
11
7
V LED1+
V CLAMP
10
V SS
9
8
Switch A for IDD2H, ISH and IEH test
Switch B for IDD2L, ISL and IEL test
V LED1−*
0.1 mF
16
+
–
IDD2
IS
VO
0.1 mF
Figure 42. High Level (IDD2H), Low Level (IDD2L) Output Supply Current,
High Level (ISH), Low Level (ISL) Source Current,
VE High Level (IEH), and VE Low Level (IEL) Supply Current Test Circuit
www.onsemi.com
VE
30 V
+
–
FOD8318
TEST CIRCUITS (Continued)
FOD8318
1
V IN+
VE
2
V IN–
V LED2+ 15
16
0.1 mF
+
5V –
3
V DD1
4
GND1
5
RESET
DESAT
14
V DD2
13
VS
12
6
FAULT
VO
7
V LED1+
V CLAMP 10
8
V LED1−*
11
3 kW
V SS
ICHG/DSCHG
+
–
V DESAT
0.1 mF
+
–
VE
V RL
VO
+
30 V –
RL
0.1 mF
IOLF
10 nF
9
Figure 43. Low Level Output Current During Fault Conditions (IOLF), Blanking Capacitor Charge Current (ICHG),
Blanking Capacitor Discharging Current (IDSCHG), and DESAT Threshold (VDESAT) Test Circuit
FOD8318
0.1 mF
+
5V –
1
V IN+
VE
2
V IN–
V LED2+ 15
3
V DD1
4
GND1
5
16
DESAT
14
V DD2
13
RESET
VS
12
6
FAULT
VO
11
7
V LED1+
V CLAMP 10
8
V LED1−*
V SS
VO
0.1 mF
DC Sweep
+
0 to 15 V
–
(100 steps)
Parameter
Analyzer
9
Figure 44. Under−Voltage Lockout Threshold (VUVLO) Test Circuit
F = 10 kHz
DC = 50 %
+
–
0.1 mF
+
5V –
FOD8318
1
V IN+
VE
2
V IN–
V LED2+ 15
3
V DD1
4
GND1
5
16
DESAT
14
V DD2
13
RESET
VS
12
6
FAULT
VO
11
7
V LED1+
V CLAMP 10
8
V LED1−*
0.1 mF
VE
V CL
VO
0.1 mF
+
30 V –
RL
3 kW
10 nF
V SS
9
Figure 45. Propagation Delay (tPLH, tPHL), Pulse Width Distortion (PWD),
Rise Time (tR), and Fall Time (tF) Test Circuit
www.onsemi.com
17
+
–
FOD8318
TEST CIRCUITS (Continued)
LOW to HIGH
+
FOD8318
–
+
5V –
0.1 mF
1
V IN+
VE
16
2
V IN–
V LED2+
15
3
V DD1
DESAT
14
4
GND1
V DD2
13
5
RESET
VS
12
6
FAULT
VO
11
7
V LED1+
V CLAMP
10
8
V LED1−*
V SS
9
100 pF
0.1 mF
VE
VO
+
–
+
30 V –
0.1 mF
RL
3 kW
V FAULT
10 nF
Figure 46. DESAT Sense (tDESAT(90 %), tDESAT(10 %)), DESAT Fault (tDESAT(FAULT)), and (tDESAT(LOW)) Test Circuit
FOD8318
0.1 mF
+
5V –
3 kW
VE
1
V IN+
2
V IN–
V LED2+
15
3
V DD1
DESAT
14
4
GND1
V DD2
13
5
RESET
VS
12
6
FAULT
VO
11
7
V LED1+
V CLAMP
10
8
V LED1−*
V SS
9
Strobe 8 V
0.1 mF
VE
0.1 mF
30 V
VO
+
–
+
–
RL
+
V FAULT
16
–
10 nF
Figure 47. Reset Delay (tRESET(FAULT)) Test Circuit
FOD8318
0.1 mF
+
5V –
1
V IN+
VE
16
2
V IN–
V LED2+
15
3
V DD1
DESAT
14
4
GND1
V DD2
13
5
RESET
VS
12
6
FAULT
VO
11
3 kW
7
V LED1+
V CLAMP
10
8
V LED1−*
V SS
9
0.1 mF
VE
+
–
VO
0.1 mF
+
V DD2**
–
**1.0 ms ramp for tUVLO
**10 ms ramp for tGP
Figure 48. Under−Voltage Lockout Delay (tUVLO) and Time to Good Power (tGP) Test Circuit
www.onsemi.com
18
FOD8318
TEST CIRCUITS (Continued)
FOD8318
5V
0.1 mF
1 kW
300 pF
1
VIN+
VE
16
2
VIN–
VLED2+
15
3
VDD1
DESAT
14
4
GND1
VDD2
13
5
RESET
VS
12
6
FAULT
VO
11
7
VLED1+
VCLAMP
10
8
VLED1−*
VSS
9
25 V
0.1 mF
SCOPE
10 W
10 nF
VCM
Floating GND
Figure 49. Common Mode Low (CML) Test Circuit at LED1 Off
FOD8318
5V
0.1 mF
1 kW
300 pF
Floating GND
1
VIN+
VE
16
2
VIN–
VLED2+
15
3
VDD1
DESAT
14
4
GND1
VDD2
13
5
RESET
VS
12
6
FAULT
VO
11
7
VLED1+
VCLAMP
10
8
VLED1− *
VSS
9
25 V
VCM
Figure 50. Common Mode High (CMH) Test Circuit at LED1 On
www.onsemi.com
19
0.1 mF
SCOPE
10 W
10 nF
FOD8318
TEST CIRCUITS (Continued)
FOD8318
5V
0.1 mF
1
V IN+
VE
16
2
V IN–
VLED2+
15
3
V DD1
DESAT
14
4
GND1
VDD2
13
5
RESET
VS
12
6
FAULT
VO
11
7
V LED1+
VCLAMP
10
8
V LED1−*
VSS
9
25 V
0.1 mF
1 kW
SCOPE
300 pF
10 W
10 nF
VCM
Floating GND
Figure 51. Common Mode High (CMH) Test Circuit at LED2 Off
FOD8318
5V
0.1 mF
1 kW
SCOPE
300 pF
1
VIN+
VE
16
2
VIN–
VLED2+
15
3
VDD1
DESAT
14
4
GND1
VDD2
13
750 W
25 V
0.1 mF
5
RESET
VS
12
6
FAULT
VO
11
7
VLED1+
VCLAMP
10
8
VLED1− *
VSS
9
10 W
10 nF
VCM
Floating GND
Figure 52. Common Mode Low (CML) Test Circuit at LED2 On
www.onsemi.com
20
+
–
9V
FOD8318
TEST CIRCUITS (Continued)
FOD8318
+
5V –
0.1 mF
1
V IN+
VE
16
2
V IN–
V LED2+
15
3
V DD1
DESAT
14
4
GND1
V DD2
13
5
RESET
VS
12
6
FAULT
VO
11
7
V LED1+
V CLAMP
10
8
V LED1−*
V SS
9
0.1 mF
0V
+
–
0.1 mF
+
–
ICLAMPL
+
3 kW
Pulsed
– V CLAMP
Figure 53. Clamp Low Level Sinking Current (ICLAMPL)
A
FOD8318
S1
1
V IN+
VE
16
2
V IN–
V LED2+
15
3
V DD1
DESAT
14
4
GND1
V DD2
13
5
RESET
VS
12
6
FAULT
VO
11
7
V LED1+
V CLAMP
10
8
V LED1−*
V SS
9
B
+
5V –
0.1 mF
0.1 mF
+
30 V –
Initially set S1 to A before connecting 3 V to clamp pin. Then switch to B before sweeping down
to get the VCLAMP_THRES, clamping threshold voltage.
Figure 54. Clamp Pin Threshold Voltage (VCLAMP)
21
+
–
0.1 mF
3 kW
www.onsemi.com
0V
50 W
+ Sweep from 3 V
–+ to V
CLAMP_THRES
FOD8318
TIMING DIAGRAMS
V IN+
2.5 V
V IN–
0V
2.5 V
tR
tF
90%
50%
10%
VO
tPHL
tPLH
Figure 55. Propagation Delay (tPLH, tPHL), Rise Time (tR), and Fall Time (tF) Timing Diagram
50%
RESET
t DESAT (LOW)
7V
VDESAT
tRESET (FAULT)
50%
t DESAT (90%)
90%
VO
10%
t DESAT (10%)
50% (0.5 x V DD1 )
FAULT
t DESAT (FAULT)
Figure 56. Definitions for Fault Reset Input (RESET), Desaturation Voltage Input (DESAT), Output Voltage (VO),
and Fault Output (FAULT) Timing Waveforms
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22
FOD8318
APPLICATION INFORMATION
VIN+
2
VIN–
VLED2+ 15
3
V DD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
11
7
VLED1+
8
VLED1− *
VE 16
1 mF
10 mF
C BLANK
100 pF
D DESAT
1 kW
3 kW
Micro
Controller
5 V + 0.1 mF
–
FOD8318
1
330 pF
VDD2 13
VO
–
+
Q1
+ V DD2 = 15 V
–
1 mF
+
VF
VCE
Rg
–
3−Phase
Output
VCLAMP 10
Q2
9
VSS
+
VCE
–
Figure 57. Recommended Application Circuit
Functional Description
The relationship between the inputs and output are
illustrated in the Figure 59.
During normal operation, when no fault is detected, the
FAULT output, which is an open−drain configuration, is
latched to HIGH state. This allows the gate driver to be
controlled by the input logic signal.
When a fault is detected, the FAULT output is latched to
LOW state. This condition remains until the input logic is
pulled to LOW and the RESET pin is also pulled LOW for
a period longer than PWRESET.
The functional behavioral of FOD8318 is illustrated by
the detailed internal schematic shown in Figure 58. This
explains the interaction and sequence of internal and
external signals, together with the timing diagrams.
Non−Inverting and Inverting Inputs
There are two CMOS/TTL−compatible inputs, VIN+ and
VIN−, to control the IGBT in non−inverting and inverting
configurations, respectively. When VIN− is set to LOW state,
VIN+ controls the driver output, VO, in non−inverting
configuration. When VIN+ is set to HIGH state, VIN−
controls the driver output in inverting configuration.
250 mA
+
–
VDD1
3
VLED+
VIN+
1
7
VIN–
2
FAULT
14
DESAT
VDESAT
Gate Drive
Optocoupler
16
VE
UVLO Comparator
6
–
+
13
12 V
12
4
VDD2
VS
GND1
Delay
VLED1– 8
R S
RESET
5
11
Q
Fault Sense
Optocoupler
50x
5 ms Pulse
Generator
1x
15
VLED2+
Figure 58. Detailed Internal Schematic
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23
VO
9, 10
VSS
FOD8318
Gate Driver Output
A pair of PMOS and NMOS comprise the output driver
stage, which facilitates close to rail−to−rail output swing.
This feature allows a tight control of gate voltage during
on−state and short−circuit condition. The output driver is
typically to sink 2 A and source 2 A at room temperature.
Due to the low RDS(ON) of the MOSFETs, the power
dissipation is reduced as compared to those bipolar−type
driver output stages. The absolute maximum rating of the
output peak current, IO(PEAK), is 3 A; therefore the careful
selection of the gate resistor, Rg, is required to limit the
short−circuit current of the IGBT.
As shown in Figure 58, gate driver output is influenced by
signals from the photodetector circuitry, the UVLO
comparator, and the DESAT signals. Under no−fault
condition, normal operation resumes while the supply
voltage is above the UVLO threshold, the output of the
photodetector drives the MOSFETs of the output stage.
The logic circuitry of the output stage ensures that the
push−pull devices are never “ON” simultaneously. When
the output of the photodetector is HIGH, the output, VO, is
pulled to HIGH state by turning on the PMOS. When the
output of the photodetector is LOW, VO is pulled to LOW
state by turning on the NMOS.
When VDD2 supply goes below VUVLO, which is the
designated UVLO threshold at the comparator, VO is pulled
down to LOW state regardless of photodetector output.
When desaturation is detected, VO turns off slowly as it is
pulled LOW by the 1XNMOS device. The input to the fault
sense circuitry is latched to HIGH state and turns on the
LED. When VO goes below 2 V, the 50XNMOS device turns
on again, clamping the IGBT gate firmly to VSS. The Fault
Sense signal remains latched in the HIGH state until the
LED of the gate driver circuitry turns off.
external capacitance (CBLANK), FAULT threshold voltage
(VDESAT), and DESAT charge current (ICHG) as:
t BLANK + C BLANK
V DESAT ń I CHG
(eq. 1)
With a recommended 100 pF DESAT capacitor, the
nominal blanking time is:
100 pF
7 V ń 250 mA + 2.8 ms
“Soft” Turn−Off
The soft turn−off feature ensures the safe turn off of the
IGBT under fault conditions. This reduces the voltage spike
on the collector of the IGBT. Without this, the IGBT would
see a heavy spike on the collector and result in permanent
damage to the device.
Under−Voltage Lockout
Under−voltage detection prevents the application of
insufficient gate voltage to the IGBT. This could be
dangerous, as it would drive the IGBT out of saturation and
into the linear operation where the losses are very high and
quickly overheated. This feature ensures the proper
operating of the IGBTs. The output voltage, VO, remains
LOW regardless of the inputs as long as the supply voltage,
VDD2 – VE, is less than VUVLO+. When the supply voltage
falls below VUVLO−, VO goes LOW, as illustrated in
Figure 61.
Active Miller Clamp Function
An active Miller clamp feature allows the sinking of the
Miller current to the ground or emitter of the IGBT during
a high−dV/dt situation. Instead of driving the IGBT gate to
a negative supply voltage to increase the safety margin, the
device has a dedicated VCLAMP pin to control the Miller
current. During turn−off, the gate voltage of the IGBT is
monitored and the VCLAMP output is activated when the gate
voltage goes below 2 V (relative to VSS). The Miller clamp
NMOS transistor is then turned on and provides a low
resistive path for the Miller current. This helps prevent a
self−turn−on due to the parasitic Miller capacitor in power
switches. The clamp voltage is VOL + 2.5 V maximum for
a Miller current up to 1200 mA. In this way, the VCLAMP
function does not affect the turn−off characteristic. It helps
to clamp the gate to the LOW level throughout the turn−off
time. During turn−on, where the input of the driver is
activated, the VCLAMP function is disabled or opened.
Desaturation Protection, FAULT Output
Desaturation detection protection ensures the protection
of the IGBT at short−circuit by monitoring the
collector−emitter voltage of the IGBT in the half bridge.
When the DESAT voltage goes up and reaches above the
threshold voltage, a short−circuit condition is detected and
the driver output stage executes a “soft” IGBT turn−off and
is eventually driven LOW, as illustrated in Figure 60. The
FAULT open−drain output is triggered active LOW to report
a desaturation error. It is only cleared by activating active
LOW by the external controller to the RESET input with the
input logic is pulled to LOW.
The DESAT fault detector should be disabled for a short
period (blanking time) before the IGBT turns on to allow the
collector voltage to fall below DESAT threshold. This
blanking period protects against false trigger of the DESAT
while the IGBT is turning on.
The blanking time is controlled by the internal DESAT
charge current, the DESAT voltage threshold, and the
external DESAT capacitor (capacitor between DESAT and
VE pin). The nominal blanking time can be calculated using
Time to Good Power
At initial power up, the LED is off and the output of the
gate driver should be in the LOW state. Sometimes race
conditions exist that causes the output to follow the VE
(assuming VDD2 and VE are connected externally), until all
of the circuits in the output IC have stabilized. This
condition can result in output transitions or transients that
are coupled to the driven IGBT. These glitches can cause the
high−side and low−side IGBTs to conduct shoot−through
current that may result in destructive damage to the power
semiconductor devices. ON has introduced a initial turn−on
www.onsemi.com
24
FOD8318
delay, generally called “time−to−good power”. This delay,
typically 2.5 ms, is only present during the initial power−up
of the device. Once powered, the “time−to−good power”
delay is determined by the delay of the UVLO circuitry.
If the LED is “ON” during the initial turn−on activation,
LOW−to−HIGH transition at the output of the gate driver
only occurs 2.5 ms after the VDD2 power is applied.
V IN–
V IN+
VO
Figure 59. Input/Output Relationship
Normal
Operation
V IN–
Fault Condition
Reset
0V
5V
V IN+
0V
Blanking
Time
RESET
7V
V DESAT
VO
FAULT
Figure 60. Timing Relationship Among DESAT, FAULT, and RESET
V IN–
5V
0V
V IN+
V UVLO+
V DD2 −VE
VO
Figure 61. UVLO for Output Side
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25
V UVLO–
FOD8318
REFLOW PROFILE
260
240
220
200
TP
Max. Ramp−up Rate = 3°C/S
Max. Ramp−down Rate = 6°C/S
tP
TL
Tsmax
Temperature (°C)
180
160
tL
Preheat Area
Tsmin
140
ts
120
100
80
60
40
20
0
120
240
360
Time 25°C to Peak
Time (seconds)
Profile Freature
Pb−Free Assembly Profile
Temperature Minimum (Tsmin)
150°C
Temperature Maximum (Tsmax)
200°C
Time (tS) from (Tsmin to Tsmax)
60 − 120 seconds
Ramp−up Rate (tL to tP)
3°C/second max.
Liquidous Temperature (TL)
217°C
Time (tL) Maintained Above (TL)
60 – 150 seconds
Peak Body Package Temperature
260°C +0°C / –5°C
Time (tP) within 5°C of 260°C
30 seconds
Ramp−down Rate (TP to TL)
6°C/second max.
Time 25°C to Peak Temperature
8 minutes max.
Figure 62. Reflow Profile
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26
FOD8318
ORDERING INFORMATION
Package
Shipping†
FOD8318
SOIC16 W, SO 16−Pin
(Pb−Free)
50 Units / Tube
FOD8318R2
SOIC16 W, SO 16−Pin
(Pb−Free)
750 Units / Tape & Reel
FOD8318V
SOIC16 W, SO 16−Pin, DIN EN/IEC 60747−5−5 Option
(Pb−Free)
50 Units / Tube
FOD8318R2V
SOIC16 W, SO 16−Pin, DIN EN/IEC 60747−5−5 Option
(Pb−Free)
750 Units / Tape & Reel
Part Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
30. All packages are lead free per JEDEC: J−STD−020B standard.
OPTOPLANAR is registered trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States
and/or other countries.
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27
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC16 W
CASE 751EN
ISSUE A
GENERIC
MARKING DIAGRAM*
AWLYWW
XXXXXXXXXX
XXXXXXXXXX
DOCUMENT NUMBER:
DESCRIPTION:
XXXX
A
WL
Y
WW
98AON13751G
SOIC16 W
DATE 24 AUG 2021
= Specific Device Code *This information is generic. Please refer to
= Assembly Location
device data sheet for actual part marking.
= Wafer Lot
Pb−Free indicator, “G” or microdot “G”, may
= Year
or may not be present. Some products may
= Work Week
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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