FPF1321BUCX

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Other names and brands may be claimed as the property of others. IntelliMAX] Dual-Input Single-Output Advanced Power Switch with True Reverse-Current Blocking FPF1320, FPF1321 www.onsemi.com Description The FPF1320/21 is a Dual−Input Single−Output (DISO) load switch consisting of two sets of slew−rate controlled, low on−resistance, P−channel MOSFET switches and integrated analog features. The slew−rate−controlled turn−on characteristic prevents inrush current and the resulting excessive voltage droop on the power rails. The input voltage range operates from 1.5 V to 5.5 V to align with the requirements of low−voltage portable device power rails. FPF1320/21 performs seamless power−source transitions between two input power rails using the SEL pin with advanced break−before−make operation. FPF1320/21 has a TRCB function to block unwanted reverse current from output to input during ON/OFF states. The switch is controlled by logic inputs of the SEL and EN pins, which are capable of interfacing directly with low−voltage control signals (GPIO). FPF1321 has 65 W on−chip load resistor for output quick discharge when EN is LOW. FPF1320/21 is available in 1.0 mm x 1.5 mm WLCSP, 6−bump, with 0.5 mm pitch. FPF1321B is available in 1.0 mm x 1.5 mm WLCSP, 6−bump, 0.5 mm pitch with backside laminate. Features • • • • • • • • • • DISO Load Switches Input Supply Operating Range: 1.5 V ~ 5.5 V RON 50 mW at VIN = 3.3 V Per Channel (Typical) True Reverse − Current Blocking (TRCB) Fixed Slew Rate Controlled 130 ms for < 1 mF COUT ISW: 1.5 A Per Channel (Maximum) Quick Discharge Feature on FPF1321 Logic CMOS IO Meets JESD76 Standard for GPIO Interface and Related Power Supply Requirements ESD Protected: ♦ Human Body Model: > 6 kV ♦ Charged Device Model: > 1.5 kV ♦ IEC 61000−4−2 Air Discharge: > 15 kV ♦ IEC 61000−4−2 Contact Discharge: > 8 kV These are Pb−Free and Halide Free Devices WLCSP−6 CASE 567RM MARKING DIAGRAM Qx&K &.&2&Z Qx &K &. &2 &Z = Specific Device Code x = S or T = Traceability Code = Pin one dot = Date Code = Assembly plant code ORDERING INFORMATION See detailed ordering and shipping information on page 12 of this data sheet. Applications • Smart Phones / Tablet PCs • Portable Devices • Near Field Communication (NFC) Capable SIM Card Power Supply © Semiconductor Components Industries, LLC, 2011 July, 2021 − Rev. 3 1 Publication Order Number: FPF1321/D FPF1320, FPF1321 APPLICATION DIAGRAM VIN_A VINA VOUT CIN1 COUT FPF1320/21 VIN_B VINB CIN2 GND SEL EN Figure 1. Typical Application BLOCK DIAGRAM TRCB VIN_A VOUT Turn−On Slew Rate Controlled Driver FPF1320/21 Output Discharge (Optional) TRCB VIN_B Turn−On Slew Rate Controlled Driver SEL Control logic GND EN Figure 2. Functional Block Diagram (Output Discharge Path for FPF1321 Only) www.onsemi.com 2 FPF1320, FPF1321 PIN CONFIGURATION Pin 1 Indicator EN VINA VINA EN A1 A2 A2 A1 SEL VOUT VOUT SEL B1 B2 B2 B1 GND VINB VINB GND C1 C2 C2 C1 Top View Bottom View Figure 3. Pin Assignments PIN DESCRIPTION Pin # Name A1 EN Enable input. Active HIGH. There is an internal pull−down resistor at the EN pin. Description B1 SEL Input power selection inputs. See Truth Table. There are internal pull−down resistors at the SEL pins. A2 VINA Supply Input. Input to the power switch A. B2 VOUT Switch output C1 GND Ground C2 VINB Supply Input. Input to power switch B. TRUTH TABLE SEL EN Switch A Switch B VOUT Status Low High ON OFF VINA VINA Selected High High OFF ON VINB VINB Selected X Low OFF OFF Floating for FPF1320 GND for FPF1321 Both Switches are OFF www.onsemi.com 3 FPF1320, FPF1321 ABSOLUTE MAXIMUM RATINGS Symbol Parameters Min Max Unit −0.3 6 V VIN VINA, VINB, VSEL, VEN, VOUT to GND ISW Maximum Continuous Switch Current per Channel − 1.5 A PD Total Power Dissipation at TA = 25°C − 1.2 W −65 150 °C − 85 (Note 1) °C/W − 110 (Note 2) 6.0 − Charged Device Model, JESD22−C101 1.5 − Air Discharge (VINA, VINB to GND), IEC61000−4−2 System Level 15.0 − Contact Discharge (VINA, VINB to GND), IEC61000−4−2 System Level 8.0 − TSTG Operating and Storage Junction Temperature QJA Thermal Resistance, Junction−to−Ambient (1 in.2 Pad of 2−oz. Copper) ESD Electrostatic Discharge Capability Human Body Model, JESD22−A114 kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Measured using 2S2P JEDEC std. PCB. 2. Measured using 2S2P JEDEC PCB cold−plate method. RECOMMENDED OPERATING CONDITIONS Symbol Parameters Min Max Unit VIN Input Voltage on VINA, VINB 1.5 5.5 V TA Ambient Operating Temperature −40 85 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. ELECTRICAL CHARACTERISTICS VINA = VINB = 1.5 to 5.5 V, TA = −40 to 85°C unless otherwise noted. Typical values are at VINA = VINB = 3.3 V, TA = 25°C Parameter Symbol Test Conditions Min Typ Max Unit 1.5 − 5.5 V BASIC OPERATION VINA, VINB Input Voltage − ISD Shutdown Current SEL = HIGH or LOW, EN = GND, VOUT = GND, VINA = VINB = 5.5 V − − 5 mA IQ Quiescent Current IOUT = 0 mA, SEL = HIGH or LOW, EN = HIGH, VINA = VINB = 5.5 V − 12 22 mA On−Resistance VINA = VINB = 5.5 V, IOUT = 200 mA, TA = 25°C − 42 60 mW VINA = VINB = 3.3 V, IOUT = 200 mA, TA = 25°C − 50 − VINA = VINB = 1.8 V, IOUT = 200 mA, TA = 25°C to 85°C − 80 − VINA = VINB = 1.5 V, IOUT = 200 mA, TA = 25°C − − 170 RON VIH SEL, EN Input Logic High Voltage VINA, VINB = 1.5 V – 5.5 V 1.15 − − V VIL SEL, EN Input Logic Low Voltage VINA, VINB = 1.8 V – 5.5 V − − 0.65 V SEL, EN Input Logic Low Voltage VINA, VINB = 1.5 V – 1.8 V − − 0.60 Output Voltage Droop while Channel Switching from Higher Input Voltage Lower Input Voltage (Note 3) VINA = 3.3 V, VINB = 5 V, Switching from VINA → VINB, RL = 150 W, COUT = 1 mF − − 100 mV Input Leakage at SEL and EN Pin − − − 1.2 mA VDROOP_OUT ISEL/IEN www.onsemi.com 4 FPF1320, FPF1321 ELECTRICAL CHARACTERISTICS VINA = VINB = 1.5 to 5.5 V, TA = −40 to 85°C unless otherwise noted. Typical values are at VINA = VINB = 3.3 V, TA = 25°C (continued) Symbol Parameter Test Conditions Min Typ Max Unit BASIC OPERATION (continued) RSEL_PD/ REN_PD RPD Pull−Down Resistance at SEL or EN Pin − − 7 − MW Output Pull−Down Resistance SEL = HIGH or LOW, EN = GND, IFORCE = 20 mA, TA = 25°C, FPF1321 − 65 − W TRUE REVERSE CURRENT BLOCKING VT_RCB RCB Protection Trip Point VOUT − VINA or VINB − 45 − mV VR_RCB RCB Protection Release Trip Point VINA or VINB −VOUT − 25 − mV IRCB VINA or VINB Current During RCB VOUT = 5.5 V, VINA or VINB = Short to GND − 9 15 mA RCB Response Time w hen Device is ON (Note 3) VINA or VINB = 5 V, VOUTVINA,B = 100 mV − 5 − ms VINA or VINB = 3.3 V, RL = 150 W, CL = 1 mF, TA = 25°C, SEL: HIGH, EN: LOW → HIGH − 120 − ms − 130 − − 250 − − 15 − − 320 − − 335 − VINA or VINB = 3.3 V, RL = 150 W, CL = 1 mF, TA = 25°C, SEL: HIGH, EN: HIGH→ LOW, Output Discharge Mode, FPF1321 − 6 − − 110 − − 116 − VINA = 3.3 V, VINB = 5 V, Switching from VINA → VINB, SEL: LOW → HIGH, EN: HIGH, RL = 150 W, CL = 1 mF, TA = 25°C − 3 − − 1 − VINA = 3.3 V, VINB = 5 V, Switching from VINB → VINA, SEL: HIGH → LOW, EN: HIGH, RL = 150 W, C = 1 mF, TA = 25°C − 45 − − 5 − tRCB_ON DYNAMIC CHARACTERISTICS tDON Turn−On Delay (Note 4) tR VOUT Rise Time (Note 4) tON Turn−On Time (Note 6) tDOFF Turn−Off Delay (Note 4) tF VOUT Fall Time (Note 4) tOFF Turn−Off Time (Note 7) tDOFF Turn−Off Delay (Note 4, Note 5) tF VOUT Fall Time (Note 4, Note 5) tOFF Turn−Off Time (Note 5, Note 7) tTRANR tSLH tTRANF tSHL Transition Time LOW → HIGH (Note 4) Switch−Over Rising Delay (Note 4) Transition Time HIGH → LOW (Note 4) Switch−Over Falling Delay (Note 4) VINA or VINB = 3.3 V, RL = 150 W, CL = 1 mF, TA = 25°C, SEL: HIGH, EN: HIGH→ LOW ms ms ms ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. This parameter is guaranteed by design and characterization; not production tested. 4. tDON/tDOFF/tR/tF/tTRANR/tTRANF/tSLH/tSHL are defined in Figure 4. 5. FPF1321 output discharge is enabled during off. 6. tON = tR + tDON 7. tOFF = tF + tDOFF www.onsemi.com 5 FPF1320, FPF1321 TIMING DIAGRAM VINA 5V VINB 3.3 V HI SEL 50% 50% LO LO HI EN 50% LO VOUT tDON tR 90% LO tSHL 5V 5V 90% 10% 3.3 V 90% tF 90% 10% VDROOP Turn−on and VINA tDOFF 10% GND Shutdown 50% tSLH tTRANR tTRANF Switching from VINA to VINB Switching from VINB to VINA Figure 4. Dynamic Behavior Timing Diagram www.onsemi.com 6 Output discharge of FPF1321 Shutdown GND FPF1320, FPF1321 TYPICAL CHARACTERISTICS 14.0 25.0 12.0 15.0 Quiecent Current (mA) Quiecent Current (mA) 20.0 VIN = 5.5 V 10.0 5.0 0.0 −40 VIN = 1.5 V −25 −10 5 20 35 50 65 2.5 3 3.5 4 4.5 5 Supply Voltage (V) Figure 5. Supply Current vs. Temperature Figure 6. Supply Current vs. Supply Voltage 5.5 3000 Shutdown Current (nA) 3000 VIN = 5.5 V 2000 1000 0 2500 1500 1000 VIN = 1.5 V −25 −10 5 20 35 50 65 85°C 2000 −40°C 25°C 500 0 1.5 80 2 2.5 3 3.5 4 4.5 5 5.5 TJ, Junction Temperature (5C) Supply Voltage (V) Figure 7. Shutdown Current vs. Temperature Figure 8. Shutdown Current vs. Supply Voltage 140 IOUT = 200 mA 120 VINA = 1.5 V 100 RON, On Resistance (mW) Shutdown Current (nA) 2 TJ, Junction Temperature (5C) 4000 RON, On Resistance (mW) 4.0 0.0 1.5 5000 VINA = 1.8 V 80 60 VINA = 3.3 V 40 VINA = 5.5 V 20 0 −40 −40°C 6.0 80 6000 140 25°C 8.0 2.0 7000 −1000 −40 85°C 10.0 −20 0 20 40 60 IOUT = 200 mA 120 100 85°C 80 60 40 25°C 0 1.5 80 −40°C 20 2 2.5 3 3.5 4 4.5 TJ, Junction Temperature (5C) Supply Voltage (V) Figure 9. RON vs. Temperature Figure 10. RON vs. Supply Voltage www.onsemi.com 7 5 5.5 FPF1320, FPF1321 TYPICAL CHARACTERISTICS (continued) 1.00 0.95 Input Logic Low Voltage (V) Input Logic Low Voltage (V) 1.00 VIN = 5.5 V 0.90 VIN = 3.3 V 0.85 0.80 VIN = 1.5 V 0.75 0.70 0.65 0.60 −40 −25 −10 5 20 35 50 65 0.80 0.75 2.3 2.8 3.3 3.8 4.3 4.8 Supply Voltage (V) Figure 11. VIL vs. Temperature Figure 12. VIL vs. Supply Voltage Input Logic High Voltage (V) 0.90 VIN = 3.3 V 0.85 0.80 VIN = 1.5 V 0.75 0.70 0.65 −25 −10 5 20 35 50 65 5.3 −40°C 0.90 25°C 85°C 0.85 0.80 0.75 2.3 2.8 3.3 3.8 4.3 4.8 TJ, Junction Temperature (5C) Supply Voltage (V) Figure 13. VIH vs. Temperature Figure 14. VIH vs. Supply Voltage 5.3 9.0 25°C 0.95 VIH 0.90 VIL 0.85 0.80 0.75 2.3 0.95 0.70 1.8 80 Pull−Down Resistance (MW) Input Logic High Voltage (V) 85°C 0.85 TJ, Junction Temperature (5C) VIN = 5.5 V 0.60 −40 Input Logic Voltage (V) 25°C 1.00 0.95 0.70 1.8 −40°C 0.90 0.70 1.8 80 1.00 1.00 0.95 2.8 3.3 3.8 4.3 4.8 8.5 8.0 7.5 EN = 6 V 7.0 EN = 1.5 V 6.5 6.0 5.5 −40 5.3 −20 0 20 40 60 80 Supply Voltage (V) TJ, Junction Temperature (5C) Figure 15. VIH/VIL vs. Supply Voltage Figure 16. RSEL_PD and REN_PD vs. Temperature www.onsemi.com 8 FPF1320, FPF1321 TYPICAL CHARACTERISTICS (continued) 179 −40°C 8.0 7.5 7.0 25°C 6.5 6.0 85°C 5.5 5.0 1.5 3.5 4.5 tDON 119 99 79 59 39 tDOFF −1 −40 5.5 −15 35 60 85 TJ, Junction Temperature (5C) Figure 17. RSEL_PD and REN_PD vs. Supply Voltage Figure 18. tDON and tDOFF vs. Temperature 190 410 tF Rise/Fall Time (ms) 310 260 210 160 60 10 −40 VIN = 3.3 V CL = 1 mF RL = 150 W −15 35 150 tR 130 110 tF 90 70 50 tR 10 VIN = 3.3 V CL = 1 mF RL = 150 W 170 360 110 30 60 10 −40 85 −15 TJ, Junction Temperature (5C) 35 60 85 Figure 20. tR and tF with FPF1321 vs. Temperature 60 5 5 Switch−Over Delay (ms) tTRANF 50 VIN = 5 V to 3.3 V CL = 1 mF RL = 150 W 40 30 20 10 0 −40 10 TJ, Junction Temperature (5C) Figure 19. tR and tF with FPF1320 vs. Temperature Transition Time (ms) 10 Supply Voltage (V) 460 Rise/Fall Time (ms) 139 19 2.5 VIN = 3.3 V CL = 1 mF RL = 150 W 159 On/Off Delay Time (ms) Pull−Down Resistance (MW) 8.5 −15 4 3 3 2 2 1 1 tTRANR 10 35 60 0 −40 85 tSHL 4 tSLH VIN = 5 V to 3.3 V CL = 1 mF RL = 150 W −15 10 35 60 TJ, Junction Temperature (5C) TJ, Junction Temperature (5C) Figure 21. Transition Time vs. Temperature Figure 22. Switch Over Time vs. Temperature www.onsemi.com 9 85 FPF1320, FPF1321 70 12.0 60 11.0 10.0 50 Trip 40 30 IRCB (mA) RCB Trip/Release A (mV) TYPICAL CHARACTERISTICS (continued) Release 20 9.0 8.0 7.0 6.0 10 5.0 0 −40 −25 −10 5 20 35 50 65 4.0 −40 80 −25 −10 5 20 35 50 65 TJ, Junction Temperature (5C) TJ, Junction Temperature (5C) Figure 23. TRCB Trip and Release vs. Temperature Figure 24. IRCB vs. Temperature 80 Output Pull Down Resistance (W) 85.0 80.0 75.0 70.0 RPD 65.0 60.0 55.0 50.0 45.0 −40 −20 0 20 40 60 80 Figure 25. RPD with FPF1321 vs. Temperature Figure 26. Turn−On Response (VINA = 3.3 V, CIN = 1 mF, COUT = 1 mF, RL = 150 W, SEL = LOW) Figure 27. Turn−Off Response with FPF1320 (VINA = 3.3 V, CIN = 1 mF, COUT = 1 mF, RL = 150 W, SEL = LOW) Figure 28. Turn−Off Response with FPF1321 (VINA = 3.3 V, CIN = 1 mF, COUT = 1 mF, RL = 150 W, SEL = LOW) TJ, Junction Temperature (5C) www.onsemi.com 10 FPF1320, FPF1321 TYPICAL CHARACTERISTICS (continued) Figure 30. Power Source Transition from 5 V to 3.3 V (VINA = 3.3 V, VINB = 5 V, CIN = 1 mF, COUT = 1 mF, RL = 150 W) Figure 29. Power Source Transition from 3.3 V to 5 V (VINA = 3.3 V, VINB = 5 V, CIN = 1 mF, COUT = 1 mF, RL = 150 W) Figure 31. TRCB During Off (VINA = VINB = Floating, VOUT = 5 V, CIN = 1 mF, COUT = 1 mF, EN = LOW, No RL) Figure 32. TRCB During On (VINA = 5 V, VOUT = 6 V, CIN = 1 mF, COUT = 1 mF, EN = HIGH, No RL) OPERATION AND APPLICATION DESCRIPTION Input Capacitor The FPF1320 and FPF1321 are dual−input single−output power multiplexer switches with controlled turn−on and seamless power source transition. The core is a 50 mW P−channel MOSFET and controller capable of functioning over a wide input operating range of 1.5 V to 5.5 V per channel. The EN and SEL pins are active−HIGH, GPIO/CMOS−compatible input. They control the state of the switch and input power source selection, respectively. TRCB functionality blocks unwanted reverse current during both ON and OFF states when higher VOUT than VINA or VINB is applied. FPF1321 has a 65 W output discharge path during off. To limit the voltage drop on the input supply caused by transient inrush current when the switch turns on into a discharged load capacitor; a capacitor must be placed between the VINA or VINB pins to the GND pin. At least 1 mF ceramic capacitor, CIN, placed close to the pins, is usually sufficient. Higher−value CIN can be used to reduce more the voltage drop. Inrush Current Inrush current occurs when the device is turned on. Inrush current is dependent on output capacitance and slew rate control capability, as expressed by: IINRUSH + COUT www.onsemi.com 11 VIN * VINITIAL ) I LOAD tR (eq. 1) FPF1320, FPF1321 FPF1320/1 adopts an advanced break−before−make control, which can result in minimized output voltage drop during the transition time. where: COUT: Output capacitance; tR: Slew rate or rise time at VOUT; VIN: Input voltage, VINA or VINB; VINITIAL: Initial voltage at COUT, usually GND; and ILOAD: Load current. Output Capacitor Capacitor COUT of at least 1 mF is highly recommended between the VOUT and GND pins to achieve minimized output voltage drop during input power source transition. This capacitor also prevents parasitic board inductance. Higher inrush current causes higher input voltage drop, depending on the distributed input resistance and input capacitance. High inrush current can cause problems. FPF1320/1 has a 130 ms of slew rate capability under 3.3 VIN at 1 mF of COUT and 150 W of RL so inrush current and input voltage drop can be minimized. True Reverse−Current Blocking The true reverse−current blocking feature protects the input source against current flow from output to input regardless of whether the load switch is on or off. Power Source Selection Board Layout Input power source selection can be controlled by the SEL pin. When SEL is LOW, output is powered from VINA while SEL is HIGH, VINB is powering output. The SEL signal is ignored during device OFF. For best performance, all traces should be as short as possible. To be most effective, the input and output capacitors should be placed close to the device to minimize the effect that parasitic trace inductance on normal and short−circuit operation. Wide traces or large copper planes for power pins (VINA, VINB, VOUT and GND) minimize the parasitic electrical effects and the thermal impedance. Output Voltage Drop During Transition Output voltage drop usually occurs during input power source transition period from low voltage to high voltage. The drop is highly dependent on output capacitance and load current. ORDERING INFORMATION Channel Switch Per Channel (Typ.) at 3.3 VIN Reverse Current Blocking Output Discharge Rise Time (tR) QS DISO 50 mW Yes NA 130 ms FPF1321UCX QT DISO 50 mW Yes 65 W 130 ms FPF1321BUCX QT DISO 50 mW Yes 65 W 130 ms Top Mark FPF1320UCX Part Number Package 1.0 mm × 1.5 mm Wafer−Level Chip−Scale Package (WLCSP) 6−Bumps, 0.5 mm Pitch 1.0 mm × 1.5 mm Wafer−Level Chip−Scale Package (WLCSP) 6−Bumps, 0.5 mm Pitch with Backside Laminate PRODUCT−SPECIFIC DIMENSIONS Product D E X Y FPF1320UCX 1460 mm ±30 mm 960 mm ±30 mm 230 mm 230 mm FPF1321UCX 1460 mm ±30 mm 960 mm ±30 mm 230 mm 230 mm FPF1321BUCX 1460 mm ±30 mm 960 mm ±30 mm 230 mm 230 mm IntelliMAX is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WLCSP6 1.46x0.96x0.582 CASE 567RM ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON16579G WLCSP6 1.46x0.96x0.582 DATE 30 NOV 2016 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. 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