FSFR1700XSL

DATA SHEET www.onsemi.com Power Switch for Half-Bridge Resonant Converters SIP9 26x10.5 CASE 127EM FSFR-XS Series Description The FSFR−XS series includes highly integrated power switches designed for high−efficiency half−bridge resonant converters. Offering everything necessary to build a reliable and robust resonant converter, the FSFR−XS series simplifies designs while improving productivity and performance. The FSFR−XS series combines power MOSFETs with fast−recovery type body diodes, a high−side gate−drive circuit, an accurate current controlled oscillator, frequency limit circuit, soft−start, and built−in protection functions. The high−side gate−drive circuit has common−mode noise cancellation capability, which guarantees stable operation with excellent noise immunity. The fast−recovery body diode of the MOSFETs improves reliability against abnormal operation conditions, while minimizing the effect of reverse recovery. Using the zero−voltage−switching (ZVS) technique dramatically reduces the switching losses and significantly improves efficiency. The ZVS also reduces the switching noise noticeably, which allows a small−sized Electromagnetic Interference (EMI) filter. The FSFR−XS series can be applied to resonant converter topologies such as series resonant, parallel resonant, and LLC resonant converters. Features SIP9 26x10.5 CASE 127EN MARKING DIAGRAM $Y&Z &3&K XXXXXXXXXX $Y = onsemi Logo &Z = Assembly Plant Code &3 = 3−Digit Date Code &K = 2−Digits Lot Run Traceability Code XXXXXXXXXX= Device Code • Variable Frequency Control with 50% Duty Cycle for Half−Bridge • • • • • • Resonant Converter Topology High Efficiency through Zero Voltage Switching (ZVS) Internal UniFETt with Fast−Recovery Body Diode Fixed Dead Time (350 ns) Optimized for MOSFETs Up to 300 kHz Operating Frequency Auto−Restart Operation for All Protections with External LVCC Protection Functions: Over−Voltage Protection (OVP), Over−Current Protection (OCP), Abnormal Over−Current Protection (AOCP), Internal Thermal Shutdown (TSD) ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. Applications • • • • PDP and LCD TVs Desktop PCs and Servers Adapters Telecom Power Supplies Related Resources AN−4151 − Half−Bridge LLC Resonant Converter Design Using FSFR−Series Power Switch © Semiconductor Components Industries, LLC, 2010 January, 2022 − Rev. 2 1 Publication Order Number: FSFR2100XS/D FSFR−XS Series ORDERING INFORMATION RDS(ON_MAX) Maximum Output Power without Heatsink (VIN = 350~400 V) (Note 1, 2) Maximum Output Power with Heatsink (VIN = 350~400 V) (Note 1, 2) 0.51 W 180 W 400 W FSFR1800XS 0.95 W 120 W 260 W FSFR1700XS 1.25 W 100 W 200 W FSFR1600XS 1.55 W 80 W 160 W 0.51 W 180 W 400 W Part Number FSFR2100XS FSFR2100XSL FSFR1800XSL Package Operating Junction Temperature 9−SIP −40 to +130°C 9−SIP L−Forming 0.95 W 120 W 260 W FSFR1700XSL 1.25 W 100 W 200 W FSFR1600XSL 1.55 W 80 W 160 W 1. The junction temperature can limit the maximum output power. 2. Maximum practical continuous power in an open−frame design at 50°C ambient. APPLICATION CIRCUIT DIAGRAM Cr VIN VCC VO LV CC VDL RMIN RMAX RT RSS CSS AR FSFR−XS Series HVCC VCTR CS SG PG Figure 1. Typical Application Circuit (LLC Resonant Half−Bridge Converter) www.onsemi.com 2 FSFR−XS Series BLOCK DIAGRAM V REF V REF LVCC V DL 7 1 9 HVCC IRT IRT 2I RT 3V S 1V R LVCC good Q V REF Internal Bias LUV+ / LUV− HUV+ / HUV− 2V Time Delay 350 ns RT 3 Level Shifter High−Side Gate Driver 10 VCTR Divider AR 2 Time Delay 350 ns V CssH / V CssL 5k S R LVCC good Q Balancing Delay Low−Side Gate Driver Shutdown TSD LV CC VOVP VAOCP Delay 50 ns 6 PG VOCP Delay 1.5 ms −1 5 SG 4 CS Figure 2. Internal Block Diagram www.onsemi.com 3 FSFR−XS Series PIN CONFIGURATION 1 V DL 2 3 4 5 6 7 8 RT SG LVcc AR CS PG 9 10 V HVcc Figure 3. Package Diagram PIN DESCRIPTION Pin # Name Description 1 VDL This is the drain of the high−side MOSFET, typically connected to the input DC link voltage. 2 AR This pin is for discharging the external soft−start capacitor when any protections are triggered. When the voltage of this pin drops to 0.2 V, all protections are reset and the controller starts to operate again. 3 RT This pin programs the switching frequency. Typically, an opto−coupler is connected to control the switching frequency for the output voltage regulation. 4 CS This pin senses the current flowing through the low−side MOSFET. Typically, negative voltage is applied on this pin. 5 SG This pin is the control ground. 6 PG This pin is the power ground. This pin is connected to the source of the low−side MOSFET. 7 LVCC 8 NC 9 HVCC This is the supply voltage of the high−side gate−drive circuit IC. 10 VCTR This is the drain of the low−side MOSFET. Typically, a transformer is connected to this pin. This pin is the supply voltage of the control IC. No connection. www.onsemi.com 4 FSFR−XS Series ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise specified) Symbol Min Max Unit VDS Maximum Drain−to−Source Voltage (VDL−VCTR and VCTR−PG) 500 − V LVCC Low−Side Supply Voltage −0.3 25.0 V High−Side VCC Pin to Low−Side Drain Voltage −0.3 25.0 V High−Side Floating Supply Voltage −0.3 525.0 V VAR Auto−Restart Pin Input Voltage −0.3 LVCC V VCS Current−Sense (CS) Pin Input Voltage −5.0 1.0 V VRT RT Pin Input Voltage −0.3 5.0 V − 50 V/ns FSFR2100XS/L − 12.0 W FSFR1800XS/L − 11.7 FSFR1700XS/L − 11.6 FSFR1600XS/L − 11.5 − +150 Recommended Operating Junction Temperature (Note 4) −40 +130 Storage Temperature Range −55 +150 °C 500 − V HVCC to VCTR HVCC dVCTR/dt PD Parameter Allowable Low−Side MOSFET Drain Voltage Slew Rate Total Power Dissipation (Note 3) Maximum Junction Temperature (Note 4) TJ TSTG °C MOSFET SECTION VDGR Drain Gate Voltage (RGS = 1 MW) VGS Gate Source (GND) Voltage IDM Drain Current Pulsed (Note 5) ID Continuous Drain Current − ±30 V FSFR2100XS/L − 32 A FSFR1800XS/L − 23 FSFR1700XS/L − 20 FSFR1600XS/L − 18 TC = 25°C − 10.5 TC = 100°C − 6.5 TC = 25°C − 7.0 TC = 100°C − 4.5 TC = 25°C − 6.0 TC = 100°C − 3.9 TC = 25°C − 4.5 TC = 100°C − 2.7 FSFR2100XS/L FSFR1800XS/L FSFR1700XS/L FSFR1600XS/L A PACKAGE SECTION Torque Recommended Screw Torque 5~7 kgf·cm Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3. Per MOSFET when both MOSFETs are conducting. 4. The maximum value of the recommended operating junction temperature is limited by thermal shutdown. 5. Pulse width is limited by maximum junction temperature. www.onsemi.com 5 FSFR−XS Series THERMAL IMPEDANCE (TA = 25°C unless otherwise specified) Symbol qJC qJA Parameter Junction−to−Case Center Thermal Impedance (Both MOSFETs Conducting) Junction−to−Ambient Thermal Impedance Value Unit FSFR2100XS/L 10.44 °C/W FSFR1800XS/L 10.68 FSFR1700XS/L 10.79 FSFR1600XS/L 10.89 FSFR XS Series 80 °C/W ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Test Condition Min Typ Max Unit ID = 200 mA, TA = 25°C 500 − − V ID = 200 mA, TA = 125°C − 540 − FSFR2100XS/L VGS = 10 V, ID = 6.0 A − 0.41 0.51 FSFR1800XS/L VGS = 10 V, ID = 3.0 A − 0.77 0.95 FSFR1700XS/L VGS = 10 V, ID = 2.0 A − 1.00 1.25 FSFR1600XS/L VGS = 10 V, ID = 2.25 A − 1.25 1.55 FSFR2100XS/L VGS = 0 V, IDiode = 10.5 A, dIDiode/dt = 100A/ms − 120 − FSFR1800XS/L VGS = 0 V, IDiode = 7.0 A, dIDiode/dt = 100 A/ms − 160 − FSFR1700XS/L VGS = 0 V, IDiode = 6.0 A, dIDiode/dt = 100 A/ms − 160 − FSFR1600XS/L VGS = 0 V, IDiode = 4.5 A, dIDiode/dt = 100 A/ms − 90 − FSFR2100XS/L VDS = 25 V, VGS = 0 V, f = 1.0 MHz − 1175 − pF − 639 − pF − 512 − pF − 412 − pF − 155 − pF − 82.1 − pF FSFR1700XS/L − 66.5 − pF FSFR1600XS/L − 52.7 − pF MOSFET SECTION BVDSS RDS(ON) trr CISS Drain−to−Source Breakdown Voltage On−State Resistance Body Diode Reverse Recovery Time (Note 6) Input Capacitance (Note 6) FSFR1800XS/L FSFR1700XS/L FSFR1600XS/L COSS Output Capacitance (Note 6) FSFR2100XS/L FSFR1800XS/L VDS = 25 V, VGS = 0 V, f = 1.0 MHz W ns SUPPLY SECTION ILK Offset Supply Leakage Current HVCC = VCTR = 500 V − − 50 mA IQHVCC Quiescent HVCC Supply Current (HVCCUV+) − 0.1 V − 50 120 mA IQLVCC Quiescent LVCC Supply Current (LVCCUV+) − 0.1 V − 100 200 mA IOHVCC Operating HVCC Supply Current (RMS Value) fOSC = 100 kHz − 6 9 mA No Switching − 100 200 mA fOSC = 100 kHz − 7 11 mA No Switching − 2 4 mA IOLVCC Operating LVCC Supply Current (RMS Value) www.onsemi.com 6 FSFR−XS Series ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (continued) Symbol Parameter Test Condition Min Typ Max Unit UVLO SECTION LVCCUV+ LVCC Supply Under−Voltage Positive Going Threshold (LVCC Start) 11.2 12.5 13.8 V LVCCUV− LVCC Supply Under−Voltage Negative Going Threshold (LVCC Stop) 8.9 10.0 11.1 V LVCCUVH LVCC Supply Under−Voltage Hysteresis − 2.50 − V HVCCUV+ HVCC Supply Under−Voltage Positive Going Threshold (HVCC Start) 8.2 9.2 10.2 V HVCCUV− HVCC Supply Under−Voltage Negative Going Threshold (HVCC Stop) 7.8 8.7 9.6 V HVCCUVH HVCC Supply Under−Voltage Hysteresis − 0.5 − V 1.5 2.0 2.5 V OSCILLATOR & FEEDBACK SECTION VRT V−I Converter Threshold Voltage RT = 5.2 kW fOSC Output Oscillation Frequency 94 100 106 kHz DC Output Duty Cycle 48 50 52 % fSS Internal Soft−Start Initial Frequency − 140 − kHz tSS Internal Soft−Start Time 2 3 4 ms fSS = fOSC + 40 kHz, RT = 5.2 kW PROTECTION SECTION VCssH Beginning Voltage to Discharge CSS 0.9 1.0 1.1 V VCssL Beginning Voltage to Charge CSS and Restart 0.16 0.20 0.24 V VOVP LVCC Over−Voltage Protection 21 23 25 V VAOCP AOCP Threshold Voltage −1.0 −0.9 −0.8 V − 50 − ns −0.64 −0.58 −0.52 V 1.0 1.5 2.0 ms − 250 400 ns 120 135 150 °C − 350 − ns tBAO AOCP Blanking Time (Note 6) VOCP OCP Threshold Voltage LVCC > 21 V VCS < VAOCP tBO OCP Blanking Time (Note 6) VCS < VOCP tDA Delay Time (Low Side) Detecting from VAOCP to Switch Off (Note 6) TSD Thermal Shutdown Temperature (Note 6) DEAD−TIME CONTROL SECTION DT Dead Time (Note 7) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. This parameter, although guaranteed, is not tested in production. 7. These parameters, although guaranteed, are tested only in EDS (wafer test) process. www.onsemi.com 7 FSFR−XS Series TYPICAL PERFORMANCE CHARACTERISTICS 1.1 1.1 1.05 1.05 Normalized at 25°C Normalized at 25°C (These characteristic graphs are normalized at TA = 25°C) 1 0.95 0.9 −50 −25 0 25 50 75 1 0.95 0.9 −50 100 −25 0 Temp (°C) 1.05 1.05 Normalized at 25°C Normalized at 25°C 1.1 1 0.95 0 25 50 75 0.95 0.9 −50 100 −25 0 1.05 1.05 Normalized at 25°C Normalized at 25°C 1.1 1 0.95 25 50 50 75 100 Figure 7. High−Side VCC (HVCC) Stop vs. Temperature 1.1 0 25 Temp (°C) Figure 6. High−Side VCC (HVCC) Start vs. Temperature −25 100 1 Temp (°C) 0.9 −50 75 Figure 5. Switching Frequency vs. Temperature 1.1 −25 50 Temp (°C) Figure 4. Low−Side MOSFET Duty Cycle vs. Temperature 0.9 −50 25 75 1 0.95 0.9 −50 100 Temp (°C) −25 0 25 50 75 Temp (°C) Figure 8. Low−Side VCC (LVCC) Start vs. Temperature Figure 9. Low−Side VCC (LVCC) Stop vs. Temperature www.onsemi.com 8 100 FSFR−XS Series TYPICAL PERFORMANCE CHARACTERISTICS (continued) 1.1 1.1 1.05 1.05 Normalized at 25°C Normalized at 25°C (These characteristic graphs are normalized at TA = 25°C) 1 0.95 0.9 −50 −25 0 25 50 75 1 0.95 0.9 −50 100 −25 0 Temp (°C) 1.05 1.05 Normalized at 25°C Normalized at 25°C 1.1 1 0.95 0 25 50 75 0.95 0.9 −50 100 Normalized at 25°C 1.05 1 0.95 25 50 0 25 50 75 Figure 13. VCssH vs. Temperature 1.1 0 −25 Temp (°C) Figure 12. VCssL vs. Temperature −25 100 1 Temp (°C) 0.9 −50 75 Figure 11. RT Voltage vs. Temperature 1.1 −25 50 Temp (°C) Figure 10. LVCC OVP Voltage vs. Temperature 0.9 −50 25 75 100 Temp (°C) Figure 14. OCP Voltage vs. Temperature www.onsemi.com 9 100 FSFR−XS Series FUNCTIONAL DESCRIPTION Gain Basic Operation FSFR−XS series is designed to drive high−side and low−side MOSFETs complementarily with 50% duty cycle. A fixed dead time of 350 ns is introduced between consecutive transitions, as shown in Figure 15. 1.8 f min f normal Low−Side MOSFET Gate Drive 0.6 60 Figure 15. MOSFETs Gate Drive Signal Internal Oscillator + 3V ICTC 1V 2I CTC CT − + − RT AR CS SG To prevent excessive inrush current and overshoot of output voltage during startup, increase the voltage gain of the resonant converter progressively. Since the voltage gain of the resonant converter is inversely proportional to the switching frequency, the soft−start is implemented by sweeping down the switching frequency from an initial high frequency (f ISS) until the output voltage is established. The soft−start circuit is made by connecting R−C series network on the RT pin, as shown in Figure 18. FSFR−XS series also has a 3 ms internal soft−start to reduce the current overshoot during the initial cycles, which adds 40 kHz to the initial frequency of the external soft−start circuit, as shown in Figure 19. The initial frequency of the soft−start is given as: − + Frequency Setting Figure 17 shows the typical voltage gain curve of a resonant converter, where the gain is inversely proportional to the switching frequency in the ZVS region. The output voltage can be regulated by modulating the switching frequency. Figure 18 shows the typical circuit configuration for the RT pin, where the opto−coupler transistor is connected to the RT pin to modulate the switching frequency. The minimum switching frequency is determined as: (eq. 1) f ISS + Assuming the saturation voltage of opto−coupler transistor is 0.2 V, the maximum switching frequency is determined as: ) Ǔ 4.68 kW R max 100 (kHz) PG Figure 18. Frequency Control Circuit Divider 100 (kHz) VDL Css F/F Figure 16. Current−Controlled Oscillator 5.2 kW Rss + R −Q Gate Drive R min Rmin Q 2V 3 5.2 kW 90 100 110 120 130 140 150 Frequency (kHz) LV CC Rmax S 80 FSFR−XS I CTC V REF 70 Figure 17. Resonant Converter Typical Gain Curve FSFR−XS series employs a current−controlled oscillator, as shown in Figure 16. Internally, the voltage of RT pin is regulated at 2 V and the charging / discharging current for the oscillator capacitor, CT, is obtained by copying the current flowing out of the RT pin (ICTC) using a current mirror. Therefore, the switching frequency increases as ICTC increases. R min Soft−Start 0.8 Time ǒ ISS 1.2 1.0 f max + f 1.4 High−Side MOSFET Gate Drive f min + max 1.6 Dead−Time RT f (eq. 2) www.onsemi.com 10 ǒ 5.2 kW R min ) 5.2 kW R SS Ǔ 100 ) 40 (kHz) (eq. 3) FSFR−XS Series (a) It is typical to set the initial frequency of soft−start two to three times the resonant frequency (fO ) of the resonant network. The soft−start time is three to four times the RC time constant. The RC time constant is: t + R SS @ C SS (b) (a) (b) (a) (b) LVCC V AR VCssH VCssL (eq. 4) I Cr fs f ISS t stop 40 kHz t S/S (a) Protections are triggered, (b) FSFR−US restarts Control Loop Take Over Figure 21. Self Auto−Restart Operation Protection Circuits The FSFR−XS series has several self−protective functions, such as Over−Current Protection (OCP), Abnormal Over−Current Protection (AOCP), Over−Voltage Protection (OVP), and Thermal Shutdown (TSD). These protections are auto−restart mode protections, as shown in Figure 22. Once a fault condition is detected, switching is terminated and the MOSFETs remain off. When LVCC falls to the LVCC stop voltage of 10 V or AR signal is HIGH, the protection is reset. The FSFR−XS resumes normal operation when LVCC reaches the start voltage of 12.5 V. Time Figure 19. Frequency Sweeping of Soft−Start Self Auto−Restart The FSFR−XS series can restart automatically even though any built−in protections are triggered with external supply voltage. As can be seen in Figure 20 and Figure 21, once any protections are triggered, the M1 switch turns on and the V−I converter is disabled. CSS starts to discharge until VCss across CSS drops to VCssL. Then, all protections are reset, M1 turns off, and the V−I converter resumes at the same time. The FSFR−XS starts switching again with soft−start. If the protections occur while VCss is under VCssL and VCssH level, the switching is terminated immediately, VCss continues to increase until reaching VCssH, then CSS is discharged by M1. LVCC 7 + LVCC good − 10 / 12.5 V Auto−Restart Protection OCP AOCP OVP S Q LVCC good RT 2V ‘H’ = disable AR 2 3 R min R ss Css VCssH / VCssL Switching Shutdown R −Q TSD + − Internal Bias VREF + − F/F AR Signal V−I Converter AR 2 5k VCssH / VCssL + − Figure 22. Protection Blocks Switching Shutdown M1 LVCC good OVP OCP AOCP TSD R S Over−Current Protection (OCP) When the sensing pin voltage drops below −0.58 V, OCP is triggered and the MOSFETs remain off. This protection has a shutdown time delay of 1.5 ms to prevent premature shutdown during startup. Q Abnormal Over−Current Protection (AOCP) If the secondary rectifier diodes are shorted, large current with extremely high di/dt can flow through the MOSFET before OCP is triggered. AOCP is triggered without shutdown delay if the sensing pin voltage drops below −0.9 V. Figure 20. Internal Block of AR Pin After protections trigger, FSFR−XS is disabled during the stop−time, tstop, where VCss decreases and reaches to VCssL. The stop−time of FSFR−XS can be estimated as: t STOP + C SS @ {(R SS ) R MIN) ø 5 kW} Over−Voltage Protection (OVP) When the LVCC reaches 23 V, OVP is triggered. This protection is used when auxiliary winding of the transformer to supply VCC to the power switch is utilized. (eq. 5) The soft−start time, ts/s can be set as Equation (4). www.onsemi.com 11 FSFR−XS Series PCB Layout Guidelines Thermal Shutdown (TSD) The MOSFETs and the control IC in one package makes it easier for the control IC to detect the abnormal over−temperature of the MOSFETs. If the temperature exceeds approximately 130°C, thermal shutdown triggers. Duty imbalance problems may occur due to the radiated noise from the main transformer, the inequality of the secondary side leakage inductances of main transformer, and so on. This is one of the reasons that the control components in the vicinity of RT pin are enclosed by the primary current flow pattern on PCB layout. The direction of the magnetic field on the components caused by the primary current flow is changed when the high− and low−side MOSFET turn on by turns. The magnetic fields with opposite directions induce a current through, into, or out of the RT pin, which makes the turn−on duration of each MOSFET different. It is strongly recommended to separate the control components in the vicinity of RT pin from the primary current flow pattern on PCB layout. Figure 25 shows an example for the duty−balanced case. Current Sensing Using a Resistor FSFR−XS series senses drain current as a negative voltage, as shown in Figure 23 and Figure 24. Half−wave sensing allows low power dissipation in the sensing resistor, while full−wave sensing has less switching noise in the sensing signal. Cr Ns Np + Ns Control IC V CS Ids CS SG PG R sense − + V CS Ids Figure 23. Half−Wave Sensing Figure 25. Example for Duty Balancing I ds V CS + Cr Control IC V CS Np CS PG SG Ns R sense Ids + Ns − Figure 24. Full−Wave Sensing UniFET is trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. www.onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SIP9 26x10.5 CASE 127EM ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON13718G SIP9 26x10.5 DATE 31 DEC 2016 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SIP9 26x10.5 CASE 127EN ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON13719G SIP9 26x10.5 DATE 31 DEC 2016 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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