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FSUSB104UMX

FSUSB104UMX

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    UFQFN10

  • 描述:

    USB Switch IC 1 Channel 10-UMLP (1.8x1.4)

  • 数据手册
  • 价格&库存
FSUSB104UMX 数据手册
Features    Description Low On Capacitance: 3.7 pF Typical Low On Resistance: 3.9 Ω Typical Low Pow er Consumption: 1 μA Maximum - 15 μA Maximum ICCT over an Expanded Voltage Range (V IN=1.8 V, V CC=4.3 V)     Wide -3 db Bandw idth: > 720 MHz Packaged in Pb-free 10-Lead UMLP (1.4 x 1.8 mm) 8 kV ESD Rating, >16 kV Pow er/GND ESD Rating Pow er-Off Protection on All Ports When V CC=0 V - D+/D- Pins Tolerate up to 5.25 V Applications   Cell phone, PDA, Digital Camera, and Notebook LCD Monitor, TV, and Set-Top Box The FSUSB104 is a bi-directional, low -pow er, tw o-port, Hi-Speed, USB2.0 sw itch. Configured as a double-pole, double-throw sw itch (DPDT) sw itch, it is optimized for sw itching betw een tw o Hi-Speed (480 Mbps) sources or a Hi-Speed and Full-Speed (12 Mbps) source. The FSUSB104 is compatible w ith the requirements of USB2.0 and features an extremely low on capacitance (CON) of 3.7 pF. The w ide bandw idth of this device (720 MHz) exceeds the bandw idth needed to pass the third harmonic, resulting in signals w ith minimum edge and phase distortion. Superior channel-to-channel crosstalk also minimizes interference. The FSUSB104 contains special circuitry on the sw itch I/O pins for applications w here the V CC supply is pow ered-off (V CC=0), w hich allow s the device to w ithstand an over-voltage condition. This device is designed to minimize current consumption even w hen the control voltage applied to the SEL pin is low er than the supply voltage (V CC). This feature is especially valuable to ultra-portable applications, such as cell phones, allow ing for direct interface w ith the generalpurpose I/Os of the baseband processor. Other applications include sw itching and connector sharing in portable cell phones, PDAs, digital cameras, printers, and notebook computers. Ordering Information Part Number Top Mark Operating Temperature Range FSUSB104UMX JF -40 to +85°C Package 10-Lead, Quad, Ultrathin Molded Leadless Package (UMLP), 1.4 x 1.8 mm HSD1+ D+ HSD2+ HSD1- D- HSD2Sel Control /OE Figure 1. Analog Sym bol © 2008 Semiconductor Components Industries, LLC. November-2017, Rev. 2 Publication Order Number: FSUSB104/D FSUSB104 — Low-Power, Two-Port, Hi-Speed, USB2.0 (480 Mbps) Switch FSUSB104 — Low-Power, Two-Port, Hi-Speed, USB2.0 (480 Mbps) Switch GN D 3 HSD2- 4 HSD2+ 5 D- D+ 2 1 6 10 Sel 9 VCC 8 /OE 7 HSD1- HSD1+ Figure 2. Pin Assignm ent (Top Through View ) Pin Definitions Pin # Name Description 1 D+ USB Data Bus 2 D- USB Data Bus 3 GND 4 HSD2- Ground Multiplexed Source Inputs 5 HSD2+ Multiplexed Source Inputs 6 HSD1- Multiplexed Source Inputs 7 HSD1+ Multiplexed Source Inputs 8 /OE Sw itch Enable 9 V CC Supply Voltage 10 Sel Sw itch Select Truth Table Sel /OE Function X HIGH Disconnect LOW LOW D+, D-=HSD1+, HSD1- HIGH LOW D+, D-=HSD2+, HSD2- www.onsemi.com 2 FSUSB104 — Low-Power, Two-Port, Hi-Speed, USB2.0 (480 Mbps) Switch Pin Assignments Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol V CC V CNTRL Parameter Supply Voltage DC Input Voltage (S, /OE) (1) (1) Min. Max. Unit -0.5 5.6 V -0.5 V CC V 5.25 V V SW DC Sw itch I/O Voltage -0.5 IIK DC Input Diode Current -50 IOUT DC Output Current TSTG Storage Temperature ESD -65 Human Body Model, JEDEC: JESD22-A114 mA 50 mA +150 °C All Pins 7 I/O to GND 8 Pow er to GND 16 Charged Device Model, JEDEC: JESD22-C101 kV 2 Note: 1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol V CC V CNTRL V SW TA Parameter Min. Max. Unit 3.0 4.4 V 0 V CC V Sw itch I/O Voltage -0.5 4.5 V Operating Temperature -40 +85 °C Supply Voltage Control Input Voltage (S, /OE) (2) Note: 2. The control input must be held HIGH or LOW and it must not float. www.onsemi.com 3 FSUSB104 — Low-Power, Two-Port, Hi-Speed, USB2.0 (480 Mbps) Switch Absolute Maximum Ratings All typical values are at 25°C unless otherw ise specified. Symbol Parameter V IK Clamp Diode Voltage V IH Input Voltage High Conditions IIN=-18 mA VCC (V) TA=- 40ºC to +85ºC Min. Typ. 3.0 Max. -1.2 Units V 3.0 to 3.6 1.3 V 4.3 1.7 V 3.0 to 3.6 0.5 V 4.3 0.7 V -1 1 µA 4.3 -2 2 µA 0 -2 2 µA 6.5 Ω V IL Input Voltage Low IIN Control Input Leakage V SW=0 to V CC 4.3 IOZ Off State Leakage 0 ≤ Dn, HSD1n, HSD2n ≤ 3.6V IOFF Pow er-Off Leakage Current (All I/O Ports) V SW=0 V to 4.3 V, V CC=0 V Figure 4 RON HS Sw itch On Resistance 3 ∆RON V SW=0.4 V, ION=-8 mA Figure 3, 3.0 3.9 HS Delta Ron 4 V SW=0.4 V, ION=-8 mA 3.0 0.65 ICC Quiescent Supply Current V CNTRL=0 or V CC, IOUT=0 4.3 1.0 µA ICCT Increase in ICC Current per Control Voltage and V CC V CNTRL =2.6 V, V CC=4.3 V 4.3 10.0 µA V CNTRL =1.8 V, V CC=4.3 V 4.3 15.0 µA ( ) ( ) Ω Notes: 3. Measured by the voltage drop betw een HSDn and Dn pins at the indicated current through the sw itch. On resistance is determined by the low er of the voltage on the tw o (HSDn or Dn ports). 4. Guaranteed by characterization. Not tested in production. www.onsemi.com 4 FSUSB104 — Low-Power, Two-Port, Hi-Speed, USB2.0 (480 Mbps) Switch DC Electrical Characteristics All typical value are for V CC=3.3 V at 25°C unless otherw ise specified. Symbol Parameter Conditions VCC (V) TA=- 40ºC to +85ºC Min. Typ. Max. Units tON Turn-On Time S, /OE to Output RL=50 Ω, CL=5 pF V SW=0.8 V Figure 5, Figure 6 3.0 to 3.6 13 30 ns tOFF Turn-Off Time S, /OE to Output RL=50 Ω, CL=5 pF V SW=0.8 V Figure 5, Figure 6 3.0 to 3.6 12 25 ns tPD Propagation Delay 5 CL=5 pF, RL=50 Ω Figure 5, Figure 7 3.3 0.25 tBBM Break-Before-Make RL=50 Ω, CL=5 pF V SW1=V SW2=0.8 V Figure 9 3.0 to 3.6 OIRR Off Isolation RL=50 Ω, f=240 MHz Figure 11 3.0 to 3.6 -30 dB Xtalk Non-Adjacent Channel Crosstalk RL=50 Ω, f=240 MHz Figure 12 3.0 to 3.6 -45 dB 720 MHz 550 MHz BW ( ) -3db Bandw idth RL=50 Ω, CL=0 pF Figure 10 RL=50 Ω, CL=5 pF Figure 10 2.0 ns 6.5 ns 3.0 to 3.6 Note: 5. Guaranteed by characterization. Not tested in production. USB Hi-Speed-Related AC Electrical Characteristics Symbol tSK(P) tJ Parameter Skew of Opposite Transitions (6) of the Same Output Total Jitter (6) Conditions Vcc (V) TA=- 40ºC to +85ºC Min. Typ. Max. Units CL=5 pF, RL=50 Ω Figure 8 3.0 to 3.6 20 ps RL=50 Ω, CL=5 pf, tR=tF=500ps (10-90%) at 480 Mbps 15 (PRBS=2 – 1) 3.0 to 3.6 200 ps Note: 6. Guaranteed by characterization. Not tested in production. Capacitance Symbol Parameter Conditions TA=- 40ºC to +85ºC Min. Typ. CIN Control Pin Input Capacitance V CC=0 V 1.5 CON D+/D- On Capacitance V CC=3.3 V, /OE=0 V, f=240 MHz Figure 14 3.7 COFF D1n, D2n Off Capacitance V CC and /OE=3.3 V See Figure 13 2.0 www.onsemi.com 5 Max. Units pF FSUSB104 — Low-Power, Two-Port, Hi-Speed, USB2.0 (480 Mbps) Switch AC Electrical Characteristics VON I Dn(OFF) NC A HSDn VSW Dn VSW Select GND I ON GND Select R ON = VON / ION V Sel = V Sel = GND **Each switch port is tested separately 0 orV cc Figure 3. On Resistance HSDn Figure 4. Off Leakage tFALL = 2.5ns tRISE = 2.5ns Dn VSW RL CL GND RS V cc 0 orV VCC V OUT Input – V/OE , VSel GND V Sel 90% VCC /2 VCC /2 10% GND 90% 10% VOH 90% GND 90% Output- VOUT RL , RS , and C L are functions of the application environment (see AC Tables for specific values) CL includes test fixture and stray capacitance. Figure 5. AC Test Circuit Load VOL tON tOFF Figure 6. Turn-On / Turn-Off Waveform s tRISE = 500ps 50% Input 400mV +400mV tPHL - 400mV 90% 0V 50% 0V tPLH 10% tFALL = 500ps 90% 10% VOH Output 50% 50% VOL Output t PHL Figure 7. Propagation Delay (t Rt F – 500 ps) t PLH Figure 8. Intra-Pair Skew Test t SK(P) www.onsemi.com 6 FSUSB104 — Low-Power, Two-Port, Hi-Speed, USB2.0 (480 Mbps) Switch Test Diagrams (Continued) tRISE = 2.5ns Vcc HSDn Dn VSW1 GND 10% 0V VOUT CL VSW2 90% Vcc/2 Input - VSel RL V OUT GND GND 0.9*Vout 0.9*Vout RS tBBM V Sel RL , RS , and C L are functions of the application environment (see AC Tables for specific values) CL includes test fixture and stray capacitance. GND Figure 9. Break-Before-Make Interval Tim ing Network Analyzer Network Analyzer RS RS V IN VS GND GND VSel GND VSel VOUT GND VS GND V OUT GND RS and RT are functions of the application environment (see AC Tables for specific values). GND V IN GND GND RT RS and RT are functions of the application environment (see AC Tables for specific values). GND RT RT GND Off isolation = 20 Log (V OUT / VIN) Figure 10. Bandw idth Figure 11. Channel Off Isolation Network Analyzer NC RS V IN GND VS VSel GND GND RT GND GND RS and RT are functions of the application environment (see AC Tables for specific values). V OUT RT GND Crosstalk = 20 Log (VOUT / VIN) Figure 12. Non-Adjacent Channel-to-Channel Crosstalk HSDn S Capacitance Meter HSDn Capacitance Meter S VSel = 0 or Vcc V Sel = 0 or Vcc HSDn HSDn Figure 13. Channel Off Capacitance Figure 14. www.onsemi.com 7 Channel On Capacitance FSUSB104 — Low-Power, Two-Port, Hi-Speed, USB2.0 (480 Mbps) Switch Test Diagrams 1.40 0.05 C A B 2X 1.80 (9X) 1.70 PIN#1 IDENT 0.563 0.663 0.05 C TOP VIEW 2X 1 2.10 0.50±.05 0.10 C 0.15±.05 0.40 (10X) 0.225 0.08 C SEATING C PLANE 0.025±.025 RECOMMENDED LAND PATTERN SIDE VIEW 1.45 0.55 9X 0.45 1.40±.05 (0.20) 4X 0.40±.05 (9X) 3 0.40 6 DETAIL A 1.80±.05 1 (0.60) 4X PIN#1 IDENT 10 0.20±.05 (10X) BOTTOM VIEW 0.10 C A B 0.05 C (10X) 0.225 OPTIONAL MINIMIAL TOE LAND PATTERN NOTES: A. PACKAGE DOES NOT CONFORM TO ANY JEDEC STANDARD. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009. 1.00±.05 D. LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN. 45° 0.40±.05 E. DRAWING FILENAME: MKT-UMLP10Arev6. DETAIL A SCALE : 2X PACKAGE EDGE LEAD OPTION 1 SCALE : 2X 1.85 0.40 LEAD OPTION 2 SCALE : 2X Figure 15. 10-Lead, Ultrathin Molded Leadless Package (UMLP) www.onsemi.com 8 FSUSB104 — Low-Power, Two-Port, Hi-Speed, USB2.0 (480 Mbps) Switch Physical Dimensions FSUSB104 — Low-Power, Two-Port, Hi-Speed, USB2.0 (480 Mbps) Switch ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax : 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. Amer ican Technical Support: 800-282-9855 Toll Free USA/Canada. Eur ope, Middle East and Afr ica Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5817-1050 www.onsemi.com 9 ON Semiconductor Website: www.onsemi.com Or der Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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