J309G

J309, J310 Preferred Device JFET VHF/UHF Amplifiers N−Channel — Depletion Features • Pb−Free Packages are Available* http://onsemi.com 1 DRAIN MAXIMUM RATINGS Rating Symbol Value Unit Drain −Source Voltage VDS 25 Vdc Gate −Source Voltage VGS 25 Vdc Forward Gate Current IGF 10 mAdc Total Device Dissipation @ TA = 25°C Derate above = 25°C PD 350 2.8 mW mW/°C Junction Temperature Range TJ −65 to +125 °C Storage Temperature Range Tstg −65 to +150 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 3 GATE 2 SOURCE TO−92 CASE 29−11 STYLE 5 1 2 3 MARKING DIAGRAM J3xx AYWW G G J3xx = Device Code xx = 09 or 10 A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 1 1 Preferred devices are recommended choices for future use and best overall value. Publication Order Number: J309/D J309, J310 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)GSS −25 − − Vdc − − − − −1.0 −1.0 nAdc mAdc −1.0 −2.0 − − −4.0 −6.5 12 24 − − 30 60 − − 1.0 − − 0.7 0.5 − − OFF CHARACTERISTICS Gate −Source Breakdown Voltage (IG = −1.0 mAdc, VDS = 0) Gate Reverse Current (VGS = −15 Vdc, VDS = 0, TA = 25°C) (VGS = −15 Vdc, VDS = 0, TA = +125°C) IGSS Gate Source Cutoff Voltage (VDS = 10 Vdc, ID = 1.0 nAdc) VGS(off) J309 J310 Vdc ON CHARACTERISTICS Zero −Gate −Voltage Drain Current(1) (VDS = 10 Vdc, VGS = 0) IDSS J309 J310 Gate−Source Forward Voltage (VDS = 0, IG = 1.0 mAdc) VGS(f) mAdc Vdc SMALL− SIGNAL CHARACTERISTICS Common−Source Input Conductance (VDS = 10 Vdc, ID = 10 mAdc, f = 100 MHz) Re(yis) J309 J310 mmhos Common−Source Output Conductance (VDS = 10 Vdc, ID = 10 mAdc, f = 100 MHz) Re(yos) − 0.25 − mmhos Common−Gate Power Gain (VDS = 10 Vdc, ID = 10 mAdc, f = 100 MHz) Gpg − 16 − dB Common−Source Forward Transconductance (VDS = 10 Vdc, ID = 10 mAdc, f = 100 MHz) Re(yfs) − 12 − mmhos Common−Gate Input Conductance (VDS = 10 Vdc, ID = 10 mAdc, f = 100 MHz) Re(yig) − 12 − mmhos 10000 8000 − − 20000 18000 − − 250 − − 13000 12000 − − − − 100 150 − − Common−Source Forward Transconductance (VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) mmhos gfs J309 J310 Common−Source Output Conductance (VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) gos Common−Gate Forward Transconductance (VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) mmhos gfg J309 J310 Common−Gate Output Conductance (VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) mmhos gog J309 J310 mmhos Gate−Drain Capacitance (VDS = 0, VGS = −10 Vdc, f = 1.0 MHz) Cgd − 1.8 2.5 pF Gate−Source Capacitance (VDS = 0, VGS = −10 Vdc, f = 1.0 MHz) Cgs − 4.3 5.0 pF en − 10 − nVń ǸHz FUNCTIONAL CHARACTERISTICS Equivalent Short−Circuit Input Noise Voltage (VDS = 10 Vdc, ID = 10 mAdc, f = 100 Hz) 1. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 3.0%. http://onsemi.com 2 J309, J310 ORDERING INFORMATION Device Shipping † Package J309 TO−92 J309G 1000 Units / Bulk TO−92 (Pb−Free) J310 TO−92 J310G 1000 Units / Bulk TO−92 (Pb−Free) J310RLRP TO−92 J310RLRPG 2000 Units / Tape & Ammo Box TO−92 (Pb−Free) J310ZL1 TO−92 J310ZL1G 2000 Units / Tape & Ammo Box TO−92 (Pb−Free) I D , DRAIN CURRENT (mA) 60 60 VDS = 10 V TA = −55°C 50 40 50 +25 °C IDSS +25 °C 40 30 20 10 −5.0 +150°C 20 +25 °C −55 °C 30 +150°C 10 −1.0 −4.0 −3.0 −2.0 ID − VGS, GATE−SOURCE VOLTAGE (VOLTS) IDSS − VGS, GATE−SOURCE CUTOFF VOLTAGE (VOLTS) 0 0 Yfs , FORWARD TRANSCONDUCTANCE (mmhos) 70 70 IDSS, SATURATION DRAIN CURRENT (mA) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 35 30 TA = −55°C VDS = 10 V f = 1.0 MHz +25 °C 25 20 +150°C 15 +25 °C −55 °C 10 +150°C 5.0 0 5.0 4.0 3.0 2.0 1.0 VGS, GATE−SOURCE VOLTAGE (VOLTS) Figure 1. Drain Current and Transfer Characteristics versus Gate−Source Voltage Figure 2. Forward Transconductance versus Gate−Source Voltage http://onsemi.com 3 0 10 1.0 k 10 k 100 VGS(off) = −2.3 V = VGS(off) = −5.7 V = 1.0 k Yos 10 RDS CAPACITANCE (pF) Yfs Yfs 120 96 7.0 72 Cgs 4.0 48 24 Cgd 1.0 1.0 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 ID, DRAIN CURRENT (mA) 100 0.01 0 10 4.0 3.0 2.0 |S21|, |S11| |S12|, |S22| 0.85 0.45 0.060 1.00 2.4 0.79 0.39 Y11 1.8 Y21 12 1.2 0.73 0.33 0.048 0.98 VDS = 10 V ID = 10 mA TA = 25°C 0.024 0.94 S11 Y22 0.61 0.21 0.6 200 300 500 f, FREQUENCY (MHz) 700 q21, q11 180° 50° 0.012 0.92 S12 0.55 0.15 100 1000 q22 200 300 500 f, FREQUENCY (MHz) q11, q12 −20 ° 120° −40 ° 86° −40 ° 100° 85° −60 ° 80° −120 ° 84° −80 ° 60° 0 q11 q21 −20 ° q22 −60 ° −80 ° 30° −40 ° −100 ° 20° q12 q11 140° 130° 10° 0° 100 −140 ° VDS = 10 V ID = 10 mA TA = 25°C 200 300 500 f, FREQUENCY (MHz) q21 −60 ° q12 −160 ° 83° −100 ° 40° −180 ° 700 0.90 q21, q22 −20 ° q21 700 1000 Figure 6. Common−Gate S Parameter Magnitude versus Frequency q12, q22 −2 0° 87° 40° 0.036 0.96 0.67 0.27 Figure 5. Common−Gate Y Parameter Magnitude versus Frequency 150° 0 0 1.0 3.0 Y12 160° 5.0 S21 6.0 170° 6.0 S22 VDS = 10 V ID = 10 mA TA = 25°C 18 0 100 7.0 Figure 4. On Resistance and Junction Capacitance versus Gate−Source Voltage Y12 (mmhos) |Y11|, |Y21 |, |Y22 | (mmhos) 24 8.0 VGS, GATE SOURCE VOLTAGE (VOLTS) Figure 3. Common−Source Output Admittance and Forward Transconductance versus Drain Current 30 9.0 −200 ° 82° 1000 −120 ° 20° 100 Figure 7. Common−Gate Y Parameter Phase−Angle versus Frequency VDS = 10 V ID = 10 mA TA = 25°C 200 300 500 f, FREQUENCY (MHz) q11 700 −80 ° −100 ° 1000 Figure 8. S Parameter Phase−Angle versus Frequency http://onsemi.com 4 R DS , ON RESISTANCE (OHMS) 100 k Yos, OUTPUT ADMITTANCE (μ mhos) Yfs , FORWARD TRANSCONDUCTANCE μ ( mhos) J309, J310 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−92 (TO−226) CASE 29−11 ISSUE AM SCALE 1:1 1 12 3 STRAIGHT LEAD BULK PACK DATE 09 MAR 2007 2 3 BENT LEAD TAPE & REEL AMMO PACK A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. STRAIGHT LEAD BULK PACK R P L SEATING PLANE K DIM A B C D G H J K L N P R V D X X G J H V C SECTION X−X N 1 INCHES MIN MAX 0.175 0.205 0.170 0.210 0.125 0.165 0.016 0.021 0.045 0.055 0.095 0.105 0.015 0.020 0.500 --0.250 --0.080 0.105 --0.100 0.115 --0.135 --- MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.407 0.533 1.15 1.39 2.42 2.66 0.39 0.50 12.70 --6.35 --2.04 2.66 --2.54 2.93 --3.43 --- N A R NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. BENT LEAD TAPE & REEL AMMO PACK B P T SEATING PLANE G K DIM A B C D G J K N P R V D X X J V 1 C N SECTION X−X MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.40 0.54 2.40 2.80 0.39 0.50 12.70 --2.04 2.66 1.50 4.00 2.93 --3.43 --- STYLES ON PAGE 2 DOCUMENT NUMBER: STATUS: 98ASB42022B ON SEMICONDUCTOR STANDARD NEW STANDARD: © Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 − Rev. 0 TO−92 (TO−226) http://onsemi.com 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. Case Outline Number: PAGE 1 OFXXX 3 TO−92 (TO−226) CASE 29−11 ISSUE AM DATE 09 MAR 2007 STYLE 1: PIN 1. EMITTER 2. BASE 3. COLLECTOR STYLE 2: PIN 1. BASE 2. EMITTER 3. COLLECTOR STYLE 3: PIN 1. ANODE 2. ANODE 3. CATHODE STYLE 4: PIN 1. CATHODE 2. CATHODE 3. ANODE STYLE 5: PIN 1. DRAIN 2. SOURCE 3. GATE STYLE 6: PIN 1. GATE 2. SOURCE & SUBSTRATE 3. DRAIN STYLE 7: PIN 1. SOURCE 2. DRAIN 3. GATE STYLE 8: PIN 1. DRAIN 2. GATE 3. SOURCE & SUBSTRATE STYLE 9: PIN 1. BASE 1 2. EMITTER 3. BASE 2 STYLE 10: PIN 1. CATHODE 2. GATE 3. ANODE STYLE 11: PIN 1. ANODE 2. CATHODE & ANODE 3. CATHODE STYLE 12: PIN 1. MAIN TERMINAL 1 2. GATE 3. MAIN TERMINAL 2 STYLE 13: PIN 1. ANODE 1 2. GATE 3. CATHODE 2 STYLE 14: PIN 1. EMITTER 2. COLLECTOR 3. BASE STYLE 15: PIN 1. ANODE 1 2. CATHODE 3. ANODE 2 STYLE 16: PIN 1. ANODE 2. GATE 3. CATHODE STYLE 17: PIN 1. COLLECTOR 2. BASE 3. EMITTER STYLE 18: PIN 1. ANODE 2. CATHODE 3. NOT CONNECTED STYLE 19: PIN 1. GATE 2. ANODE 3. CATHODE STYLE 20: PIN 1. NOT CONNECTED 2. CATHODE 3. ANODE STYLE 21: PIN 1. COLLECTOR 2. EMITTER 3. BASE STYLE 22: PIN 1. SOURCE 2. GATE 3. DRAIN STYLE 23: PIN 1. GATE 2. SOURCE 3. DRAIN STYLE 24: PIN 1. EMITTER 2. COLLECTOR/ANODE 3. CATHODE STYLE 25: PIN 1. MT 1 2. GATE 3. MT 2 STYLE 26: PIN 1. VCC 2. GROUND 2 3. OUTPUT STYLE 27: PIN 1. MT 2. SUBSTRATE 3. MT STYLE 28: PIN 1. CATHODE 2. ANODE 3. GATE STYLE 29: PIN 1. NOT CONNECTED 2. ANODE 3. CATHODE STYLE 30: PIN 1. DRAIN 2. GATE 3. SOURCE STYLE 31: PIN 1. GATE 2. DRAIN 3. SOURCE STYLE 32: PIN 1. BASE 2. COLLECTOR 3. EMITTER STYLE 33: PIN 1. RETURN 2. INPUT 3. OUTPUT STYLE 34: PIN 1. INPUT 2. GROUND 3. LOGIC STYLE 35: PIN 1. GATE 2. COLLECTOR 3. EMITTER DOCUMENT NUMBER: STATUS: 98ASB42022B ON SEMICONDUCTOR STANDARD NEW STANDARD: © Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 − Rev. 0 TO−92 (TO−226) http://onsemi.com 2 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. Case Outline Number: PAGE 2 OFXXX 3 DOCUMENT NUMBER: 98ASB42022B PAGE 3 OF 3 ISSUE AM REVISION ADDED BENT−LEAD TAPE & REEL VERSION. REQ. BY J. SUPINA. DATE 09 MAR 2007 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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