KAI-04050-FBA-JB-X2-T

KAI-04050 2336 (H) x 1752 (V) Interline CCD Image Sensor Description The KAI−04050 Image Sensor is a 4-megapixel CCD in a 1” optical format. Based on the TRUESENSE 5.5 micron Interline Transfer CCD Platform, the sensor features broad dynamic range, excellent imaging performance, and a flexible readout architecture that enables use of 1, 2, or 4 outputs. The sensor supports full resolution readout up to 32 frames per second, while a Region of Interest (ROI) mode enables partial readout of the sensor at even higher frame rates. A vertical overflow drain structure suppresses image blooming and enables electronic shuttering for precise exposure control. www.onsemi.com Table 1. GENERAL SPECIFICATIONS Parameter Typical Value Architecture Interline CCD, Progressive Scan Total Number of Pixels 2404 (H) × 1800 (V) Number of Effective Pixels 2360 (H) × 1776 (V) Number of Active Pixels 2336 (H) × 1752 (V) Pixel Size 5.5 mm (H) × 5.5 mm (V) Active Image Size 12.85 mm (H) × 9.64 mm (V), 16.06 mm (Diagonal), 1″ Optical Format Aspect Ratio 4:3 Number of Outputs 1, 2, or 4 Charge Capacity 20,000 electrons Output Sensitivity 34 mV/e− Quantum Efficiency Pan (−ABA, −QBA, −PBA) R, G, B (−FBA, −QBA) R, G, B (−CBA, −PBA) 44% 31%, 37%, 38% 29%, 37%, 39% Read Noise (f = 40 MHz) 12 e− rms Dark Current Photodiode VCCD 7 e−/s 100 e−/s Dark Current Doubling Temp. Photodiode VCCD 7°C 9°C Dynamic Range 64 dB Charge Transfer Efficiency 0.999999 Blooming Suppression > 300 X Smear −100 dB Image Lag < 10 electrons Maximum Pixel Clock Speed 40 MHz Maximum Frame Rate Quad Output Dual Output Single Output 32 fps 16 fps 8 fps Package 68 Pin PGA Cover Glass AR Coated, 2 Sides or Clear Glass Figure 1. KAI−04050 Interline CCD Image Sensor Features • Bayer Color Pattern, TRUESENSE Sparse • • • • • • • Color Filter Pattern, and Monochrome Configurations Progressive Scan Readout Flexible Readout Architecture High Frame Rate High Sensitivity Low Noise Architecture Excellent Smear Performance Package Pin Reserved for Device Identification Application • Industrial Imaging • Medical Imaging • Security ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. NOTE: All Parameters are specified at T = 40°C unless otherwise noted. © Semiconductor Components Industries, LLC, 2014 February, 2017 − Rev. 6 1 Publication Order Number: KAI−04050/D KAI−04050 The sensor is available with the TRUESENSE Sparse Color Filter Pattern, a technology which provides a 2x improvement in light sensitivity compared to a standard color Bayer part. The sensor shares common pin-out and electrical configurations with other devices based on the TRUESENSE 5.5 micron Interline Transfer CCD Platform, allowing a single camera design to support multiple members of this sensor family. ORDERING INFORMATION Table 2. ORDERING INFORMATION − KAI−04050 IMAGE SENSOR Part Number Description KAI−04050−AAA−JP−BA Monochrome, No Microlens, PGA Package, Taped Clear Cover Glass, No Coatings, Standard Grade KAI−04050−AAA−JP−AE Monochrome, No Microlens, PGA Package, Taped Clear Cover Glass, No Coatings, Engineering Grade KAI−04050−ABA−JD−BA Monochrome, Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Standard Grade KAI−04050−ABA−JD−AE Monochrome, Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade KAI−04050−ABA−JP−BA Monochrome, Telecentric Microlens, PGA Package, Taped Clear Cover Glass, No Coatings, Standard Grade KAI−04050−ABA−JP−AE Monochrome, Telecentric Microlens, PGA Package, Taped Clear Cover Glass, No Coatings, Engineering Grade KAI−04050−FBA−JD−BA Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Standard Grade KAI−04050−FBA−JD−AE Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade KAI−04050−FBA−JB−B2 Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass (No Coatings), Grade 2 KAI−04050−FBA−JB−AE Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass (No Coatings), Engineering Grade KAI−04050−FBA−JB−B2−T Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass (No Coatings), Grade 2, Packed in Trays KAI−04050−QBA−JD−BA Gen2 Color (TRUESENSE Sparse CFA), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Standard Grade KAI−04050−QBA−JD−AE Gen2 Color (TRUESENSE Sparse CFA), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade KAI−04050−CBA−JD−BA* Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Standard Grade KAI−04050−CBA−JD−AE* Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade KAI−04050−CBA−JB−B2* Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass (No Coatings), Grade 2 KAI−04050−CBA−JB−AE* Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass (No Coatings), Engineering Grade KAI−04050−CBA−JB−B2−T* Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass (No Coatings), Grade 2, Packed in Trays KAI−04050−PBA−JD−BA* Gen1 Color (TRUESENSE Sparse CFA), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Standard Grade KAI−04050−PBA−JD−AE* Gen1 Color (TRUESENSE Sparse CFA), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade Marking Code KAI−04050−AAA Serial Number KAI−04050−ABA Serial Number KAI−04050−FBA Serial Number KAI−04050−QBA Serial Number KAI−04050−CBA Serial Number KAI−04050−PBA Serial Number *Not recommended for new designs. See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. www.onsemi.com 2 KAI−04050 DEVICE DESCRIPTION Architecture H2Bd H2Sd H1Bd H1Sd SUB H2Bc H2Sc H1Bc H1Sc ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ RDc Rc VDDc VOUTc RDd Rd VDDd VOUTd HLOD 1 10 22 12 8 1168 1168 8 12 22 10 1 1 Dummy 12 12 GND OGc H2SLc GND OGd H2SLd V1T V2T V3T V4T V1T V2T V3T V4T DevID 2336 H x 1752V 5.5mm x 5.5mm Pixels 22 12 ESD 12 22 V1B V2B V3B V4B RDa Ra VDDa VOUTa V1B V2B V3B V4B ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ 12 Buffer 12 Dark 1 Dummy (Last VCCD Phase = V1 à H1S) 1 10 22 12 8 1168 1168 HLOD H2Bb H2Sb H1Bb H1Sb SUB H2Ba H2Sa H1Ba H1Sa GND OGa H2SLa ESD 12 8 22 10 1 RDb Rb VDDb VOUTb GND OGb H2SLb Figure 2. Block Diagram Dark Reference Pixels These pixels are light sensitive but are not tested for defects and non-uniformities. There are 12 dark reference rows at the top and 12 dark rows at the bottom of the image sensor. The dark rows are not entirely dark and so should not be used for a dark reference level. Use the 22 dark columns on the left or right side of the image sensor as a dark reference. Under normal circumstances use only the center 20 columns of the 22 column dark reference due to potential light leakage. Image Acquisition An electronic representation of an image is formed when incident photons falling on the sensor plane create electron−hole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of potential wells at each photosite. Below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non−linearly dependent on wavelength. When the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. Dummy Pixels Within each horizontal shift register there are 11 leading additional shift phases. These pixels are designated as dummy pixels and should not be used to determine a dark reference level. In addition, there is one dummy row of pixels at the top and bottom of the image. ESD Protection Adherence to the power-up and power-down sequence is critical. Failure to follow the proper power-up and power-down sequences may cause damage to the sensor. See Power-Up and Power-Down Sequence section. Active Buffer Pixels 12 unshielded pixels adjacent to any leading or trailing dark reference regions are classified as active buffer pixels. www.onsemi.com 3 KAI−04050 Bayer Color Filter Pattern H2Bd H2Sd H1Bd H1Sd SUB H2Bc H2Sc H1Bc H1Sc RDc Rc VDDc VOUTc RDd Rd VDDd VOUTd HLOD ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ 1 10 22 12 8 GND OGc H2SLc 1168 BG GR V1T V2T V3T V4T 1168 12 8 22 10 1 1 Dummy 12 12 GND OGd H2SLd BG GR V1T V2T V3T V4T DevID ESD 2336 (H) × 1752 (V) 5.5 mm × 5.5 mm Pixels 22 12 V1B V2B V3B V4B ESD 12 22 BG GR V1B V2B V3B V4B BG GR ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ 12 Buffer 12 Dark 1 Dummy (Last VCCD Phase = V1 → H1S) RDa Ra VDDa VOUTa 1 10 22 12 8 1168 1168 RDb Rb VDDb VOUTb 12 8 22 10 1 HLOD GND OGb H2SLb H2Bb H2Sb H1Bb H1Sb SUB H2Ba H2Sa H1Ba H1Sa GND OGa H2SLa Figure 3. Bayer Color Filter Pattern TRUESENSE Sparse Color Filter Pattern H2Bd H2Sd H1Bd H1Sd SUB H2Bc H2Sc H1Bc H1Sc RDc Rc VDDc VOUTc RDd Rd VDDd VOUTd HLOD ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ 1 10 22 12 8 1168 1168 12 8 22 10 1 1 Dummy 12 12 GND OGc H2SLc G P R P V1T V2T V3T V4T G P R P P G P R P G P R B P G P B P G P P B P G P B P G GND OGd H2SLd V1T V2T V3T V4T DevID ESD V1B V2B V3B V4B RDa Ra VDDa VOUTa 12 22 G P R P G P R P P G P R P G P R B P G P B P G P P B P G P B P G ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ 12 Buffer 12 Dark 1 Dummy (Last VCCD Phase = V1 → H1S) 1 10 22 12 8 1168 1168 12 8 22 10 1 HLOD H2Bb H2Sb H1Bb H1Sb SUB H2Ba H2Sa H1Ba H1Sa GND OGa H2SLa 2336 (H) × 1752 (V) 5.5 mm × 5.5 mm Pixels 22 12 Figure 4. TRUESENSE Sparse Color Filter Pattern www.onsemi.com 4 ESD V1B V2B V3B V4B RDb Rb VDDb VOUTb GND OGb H2SLb KAI−04050 Physical Description Pin Description and Device Orientation 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 V3T V1T VDDc GND Rc H2SLc H1Bc H2Sc N/C H2Sd H1Bd H2SLd Rd GND VDDd V1T V3T 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 V4T V2T VOUTc RDc OGc H2Bc H1Sc SUB H1Sd H2Bd OGd RDd VOUTd V2T V4T DevID 4 68 ESD Pixel (1,1) 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 V4B V2B VOUTa RDa OGa H2Ba H1Sa SUB H1Sb H2Bb OGb RDb VOUTb V2B V4B ESD 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 V3B V1B VDDa GND Ra H2SLa H1Ba H2Sa N/C H2Sb H1Bb H2SLb Rb GND VDDb V1B V3B Figure 5. Package Pin Designations − Top View Table 3. PACKAGE PIN DESCRIPTION Pin Name Description 1 V3B Vertical CCD Clock, Phase 3, Bottom 3 V1B Vertical CCD Clock, Phase 1, Bottom 4 V4B Vertical CCD Clock, Phase 4, Bottom 5 VDDa Output Amplifier Supply, Quadrant a 6 V2B Vertical CCD Clock, Phase 2, Bottom 7 GND Ground 8 VOUTa 9 Ra Reset Gate, Quadrant a 10 RDa Reset Drain, Quadrant a 11 H2SLa Video Output, Quadrant a Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a 12 OGa Output Gate, Quadrant a 13 H1Ba Horizontal CCD Clock, Phase 1, Barrier, Quadrant a 14 H2Ba Horizontal CCD Clock, Phase 2, Barrier, Quadrant a 15 H2Sa Horizontal CCD Clock, Phase 2, Storage, Quadrant a 16 H1Sa Horizontal CCD Clock, Phase 1, Storage, Quadrant a 17 N/C No Connect 18 SUB Substrate 19 H2Sb Horizontal CCD Clock, Phase 2, Storage, Quadrant b 20 H1Sb Horizontal CCD Clock, Phase 1, Storage, Quadrant b 21 H1Bb Horizontal CCD Clock, Phase 1, Barrier, Quadrant b 22 H2Bb Horizontal CCD Clock, Phase 2, Barrier, Quadrant b www.onsemi.com 5 KAI−04050 Table 3. PACKAGE PIN DESCRIPTION (continued) Pin Name Description 23 H2SLb 24 OGb Output Gate, Quadrant b 25 Rb Reset Gate, Quadrant b 26 RDb Reset Drain, Quadrant b 27 GND Ground 28 VOUTb 29 VDDb Output Amplifier Supply, Quadrant b 30 V2B Vertical CCD Clock, Phase 2, Bottom 31 V1B Vertical CCD Clock, Phase 1, Bottom 32 V4B Vertical CCD Clock, Phase 4, Bottom 33 V3B Vertical CCD Clock, Phase 3, Bottom 34 ESD ESD Protection Disable 35 V3T Vertical CCD Clock, Phase 3, Top 36 DevID 37 V1T Vertical CCD Clock, Phase 1, Top 38 V4T Vertical CCD Clock, Phase 4, Top 39 VDDd 40 V2T Vertical CCD Clock, Phase 2, Top 41 GND Ground 42 VOUTd 43 Rd Reset Gate, Quadrant d 44 RDd Reset Drain, Quadrant d 45 H2SLd Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant b Video Output, Quadrant b Device Identification Output Amplifier Supply, Quadrant d Video Output, Quadrant d Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant d 46 OGd Output Gate, Quadrant d 47 H1Bd Horizontal CCD Clock, Phase 1, Barrier, Quadrant d 48 H2Bd Horizontal CCD Clock, Phase 2, Barrier, Quadrant d 49 H2Sd Horizontal CCD Clock, Phase 2, Storage, Quadrant d 50 H1Sd Horizontal CCD Clock, Phase 1, Storage, Quadrant d 51 N/C No Connect 52 SUB Substrate 53 H2Sc Horizontal CCD Clock, Phase 2, Storage, Quadrant c 54 H1Sc Horizontal CCD Clock, Phase 1, Storage, Quadrant c 55 H1Bc Horizontal CCD Clock, Phase 1, Barrier, Quadrant c 56 H2Bc Horizontal CCD Clock, Phase 2, Barrier, Quadrant c 57 H2SLc Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant c 58 OGc Output Gate, Quadrant c 59 Rc Reset Gate, Quadrant c 60 RDc Reset Drain, Quadrant c 61 GND Ground 62 VOUTc Video Output, Quadrant c 63 VDDc Output Amplifier Supply, Quadrant c 64 V2T Vertical CCD Clock, Phase 2, Top 65 V1T Vertical CCD Clock, Phase 1, Top 66 V4T Vertical CCD Clock, Phase 4, Top 67 V3T Vertical CCD Clock, Phase 3, Top 68 ESD EDS Protection Disable 1. Liked named pins are internally connected and should have a common drive signal. 2. N/C pins (17, 51) should be left floating. www.onsemi.com 6 KAI−04050 IMAGING PERFORMANCE Table 4. TYPICAL OPERATIONAL CONDITIONS (Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.) Condition Description Light Source Continuous Red, Green and Blue LED Illumination Operation Nominal Operating Voltages and Timing Notes 1 1. For monochrome sensor, only green LED used. Specifications Table 5. PERFORMANCE SPECIFICATIONS Description Temperature Tested at (5C) Symbol Min. Nom. Max. Unit Sampling Plan DSNU − − 2.0 mVpp Die 27, 40 − 2.0 5.0 % rms Die 27, 40 − 5.0 15.0 % pp Die 27, 40 − 1.0 2.0 % rms Die 27, 40 ALL CONFIGURATIONS Dark Field Global Non-Uniformity Bright Field Global Non-Uniformity (Note 1) Bright Field Global Peak to Peak Non-Uniformity (Note 1) PRNU Bright Field Center Non-Uniformity (Note 1) Maximum Photoresponse Nonlinearity NL − 2 − % Design Maximum Gain Difference between Outputs (Note 2) DG − 10 − % Design Maximum Signal Error due to Nonlinearity Differences (Note 2) DNL − 1 − % Design Horizontal CCD Charge Capacity HNe − 55 − ke− Design Vertical CCD Charge Capacity VNe − 40 − ke− Design ke− Die Photodiode Charge Capacity (Note 3) PNe − 20 − Horizontal CCD Charge Transfer Efficiency HCTE 0.999995 0.999999 − Die Vertical CCD Charge Transfer Efficiency VCTE 0.999995 0.999999 − Die Photodiode Dark Current IPD − 7 70 e/p/s Die 40 Vertical CCD Dark Current IVD − 100 300 e/p/s Die 40 e− Design Image Lag Lag − − 10 Anti-Blooming Factor XAB 300 − − Vertical Smear Smr − −100 − Read Noise (Note 4) ne−T − 12 − Dynamic Range (Notes 4, 5) DR − 64 − Output Amplifier DC Offset VODC − 9.4 Output Amplifier Bandwidth (Note 6) f−3db − 250 Output Amplifier Impedance ROUT − 127 Output Amplifier Sensitivity DV/DN − 34 Design dB e− rms Design Design dB Design − V Die − MHz Die − W Die − mV/e− Design KAI−04050−ABA, KAI−04050−QBA, AND KAI−04050−PBA(7) CONFIGURATIONS Peak Quantum Efficiency Peak Quantum Efficiency Wavelength QEMAX − 46 − % Design lQE − 500 − nm Design www.onsemi.com 7 27, 40 27, 40 27, 40 KAI−04050 Table 5. PERFORMANCE SPECIFICATIONS (continued) Description Symbol Min. Nom. Max. Unit Sampling Plan Temperature Tested at (5C) KAI−04050−FBA AND KAI−04050−QBA GEN2 COLOR CONFIGURATIONS WITH MAR GLASS Peak Quantum Efficiency Blue Green Red Peak Quantum Efficiency Wavelength Blue Green Red QEMAX lQE − − − 38 37 31 − − − − − − 460 530 605 − − − % Design nm Design % Design nm Design KAI−04050−FBA GEN2 COLOR CONFIGURATION WITH CLEAR GLASS Peak Quantum Efficiency Blue Green Red Peak Quantum Efficiency Wavelength Blue Green Red QEMAX lQE − − − 35 34 29 − − − − − − 460 530 605 − − − KAI−04050−CBA AND KAI−04050−PBA GEN1 COLOR CONFIGURATIONS WITH MAR GLASS (Note 7) Peak Quantum Efficiency Blue Green Red Peak Quantum Efficiency Wavelength Blue Green Red QEMAX lQE − − − 39 37 29 − − − − − − 470 540 620 − − − % Design nm Design % Design nm Design KAI−04050−CBA GEN1 COLOR CONFIGURATION WITH CLEAR GLASS (Note 7) Peak Quantum Efficiency Blue Green Red Peak Quantum Efficiency Wavelength Blue Green Red QEMAX lQE − − − 36 34 27 − − − − − − 470 540 620 − − − 1. Per color. 2. Value is over the range of 10% to 90% of linear signal level saturation. 3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such that the photodiode charge capacity is 680 mV. 4. At 40 MHz. 5. Uses 20LOG (PNe / ne−T). 6. Assumes 5 pF load. 7. This color filter set configuration (Gen1) is not recommended for new designs. www.onsemi.com 8 KAI−04050 TYPICAL PERFORMANCE CURVES Quantum Efficiency Monochrome, All Configurations Figure 6. Monochrome Configurations − Quantum Efficiency Color (Bayer RGB) with Microlens and MAR Cover Glass (Gen2 and Gen1 CFA) Figure 7. MAR Glass Color (Bayer) with Microlens Quantum Efficiency www.onsemi.com 9 KAI−04050 Color (Bayer RGB) with Microlens and Clear Cover Glass (Gen2 and Gen1 CFA) Figure 8. Clear Glass Color (Bayer) with Microlens Quantum Efficiency Color (TRUESENSE Sparse CFA) with Microlens (Gen2 and Gen1 CFA) Figure 9. Color (TRUESENSE Sparse CFA) with Microlens Quantum Efficiency www.onsemi.com 10 KAI−04050 Angular Quantum Efficiency For the curves marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD. For the curves marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD. Monochrome with Microlens 100 Relative Quantum Efficiency (%) 90 Vertical 80 70 60 50 Horizontal 40 30 20 10 0 −30 −20 −10 0 10 20 30 Angle (degrees) Figure 10. Monochrome with Microlens Angular Quantum Efficiency Dark Current vs. Temperature 10000 Dark Current (e/s) 1000 VCCD 100 10 Photodiode 1 0.1 1000/T (K) 2.9 T (C) 72 3.0 3.1 3.2 3.3 3.4 60 50 40 30 21 Figure 11. Dark Current vs. Temperature www.onsemi.com 11 KAI−04050 Power-Estimated 1.2 1.0 Power (W) 0.8 0.6 0.4 0.2 0.0 10 15 20 25 30 35 40 HCCD Frequency (MHz) Single Dual Quad Figure 12. Power Frame Rate (fps) Frame Rates 40 40 35 35 30 30 25 25 20 20 15 15 10 10 5 5 0 0 10 15 20 25 30 35 HCCD Frequency (MHz) Single Dual (Left/Right) Figure 13. Frame Rates www.onsemi.com 12 Quad 40 KAI−04050 DEFECT DEFINITIONS Table 6. OPERATION CONDITIONS FOR DEFECT TESTING AT 405C Description Operational Mode Condition Two Outputs, using VOUTa and VOUTc, Continuous Readout HCCD Clock Frequency 10 MHz Pixels per Line 2,560 1 992 2 Lines per Frame Line Time 259.8 ms Frame Time 256.8 ms Photodiode Integration Time (PD_Tint) Notes Mode A: PD_Tint = Frame Time = 256.8 ms, No Electronic Shutter Used Mode B: PD_Tint = 33 ms, Electronic Shutter Used VCCD Integration Time 233.0 ms 3 Temperature 40°C Light Source Continuous Red, Green and Blue LED Illumination Operation 1. 2. 3. 4. 4 Nominal Operating Voltages and Timing Horizontal overclocking used Vertical overclocking used VCCD Integration Time = 900 lines x Line Time, which is the total time a pixel will spend in the VCCD registers. For monochrome sensor, only the green LED is used. Table 7. DEFECT DEFINITIONS FOR TESTING AT 405C Description Definition Standard Grade Grade 2 Notes Major Dark Field Defective Bright Pixel PD_Tint = Mode A → Defect ≥ 88 mV or PD_Tint = Mode B → Defect ≥ 12 mV 40 40 1 Major Bright Field Defective Dark Pixel Defect ≥ 12% 40 40 1 Minor Dark Field Defective Bright Pixel PD_Tint = Mode A → Defect ≥ 44 mV or PD_Tint = Mode B → Defect ≥ 6 mV 400 400 Cluster Defect A group of 2 to 10 contiguous major defective pixels, but no more than 2 adjacent defects horizontally. 8 n/a 2 Cluster Defect (Grade 2) A group of 2 to 10 contiguous major defective pixels n/a 10 2 A group of more than 10 contiguous major defective pixels along a single column. 0 0 2 Column Defect 1. For the color device (KAI−04050−FBA ,KAI−04050−CBA, KAI−04050−QBA, or KAI−04050−PBA), a bright field defective pixel deviates by 12% with respect to pixels of the same color. 2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects). www.onsemi.com 13 KAI−04050 Table 8. OPERATION CONDITIONS FOR DEFECT TESTING AT 275C Description Operational Mode Condition Two Outputs, using VOUTa and VOUTc, Continuous Readout HCCD Clock Frequency 20 MHz Pixels per Line 2,560 1 992 2 Lines per Frame Line Time 131.5 ms Frame Time 130.4 ms Photodiode Integration Time (PD_Tint) Notes Mode A: PD_Tint = Frame Time = 130.4 ms, No Electronic Shutter Used Mode B: PD_Tint = 33 ms, Electronic Shutter Used VCCD Integration Time 118.2 ms 3 Temperature 27°C Light Source Continuous Red, Green and Blue LED Illumination Operation 1. 2. 3. 4. 4 Nominal Operating Voltages and Timing Horizontal overclocking used Vertical overclocking used VCCD Integration Time = 900 lines x Line Time, which is the total time a pixel will spend in the VCCD registers. For monochrome sensor, only the green LED is used. Table 9. DEFECT DEFINITIONS FOR TESTING AT 275C Description Definition Standard Grade Grade 2 Notes Major Dark Field Defective Bright Pixel PD_Tint = Mode A → Defect ≥ 14 mV or PD_Tint = Mode B → Defect ≥ 4 mV 40 40 1 Major Bright Field Defective Dark Pixel Defect ≥ 12% 40 40 1 Cluster Defect A group of 2 to 10 contiguous major defective pixels, but no more than 2 adjacent defects horizontally. 8 n/a 2 Cluster Defect (Grade 2) A group of 2 to 10 contiguous major defective pixels n/a 10 2 A group of more than 10 contiguous major defective pixels along a single column. 0 0 2 Column Defect 1. For the color device (KAI−04050−FBA ,KAI−04050−CBA, KAI−04050−QBA, or KAI−04050−PBA), a bright field defective pixel deviates by 12% with respect to pixels of the same color. 2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects). Defect Map defects are not included in the defect map. All defective pixels are reference to pixel 1, 1 in the defect maps. See Figure 14 for the location of pixel 1, 1. The defect map supplied with each sensor is based upon testing at an ambient (27°C) temperature. Minor point www.onsemi.com 14 KAI−04050 TEST DEFINITIONS Test Regions of Interest Overclocking Image Area ROI: Active Area ROI: Center ROI: The test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. See Figure 14 for a pictorial representation of the regions of interest. Pixel (1, 1) to Pixel (2360, 1776) Pixel (13, 13) to Pixel (2348, 1764) Pixel (1131, 839) to Pixel (1230, 938) Only the Active Area ROI pixels are used for performance and defect tests. VOUTc 12 dark rows 12 buffer rows Horizontal Overclock 22 dark columns 12 buffer columns 12 buffer columns 22 dark columns Pixel 13, 13 2336 x 1752 Active Pixels Pixel 1, 1 12 buffer rows 12 dark rows VOUTa Figure 14. Regions of Interest Tests are found. The dark field global uniformity is then calculated as the maximum signal found minus the minimum signal level found. Dark Field Global Non-Uniformity This test is performed under dark field conditions. The sensor is partitioned into 192 sub regions of interest, each of which is 146 by 146 pixels in size. (See Figure 15: Test Sub Regions of Interest.) The average signal level of each of the 192 sub regions of interest is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: Global Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 476 mV). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mV. Global non-uniformity is defined as Signal of ROI[i] + (ROI Average in Counts * * Horizontal Overclock Average in Counts) @ @ mV per Count Global Non−Uniformity + 100 @ Units : mVpp (millivolts Peak to Peak) ǒ Active Area Standard Deviation Active Area Signal Ǔ Units : % rms Active Area Signal = Active Area Average − Dark Column Average where i = 1 to 192. During this calculation on the 192 sub regions of interest, the maximum and minimum signal levels www.onsemi.com 15 KAI−04050 Bright Field Defect Test This test is performed with the imager illuminated to a level such that the output is at approximately 476 mV. Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mV. The average signal level of all active pixels is found. The bright and dark thresholds are set as: Global Peak to Peak Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 476 mV). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mV. The sensor is partitioned into 192 sub regions of interest, each of which is 146 by 146 pixels in size.(See Figure 15: Test Sub Regions of Interest.) The average signal level of each of the 192 sub regions of interest (ROI) is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: Dark Defect Threshold = Active Area Signal @ Threshold Bright Defect Threshold = Active Area Signal @ Threshold The sensor is then partitioned into 192 sub regions of interest, each of which is 146 by 146 pixels in size. In each region of interest, the average value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. Example for major bright field defective pixels: • Average value of all active pixels is found to be 476 mV • Dark defect threshold: 476 mV ⋅ 12% = 57 mV • Bright defect threshold: 476 mV ⋅ 12% = 57 mV • Region of interest #1 selected. This region of interest is pixels 13, 13 to pixels 158, 158 ♦ Median of this region of interest is found to be 470 mV ♦ Any pixel in this region of interest that is ≥ (470 + 57 mV) 527 mV in intensity will be marked defective ♦ Any pixel in this region of interest that is ≤ (470 − 57 mV) 413 mV in intensity will be marked defective • All remaining 192 sub regions of interest are analyzed for defective pixels in the same manner Signal of ROI[i] + (ROI Average in Counts * * Horizontal Overclock Average in Counts) @ @ mV per Count Where i = 1 to 192. During this calculation on the 192 sub regions of interest, the maximum and minimum signal levels are found. The global peak to peak uniformity is then calculated as: Global Uniformity + 100 @ ǒ Ǔ Max. Signal * Min. Signal Active Area Signal Units : % pp Center Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 476 mV). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mV. Defects are excluded for the calculation of this test. This test is performed on the center 100 by 100 pixels of the sensor. Center uniformity is defined as: Center ROI Uniformity + 100 @ ǒ Center ROI Standard Deviation Center ROI Signal Ǔ Units : % rms Center ROI Signal = Center ROI Average − Dark Colum Average Dark Field Defect Test This test is performed under dark field conditions. The sensor is partitioned into 192 sub regions of interest, each of which is 146 by 146 pixels in size. In each region of interest, the median value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in the “Detect Definitions” section. www.onsemi.com 16 KAI−04050 Test Sub Regions of Interest Pixel (2348, 1764) 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pixel (13,13) VOUTa Figure 15. Test Sub Regions of Interest www.onsemi.com 17 KAI−04050 OPERATION Absolute Maximum Ratings description. If the level or the condition is exceeded, the device will be degraded and may be damaged. Operation at these values will reduce MTTF. Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the Table 10. ABSOLUTE MAXIMUM RATINGS Description Symbol Minimum Maximum Unit Notes Operating Temperature TOP −50 70 °C 1 Humidity RH 5 90 % 2 Output Bias Current IOUT − 60 mA 3 CL − 10 pF Off-Chip Load Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Noise performance will degrade at higher temperatures. 2. T = 25°C. Excessive humidity will degrade MTTF. 3. Total for all outputs. Maximum current is −15 mA for each output. Avoid shorting output pins to ground or any low impedance source during operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity). Table 11. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND Description Minimum Maximum Unit Notes VDDa, VOUTa −0.4 17.5 V 1 RDa −0.4 15.5 V 1 V1B, V1T ESD − 0.4 ESD + 24.0 V V2B, V2T, V3B, V3T, V4B, V4T ESD − 0.4 ESD + 14.0 V H1Sa, H1Ba, H2Sa, H2Ba, H2SLa, Ra, OGa ESD − 0.4 ESD + 14.0 V ESD −10.0 0.0 V SUB −0.4 40.0 V 1. a denotes a, b, c or d. 2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions www.onsemi.com 18 1 2 KAI−04050 Power-Up and Power-Down Sequence Adherence to the power-up and power-down sequence is critical. Failure to follow the proper power-up and power-down sequences may cause damage to the sensor. Do Not Pulse the Electronic Shutter until ESD is Stable V+ VDD SUB Time ESD V− VCCD Low HCCD Low Activate All Other Biases when ESD is Stable and Sub is above 3 V Notes: 1. Activate all other biases when ESD is stable and SUB is above 3 V. 2. Do not pulse the electronic shutter until ESD is stable. 3. VDD cannot be +15 V when SUB is 0 V. 4. The image sensor can be protected from an accidental improper ESD voltage by current limiting the SUB current to less than 10 mA. SUB and VDD must always be greater than GND. ESD must always be less than GND. Placing diodes between SUB, VDD, ESD and ground will protect the sensor from accidental overshoots of SUB, VDD and ESD during power on and power off. See the figure below. Figure 16. Power-Up and Power-Down Sequence The VCCD clock waveform must not have a negative overshoot more than 0.4 V below the ESD voltage. 0.0 V ESD ESD − 0.4 V All VCCD Clocks Absolute Maximum Overshoot of 0.4 V Figure 17. VCCD Clock Waveform Example of external diode protection for SUB, VDD and ESD. a denotes a, b, c or d. VDDa SUB GND ESD Figure 18. Example of External Diode Protection www.onsemi.com 19 KAI−04050 DC Bias Operating Conditions Table 12. DC BIAS OPERATING CONDITIONS Pins Symbol Min. Nom. Max. Unit Max. DC Current Notes Reset Drain RDa RD 11.8 12.0 12.2 V 10 mA 1 Output Gate OGa OG −2.2 −2.0 −1.8 V 10 mA 1 Output Amplifier Supply VDDa VDD 14.5 15.0 15.5 V 11.0 mA 1, 2 Ground GND GND 0.0 0.0 0.0 V −1.0 mA Substrate SUB VSUB 5.0 VAB VDD V 50 mA 3, 8 ESD Protection Disable ESD ESD −9.5 −9.0 Vx_L V 50 mA 6, 7, 9 VOUTa IOUT −3.0 −7.0 −10.0 mA − 1, 4, 5 Description Output Bias Current VDDa RDa Ra 1. a denotes a, b, c or d. 2. The maximum DC current is for one output. IDD = IOUT + ISS. See Figure 19. 3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such that the photodiode charge capacity is the nominal PNe (see Specifications). 4. An output load sink must be applied to each VOUT pin to activate each output amplifier. 5. Nominal value required for 40 MHz operation per output. May be reduced for slower data rates and lower noise. 6. Adherence to the power-up and power-down sequence is critical. See Power−Up and Power−Down Sequence section. 7. ESD maximum value must be less than or equal to V1_L + 0.4 V and V2_L + 0.4 V. 8. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. 9. Where Vx_L is the level set for V1_L, V2_L, V3_L, or V4_L in the application. IDD HCCD Floating Diffusion IOUT VOUTa OGa ISS Source Follower #1 Figure 19. Output Amplifier www.onsemi.com 20 Source Follower #2 Source Follower #3 KAI−04050 AC Operating Conditions Table 13. CLOCK LEVELS Description Vertical CCD Clock, Phase 1 Pins1 Symbol Level Min. Nom. Max. Units Capacitance2 V1B, V1T V1_L Low −8.2 −8.0 −7.8 V 21 nF (Note 6) V1_M Mid −0.2 0.0 0.2 V1_H High 11.5 12.0 12.5 V2_L Low −8.2 −8.0 −7.8 V 21 nF (6) V2_H High −0.2 0.0 0.2 V3_L Low −8.2 −8.0 −7.8 V 21 nF (6) V3_H High −0.2 0.0 0.2 V4_L Low −8.2 −8.0 −7.8 V 21 nF (6) V4_H High −0.2 0.0 0.2 −4.0 −3.8 V 200 pF (6) 4.0 5.2 (7) −4.0 −3.8 V 130 pF (6) V 200 pF (6) V 130 pF (6) V 20 pF (6) V 16 pF (6) V 1400 pF (6) Vertical CCD Clock, Phase 2 V2B, V2T Vertical CCD Clock, Phase 3 V3B, V3T Vertical CCD Clock, Phase 4 V4B, V4T Horizontal CCD Clock, Phase 1 Storage H1Sa Horizontal CCD Clock, Phase 1 Barrier H1Ba Horizontal CCD Clock, Phase 2 Storage H2Sa Horizontal CCD Clock, Phase 2 Barrier H2Ba Horizontal CCD Clock, Last Phase (Note 3) H2SLa Reset Gate R1a Electronic Shutter (Note 5) 1. 2. 3. 4. 5. 6. 7. SUB H1S_L Low H1S_A Amplitude −5.2 (7) 3.8 −5.2 (7) H1B_L Low H1B_A Amplitude 3.8 4.0 5.2 (7) H2S_L Low −5.2 (7) −4.0 −3.8 H2S_A Amplitude 3.8 4.0 5.2 (7) H2B_L Low −5.2 (7) −4.0 −3.8 H2B_A Amplitude 3.8 4.0 H2SL_L Low −5.2 −5.0 −4.8 H2SL_A Amplitude 4.8 5.0 5.2 Low −3.5 −2.0 −1.5 R_A Amplitude 2.5 3.0 4.0 VES High 29.0 30.0 40.0 R_L (4) 5.2 (7) a denotes a, b, c or d. Capacitance is total for all like named pins. Use separate clock driver for improved speed performance. Reset low should be set to −3 V for signal levels greater than 40,000 electrons. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. Capacitance values are estimated. If the minimum horizontal clock low level is used (–5.2 V), then the maximum horizontal clock amplitude should be used (5.2 V amplitude) to create a –5.2 V to 0.0 V clock. If a 5 volt clock driver is used, the horizontal low level should be set to –5.0 V and the high level should be a set to 0.0 V. The figure below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock are referenced to ground. VES VSUB GND GND Figure 20. DC Bias and AC Clock Applied to the SUB Pin www.onsemi.com 21 KAI−04050 Device Identification The device identification pin (DevID) may be used to determine which Truesense Imaging 5.5 micron pixel interline CCD sensor is being used. Table 14. DEVICE IDENTIFICATION Description Device Identification Pins Symbol Min. Nom. Max. Unit Max. DC Current Notes DevID DevID 20,000 25,000 30,000 W 50 mA 1, 2, 3 1. Nominal value subject to verification and/or change during release of preliminary specifications. 2. If the Device Identification is not used, it may be left disconnected. 3. Values specified are for 40°C. Recommended Circuit Note that V1 must be a different value than V2. V1 V2 R_external DevID ADC R_DeviceID GND KAI−04050 Figure 21. Device Identification Recommended Circuit www.onsemi.com 22 KAI−04050 TIMING Requirements and Characteristics Table 15. REQUIREMENTS AND CHARACTERISTICS Description Symbol Min. Nom. Max. Unit Photodiode Transfer tPD 1.0 − − ms VCCD Leading Pedestal t3P 4.0 − − ms VCCD Trailing Pedestal t3D 4.0 − − ms VCCD Transfer Delay tD 1.0 − − ms tV 1.6 − − ms VVCR 75 − 100 % tVR, tVF 5 − 10 % tHS 0.2 − − ms HCCD Transfer te 25.0 − − ns Shutter Transfer tSUB 1.0 − − ms Shutter Delay tHD 1.0 − − ms Reset Pulse tR 2.5 − − ns Reset − Video Delay tRV − 2.2 − ns tHV − 3.1 − ns tLINE 32.9 − − ms 63.0 − − 29.7 − − 59.3 − − Dual HCCD Readout 113.4 − − Single HCCD Readout VCCD Transfer VCCD Clock Cross-Over VCCD Rise, Fall Times HCCD Delay H2SL − Video Delay Line Time Frame Time tFRAME 1. Refer to Figure 26: VCCD Clock Edge Alignment. 2. Relative to the pulse width. www.onsemi.com 23 Notes 1, 2 Dual HCCD Readout Single HCCD Readout ms Quad HCCD Readout KAI−04050 Timing Diagrams table below. The patterns are defined in Figure 22 and Figure 23. Contact ON Semiconductor Application Engineering for other readout modes. The timing sequence for the clocked device pins may be represented as one of seven patterns (P1−P7) as shown in the Table 16. TIMING DIAGRAMS Device Pin Quad Readout Dual Readout VOUTa, VOUTb Dual Readout VOUTa, VOUTc Single Readout VOUTa V1T P1T P1B P1T P1B V2T P2T P4B P2T P4B V3T P3T P3B P3T P3B V4T P4T P2B P4T P2B V1B P1B V2B P2B V3B P3B V4B P4B H1Sa P5 H1Ba P6 H2Sa (Note 2) H2Ba Ra P7 P5 H1Sb P5 H1Bb P6 P6 H2Sb (Note 2) P6 H2Bb P5 Rb P7 P7 (Note 1) or Off (Note 3) P7 (Note 1) or Off (Note 3) P5 P5 (Note 1) or Off (Note 3) P5 P5 (Note 1) or Off (Note 3) P6 P6 (Note 1) or Off (Note 3) P6 P6 (Note 1) or Off (Note 3) Rc P7 P7 (Note 1) or Off (Note 3) P7 P7 (Note 1) or Off (Note 3) H1Sd P5 P5 (Note 1) or Off (Note 3) P5 P5 (Note 1) or Off (Note 3) H1Sc H1Bc H2Sc (Note 2) H2Bc H1Bd H2Sd (Note 2) P6 P6 P6 (Note 1) or Off (Note 3) H2Bd P6 (Note 1) or Off (Note 3) P6 P5 Rd P7 P7 (Note 1) or Off (Note 3) P7 (Note 1) or Off (Note 3) P7 (Note 1) or Off (Note 3) #Lines/Frame (Minimum) 900 1800 900 1800 #Pixels/Line (Minimum) 1213 2426 1. For optimal performance of the sensor. May be clocked at a lower frequency. If clocked at a lower frequency, the frequency selected should be a multiple of the frequency used on the a and b register. 2. H2SLx follows the same pattern as H2Sx. For optimal speed performance, use a separate clock driver. 3. Off = +5 V. Note that there may be operating conditions (high temperature and/or very bright light sources) that will cause blooming from the unused c/d register into the image area. www.onsemi.com 24 KAI−04050 Photodiode Transfer Timing A row of charge is transferred to the HCCD on the falling edge of V1 as indicated in the P1 pattern below. Using this timing sequence, the leading dummy row or line is combined with the first dark row in the HCCD. The “Last Line” is dependent on readout mode – either 632 or 1264 minimum counts required. It is important to note that, in 1 Pattern 2 tD 3 t3P 4 tPD 5 t3D general, the rising edge of a vertical clock (patterns P1−P4) should be coincident or slightly leading a falling edge at the same time interval. This is particularly true at the point where P1 returns from the high (3rd level) state to the mid-state when P4 transitions from the low state to the high state. 6 tD tV tV P1T tV/2 P2T tV/2 tV/2 tV/2 P3T P4T tV P1B tV/2 tV tV/2 P2B P3B P4B tHS tHS Last Line P5 L1 + Dummy Line L2 P6 P7 Figure 22. Photodiode Transfer Timing P6 pattern). The number of pixels in a row is dependent on readout mode – either 1213 or 2426 minimum counts required. Line and Pixel Timing Each row of charge is transferred to the output, as illustrated below, on the falling edge of H2SL (indicated as tLINE Pattern tV P1T P1B tV tHS P5 P6 te/2 te tR P7 VOUT Pixel 1 Pixel 34 Pixel n Figure 23. Line and Pixel Timing www.onsemi.com 25 KAI−04050 Pixel Timing Detail P5 P6 P7 VOUT tHV tRV Figure 24. Pixel Timing Detail Frame/Electronic Shutter Timing The SUB pin may be optionally clocked to provide electronic shuttering capability as shown below. The resulting photodiode integration time is defined from the falling edge of SUB to the falling edge of V1 (P1 pattern). Pattern tFRAME P1T/B tHD tSUB SUB P6 tINT tHD Figure 25. Electronic Shutter Timing VCCD Clock Edge Alignment VVCR tV 90% 10% tVR tVF tV tVF tVR Figure 26. VCCD Clock Edge Alignment www.onsemi.com 26 KAI−04050 Line and Pixel Timing − Vertical Binning by 2 tV tV tV tHS P1T P2T P3T P4T P1B P2B P3B P4B tHS P5 P6 P7 VOUT Pixel 1 Pixel n Pixel 34 Figure 27. Line and Pixel Timing − Vertical Binning by 2 www.onsemi.com 27 KAI−04050 STORAGE AND HANDLING Table 17. STORAGE CONDITIONS Description Symbol Minimum Maximum Unit Storage Temperature (Note 1) TST −55 80 °C Humidity (Note 2) RH 5 90 % 1. Long-term exposure toward the maximum temperature will accelerate color filter degradation. 2. T = 25°C. Excessive humidity will degrade MTTF. For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on environmental exposure, please download the Using Interline CCD Image Sensors in High Intensity Lighting Conditions Application Note (AND9183/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com. www.onsemi.com 28 KAI−04050 MECHANICAL INFORMATION Completed Assembly Notes: 1. See Ordering Information for marking code. 2. No materials to interfere with clearance through guide holes. 3. The center of the active image is nominally at the center of the package. 4. Die rotation < 0.5 degrees. 5. Cover glass placement is within recess cavity wall. 6. Internal traces may be exposed on sides of package. Do not allow metal to contact sides of ceramic package. 7. Recommended mounting screws: 1.6 x 0.35 mm (ISO Standard); 0 − 80 (Unified Fine Thread Standard). 8. Units: millimeters. Figure 28. Completed Assembly www.onsemi.com 29 KAI−04050 MAR Cover Glass Notes: 1. Dust/Scratch count − 12 microns maximum 2. Units: mm. Figure 29. MAR Cover Glass www.onsemi.com 30 KAI−04050 Clear Cover Glass Notes: 1. Dust/Scratch count − 12 microns maximum 2. Units: mm. Figure 30. Clear Cover Glass www.onsemi.com 31 KAI−04050 Cover Glass Transmission 100 90 Transmission (%) 80 70 60 50 40 30 20 10 0 200 300 400 500 600 700 800 Wavelength (nm) MAR Clear Figure 31. Cover Glass Transmission www.onsemi.com 32 900 KAI−04050 SHIPPING CONFIGURATION Cover Glass Protective Tape Cover glass protective tape, as shown in Figure 32, is utilized to help ensure the cleanliness of the cover glass during transportation and camera manufacturing. This protective tape is not intended to be optically correct, and should be removed prior to any image testing. The protective tape should be removed in an ionized air stream to prevent static build-up and the attraction of particles. The following part numbers will have the protective tape applied: Table 18. Part Number Description KAI−04050−CBA−JB−B2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass (No Coatings), Grade 2 KAI−04050−CBA−JB−AE Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass (No Coatings), Engineering Grade KAI−04050−CBA−JB−B2−T Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass (No Coatings), Grade 2, Packed in Trays Table 19. Criteria Placement Tab Location Scratches Description Per the drawing. The lid tape shall not overhang the edge of the package or mounting holes. The lid tape always overhangs the top of the glass (chamfers not included). The tape tab is located near pin 68. The tape application equipment will make slight scratches on the lid tape. This is allowed. Figure 32. Cover Glass Protective Tape www.onsemi.com 33 KAI−04050 Tray Packing 192 image sensors per brick. The minimum order and multiple quantities for this configuration are 192 image sensors. The following part numbers are packed in bricks of 6 trays, each tray containing 32 image sensors, for a total of Table 20. Part Number KAI−04050−CBA−JB−B2−T Description Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass (No Coatings), Grade 2, Packed in Trays Tray Configuration Pin-Up View Tray Position 1 Pin 1 Tray Location Marking Tray Position 32 Figure 33. Tray Pin-Up View Pin-Down View Pin 1 Tray Position 1 Tray Location Marking Tray Position 32 Figure 34. Tray Pin-Down View www.onsemi.com 34 KAI−04050 sensors in the brick. The ID label is applied to the top of the brick. Tray 1 is at the bottom of the brick and the empty tray is at the top of the brick. Brick Configuration Bricks consist of 6 full trays and 1 empty tray. Each tray contains 32 image sensors. There are a total of 192 image Strapping (2 Places) Tray Sheet Covers Brick ID Label Figure 35. Brick The Brick ID is Encoded in the Bar Code. Brick ID Figure 36. Brick ID Label Brick in Vacuum Sealed Bag Brick Label (Figure 41) Figure 37. Sealed Brick www.onsemi.com 35 KAI−04050 Shipping Container Brick Loaded in Shipping Container Figure 38. Brick Loaded in Shipping Container Open Shipping Container with Parts List The parts list (see Figure 42) details information for each sensor in the brick. The parts list includes the serial number, tray and location, and VAB value for each sensor. Figure 39. Open Shipping Container with Parts List Sealed Shipping Container The Brick Label (see Figure 41) is applied to both ends of the shipping container. Figure 40. Sealed Shipping Container www.onsemi.com 36 KAI−04050 Brick Label Figure 41. Brick Label Parts List The parts list details information for each sensor in the brick. The parts list includes the serial number, tray and location, and VAB value for each sensor. Additionally, the VAB value and serial number are encoded in the bar code. Serial Number VAB Position in Tray Tray Figure 42. Parts List www.onsemi.com 37 KAI−04050 REFERENCES For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on environmental exposure, please download the Using Interline CCD Image Sensors in High Intensity Lighting Conditions Application Note (AND9183/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 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