LC75810T-8725-E

LC75810E, LC75810T 1/8 to 1/10-Duty Dot Matrix LCD Controller / Driver Overview The LC75810E and LC75810T are 1/8 to 1/10 duty dot matrix LCD display controllers/drivers that support the display of characters, numbers, and symbols. In addition to generating dot matrix LCD drive signals based on data transferred serially from a microcontroller, the LC75810E and LC75810T also provide on-chip character display ROM and RAM to allow display systems to be implemented easily. Features  Controls and drives a 5  7, 5  8, or 5  9 dot matrix LCD.  Supports accessory display segment drive (up to 80 segments)  Display technique: 1/8-duty, 1/4-bias drive (5  7 dots, 6  7 dots) 1/9-duty, 1/4-bias drive (5  8 dots, 6  8 dots) 1/10-duty, 1/4-bias drive (5  9 dots, 6  9 dots)  Display digits: 16 digits  1 line (5  7 dots), 15 digits × 1 line (5  8 or 5  9 dots) 13 digits  1 line (6  7, 6  8, or 6  9 dots)  Display control memory CGROM: 240 characters (5  7, 5  8, or 5  9 dots) CGRAM: 16 characters (5  7, 5  8, or 5  9 dots) DCRAM: 64  8 bits ALATCH: 80 bits  Instruction function Display on/off control Smooth up, down, left, and right scrolling of the display  Provides a backup function based on power saving mode  The frame frequency of the common and segment output waveforms can be controlled by instructions.  Built-in display contrast adjustment circuit  Serial data input supports CCB* format communication with the system controller  Independent LCD driver block power supply VLCD  Provides a RES pin for IC internal initialization.  RC oscillator circuit www.onsemi.com PQFP100 14x20 / QIP100E [LC75810E] TQFP100 14x14 / TQIP100 [LC75810T] * Computer Control Bus (CCB) is an ON Semiconductor’s original bus format and the bus addresses are controlled by ON Semiconductor. ORDERING INFORMATION See detailed ordering and shipping information on page 55 of this data sheet. © Semiconductor Components Industries, LLC, 2017 July 2017 - Rev. 1 1 Publication Order Number : LC75810E_T/D LC75810E, LC75810T S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 Pin Assignments (Top view) 80 51 81 50 COM10/S79 COM9/S80 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 VDD VLCD VLCD0 VLCD1 VLCD2 VLCD3 VSS OSC RES CE S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 LC75810E (QFP100E) 100 31 30 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 CL DI S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 1 75 51 76 50 S76 S77 S78 COM10/S79 COM9/S80 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 VDD VLCD VLCD0 VLCD1 VLCD2 VLCD3 VSS OSC RES CE CL DI S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 LC75810T (TQFP100) 100 26 25 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 1 www.onsemi.com 2 LC75810E, LC75810T Specifications Absolute Maximum Ratings at Ta  25C, VSS  0 V Parameter Maximum supply voltage Input voltage Output voltage Output current Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VLCD max VIN1 VIN2 VIN3 VOUT1 VOUT2 IOUT1 IOUT2 Pd max Conditions VDD VLCD CE, CL, DI, RES OSC VLCD1, VLCD2, VLCD3 OSC VLCD0, S1 to S80, COM1 to COM10 S1 to S80 COM1 to COM10 Ratings Unit 0.3 to 7.0 0.3 to 11.0 0.3 to 7.0 0.3 to VDD  0.3 0.3 to VLCD  0.3 0.3 to VDD 0.3 0.3 to VLCD  0.3 300 3 A mA 200 mW Ta  85C 40 to 85 55 to 125 Topr Tstg V V V C C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Allowable Operating Ranges at Ta  40 to  85C, VSS  0 V Parameter Supply voltage Output voltage Input voltage Input high level voltage Input low level voltage Recommended external resistance Recommended external capacitance Guaranteed oscillation range Data setup time Data hold time CE wait time CE setup time CE hold time High level clock pulse width Low level clock pulse width Minimum reset pulse width Ratings typ. Symbol Conditions VDD VLCD0 VLCD1 VLCD2 VLCD3 VIH VIL VDD When the display contrast adjustment circuit is used. When the display contrast adjustment circuit is not used. VLCD0 VLCD1 VLCD2 VLCD3 CE, CL, DI, RES CE, CL, DI, RES Rosc OSC 10 kΩ Cosc OSC 470 pF fosc OSC tds tdh tcp tcs tch CL, DI CL, DI CE, CL CE, CL CE, CL (Figure 2) (Figure 2) (Figure 2) (Figure 2) (Figure 2) 160 160 160 160 160 ns ns ns ns ns tH CL (Figure 2) 160 ns tL CL (Figure 2) 160 ns RES (Figure 3) 1 s VLCD tWRES min. 2.7 max. 6.0 7.0 10.0 4.5 10.0 4.5 3/4 VLCD0 2/4 VLCD0 1/4 VLCD0 0.8 VDD 0 150 300 VLCD VLCD0 VLCD0 VLCD0 6.0 0.2 VDD 600 Unit V V V V V kHz Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 3 LC75810E, LC75810T Electrical Characteristics for the Allowable Operating Ranges Parameter Symbol Conditions Hysteresis VH Input high level current IIH CE, CL, DI, RES CE, CL, DI, RES: VI  6.0 V IIL CE, CL, DI, RES: VI  0 V Input low level current Output high level voltage Output low level voltage Output middle level voltage 1 Oscillator frequency Current drain Ratings min. typ. Unit max. 0.1VDD V 5.0 5.0 VOH1 S1 to S80: IO  20 A VLCD00.6 VOH2 COM1 to COM10: IO  100 A VLCD00.6 A V VOL1 S1 to S80: IO  20 A 0.6 VOL2 COM1 to COM10: IO  100 A 0.6 VMID1 S1 to S80: IO  20 A 2/4 VLCD0 0.6 2/4 VLCD0 0.6 VMID2 COM1 to COM10: IO  100 A 3/4 VLCD0 0.6 3/4 VLCD0 0.6 VMID3 COM1 to COM10: IO  100 A 1/4 VLCD0 0.6 1/4 VLCD0 0.6 fosc OSC: IDD1 VDD: Power saving mode IDD2 VDD: VDD  6.0 V Output open fOSC  300 kHz ILCD1 VLCD: Power saving mode VLCD: VLCD  10.0 V Output open fOSC  300 kHz When the display contrast adjustment circuit is used 450 900 VLCD: VLCD  10.0 V Output open fOSC  300 kHz When the display contrast adjustment circuit is not used 200 400 ILCD2 ILCD3 ROSC  10 k COSC  470 pF 210 A 300 390 V V kHz 5 700 1400 5 A Note 1: Excluding the bias voltage generation divider resistors built into the VLCD0, VLCD1, VLCD2, VLCD3, and VSS pins. (See figure 1.) VLCD CONTRAST ADJUSTER VLCD0 VLCD1 To the common and segment drivers VLCD2 VLCD3 VSS Excluding these resistors Figure 1 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 4 LC75810E/T • When CL is stopped at the low level VIH CE CL VIL tφH VIH 50% VIL tφL tcp tcs tch VIH DI VIL tds • tdh When CL is stopped at the high level VIH CE VIL tφL tφH VIH 50% VIL CL tcp tcs tch VIH DI VIL tds tdh Figure 2 S1 S80/COM9 S79/COM10 S78 COM8 COM1 Block Diagram SEGMENT DRIVER COMMON DRIVER ALATCH 80bits LATCH VDD INSTRUCTION DECODER VLCD CONTRAST ADJUSTER VLCD0 INSTRUCTION REGISTER VLCD1 VLCD2 CLOCK GENERATOR CGROM 5 × 9 × 240 bits ADDRESS COUNTER DCRAM 64 × 8 bits ADDRESS REGISTER SHIFT REGISTER OSC CE CCB INTERFACE RES CL VSS TIMING GENERATOR CGRAM 5 × 9 × 16 bits DI VLCD3 SCROLL COUNTER Page 5 LC75810E/T Pin Functions Active level I/O Handling when unused The S79/COM10 and S80/COM9 pins can be used as common driver outputs under the “set display technique” instruction. − O OPEN Common driver outputs − O OPEN VDD Pin No. Pin Function LC75810E LC75810T S1 to S78 3 to 80 1 to 78 S79/COM10 81 79 S80/COM9 82 80 COM1 to COM8 90 to 83 88 to 81 OSC 98 96 Oscillator connection. An oscillator circuit is formed by connecting an external resistor and capacitor at this pin. − I/O CE 100 98 Serial data transfer inputs. These pins are connected to the microcontroller. H I CL 1 99 Segment driver outputs CE: Chip enable I GND CL: Synchronization clock DI 2 100 DI: Transfer data − I L I GND − O OPEN Reset signal input • When RES is low (VSS) − Display off S1 to S78 = “L” (VSS) S79/COM10 and S80/COM9 = “L” (VSS) COM1 to COM8 = “L” (VSS) RES 99 97 − Serial data transfer is disabled. − The OSC pin oscillator is stopped. • When RES is high (VDD) − Display on after a “display on/off control” (display on state setting) instruction is executed. − Serial data transfers are enabled. − The OSC pin oscillator operates. VLCD0 93 91 LCD drive 4/4 bias voltage (high level) supply pin. The level on this pin can be changed by the display contrast adjustment circuit. However, VLCD0 must be greater than or equal to 4.5 V. Also, external power must not be applied to this pin since the pin circuit includes the display contrast adjustment circuit. VLCD1 94 92 LCD drive 3/4 bias voltage (middle level) supply pin. This pin can be used to supply the 3/4 VLCD0 voltage level externally. − I OPEN VLCD2 95 93 LCD drive 2/4 bias voltage (middle level) supply pin. This pin can be used to supply the 2/4 VLCD0 voltage level externally. − I OPEN VLCD3 96 94 LCD drive 1/4 bias voltage (middle level) supply pin. This pin can be used to supply the 1/4 VLCD0 voltage level externally. − I OPEN VDD 91 89 Logic block power supply connection. Provide a voltage of between 2.7 and 6.0 V. − − − − − − − − − VLCD 92 90 LCD driver block power supply connection. Provide a voltage of between 7.0 and 10.0 V when the display contrast adjustment circuit is used and provide a voltage of between 4.5 and 10.0 V when the circuit is not used. VSS 97 95 Power supply connection. Connect to ground. Page 6 LC75810E/T Block Functions • AC (Address counter) AC is a counter that provides the DCRAM address. The address is automatically modified internally, and the LCD display state is retained. • DCRAM (Data control RAM) DCRAM is the RAM that is used to store display data expressed as 8-bit character codes. (These character codes are converted to 5 × 7, 5 × 8, or 5 × 9 dot matrix character patterns using CGROM or CGRAM.) DCRAM has a capacity of 64 × 8 bits, and can hold 64 characters. The table below lists the correspondence between the 6-bit DCRAM address loaded into AC and the display position on the LCD panel. • For a 64 digits × 1 line display structure (For a “set display technique” instruction with 0Z1 = 0 and 0Z2 = 0) When the DCRAM address loaded into AC is 00H Display digit DCRAM address (hexadecimal) 1 First line 9 10 11 12 13 14 15 16 17 18 61 62 63 64 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 2 3 4 5 6 7 8 3C 3D 3E 3F However, when the display smooth scrolling is performed, the DCRAM address shifts as follows. Display digit DCRAM address (hexadecimal) 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 First line 3F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 Display digit DCRAM address (hexadecimal) 2 First line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 61 62 63 64 Shift to the left 3D 3E 3F 00 by 1 character digit 61 62 63 64 Shift to the right 3B 3C 3D 3E by 1 character digit Note that the display area on the LCD is display digits 1 to 16 on the first line when a display technique is 5 × 7, 5 × 8, or 5 × 9 dots, and it is display digits 1 to 13 on the first line when a display technique is 6 × 7, 6 × 8, or 6 × 9 dots. • For a 32 digits × 2 lines display structure (For a “set display technique” instruction with 0Z1 = 1 and 0Z2 = 0) When the DCRAM address loaded into AC is 00H Display digit DCRAM address (hexadecimal) 9 10 11 12 13 14 15 16 17 18 29 30 31 32 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 1 1C 1D 1E 1F Second line 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 3C 3D 3E 3F First line 2 3 4 5 6 7 8 However, when the display smooth scrolling is performed, the DCRAM address shifts as follows. Display digit DCRAM address (hexadecimal) 1 First line 1 First line 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 Second line 3F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 Display digit DCRAM address (hexadecimal) 3 Second line 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 Display digit DCRAM address (hexadecimal) 2 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 1 First line 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 Second line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 29 30 31 32 Shift to the left 1D 1E 1F 00 by 1 character digit 3D 3E 3F 20 29 30 31 32 Shift to the right 1B 1C 1D 1E by 1 character digit 3B 3C 3D 3E 29 30 31 32 Shift to the up or 3C 3D 3E 3F down by 1 character digit 1C 1D 1E 1F Note that the display area on the LCD is display digits 1 to 16 on the first line when a display technique is 5 × 7, 5 × 8, or 5 × 9 dots, and it is display digits 1 to 13 on the first line when a display technique is 6 × 7, 6 × 8, or 6 × 9 dots. Page 7 LC75810E/T • For a 16 digits × 4 lines display structure (For a “set display technique” instruction with 0Z1 = 0 and 0Z2 = 1) When the DCRAM address loaded into AC is 00H Display digit 1 First line 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Second line 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DCRAM address (hexadecimal) Third line 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Fourth line 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F However, when the display smooth scrolling is performed, the DCRAM address shifts as follows. Display digit 1 First line 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 Shift to the left by Second line 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 10 1 character digit Third line 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 20 DCRAM address (hexadecimal) Fourth line 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 30 Display digit 1 First line 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E Shift to the right by Second line 1F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1 character digit Third line 2F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E DCRAM address (hexadecimal) Fourth line 3F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E Display digit 1 First line 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Second line 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Shift to the up by 1 character digit DCRAM address (hexadecimal) Third line 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Fourth line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Display digit 1 First line 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Second line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Shift to the down by 1 character digit DCRAM address (hexadecimal) Third line 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Fourth line 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Note that the display area on the LCD is display digits 1 to 16 on the first line when a display technique is 5 × 7, 5 × 8, or 5 × 9 dots, and it is display digits 1 to 13 on the first line when a display technique is 6 × 7, 6 × 8, or 6 × 9 dots. Note ∗2: The DCRAM address is expressed in hexadecimal. Least significant bit Most significant bit ↓ LSB MSB DCRAM address DA0 ↓ DA1 DA2 DA3 Hexadecimal DA4 DA5 Hexadecimal Example: When the DCRAM address is 2EH Note ∗3: DA0 DA1 DA2 DA3 DA4 DA5 0 1 1 1 0 1 5 × 7 dots 5 × 8 dots 5 × 9 dots 6 × 7 dots 6 × 8 dots 6 × 9 dots • • • • • • • • • • • • • • • • • • 16-digit display 16-digit display 16-digit display 13-digit display 13-digit display 13-digit display 5 × 7 dots. 4 × 8 dots. 3 × 9 dots. 6 × 7 dots. 6 × 8 dots. 6 × 9 dots. Page 8 LC75810E/T • • • • CGROM (Character generator ROM) CGROM is the ROM that is used to generate the 240 kinds of 5 × 7, 5 × 8, or 5 × 9 dot matrix character patterns from the 8-bit character codes. CGROM has a capacity of 240 × 45 bits. When a character code is written to DCRAM, the character pattern stored in the CGROM corresponding to the character code is displayed at the position on the LCD corresponding to the DCRAM address loaded into AC. CGRAM (Character generator RAM) CGRAM is the RAM to which user programs can freely write arbitrary character patterns. Up to 16 kinds of 5 × 7, 5 × 8, or 5 × 9 dot matrix character patterns can be stored. CGRAM has a capacity of 16 × 45 bits. ALATCH (Additional data latch) ALATCH is the latch that is used to store the ADATA display data for the accessory display. ALATCH has a capacity of 80 bits, and the stored display data is displayed directly without the use of CGROM or CGRAM. SC (Scroll counter) SC is the counter that is used to scroll the display in the left, right, up, or down directions in dot units. Since this function scrolls in dot units, it implements smooth scrolling. Reset Function The LC75810E and LC75810T are reset when a low level is applied to the RES pin at power on and, in normal mode. On a reset the LC75810E and LC75810T create a display with all LCD panels turned off. However, after a reset applications must set the contents of DCRAM, ALATCH, and CGRAM before turning on display with a “display on/off control” instruction since the contents of these memories are undefined. That is, applications must execute the following instructions. • Set display technique • DCRAM data write • ALATCH data write (If ALATCH is used.) • CGRAM data write (IF CGRAM is used.) • Set AC and SC addresses • Set display contrast (If the display contrast adjustment circuit is used.) After executing the above instructions, applications must turn on the display with a “display on/off control” instruction. Note that when applications turn off in the normal mode, applications must turn off the display with a “display on/off control” instruction. (See the detailed instruction descriptions.) Serial Data Transfer Format • When CL is stopped at the low level CE CL DI 0 1 1 1 0 0 1 0 D0 D1 D2 D3 D4 D142 D143 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits • Instruction data Up to 144 bits When CL is stopped at the high level CE CL DI 0 1 1 1 0 0 1 0 D0 D1 D2 D3 D4 D142 D143 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits • • Instruction data Up to 144 bits CCB address: 4EH D0 to D143: Instruction data The data is acquired on the rising edge of the CL signal and latched on the falling edge of the CE signal. When transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set of instruction data until the next instruction data transfer is significantly longer than the instruction execution time. Page 9 X X X X X X X X X X X X X X X X X X X X X CD1 CD2 • • • CD32 CD33 CD34 CD35 CD36 CD37 CD38 CD39 CD40 CD41 CD42 CD43 CD44 CD45 X X X CT0 CT1 CT2 CT3 = 39 μs 162 μs × 210 300 = 232 μs ti μs × 210 300 = ti × 1.43 μs 40.5 μs × 210 300 = 58 μs X X X X CTC X X X X X X X X X 0 0 0 0 0 0 BU 0 ∗6: The execution time must be seen as being 162 µs (when fosc = 300 kHz) if another “display scroll” instruction is executed immediately after a preceding “display scroll” instruction. ∗5: Note that when the power saving mode (BU = 1) is set, the execution time is 27 µs (when fosc = 300 kHz). 210 300 Example: When fosc = 210 kHz X X IM1 IM2 X R/L D/U CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 WM AD1AD2• • •AD24 AD25AD26• • • AD56 AD57 AD58 AD59 AD60 AD61 AD62 AD63 AD64 AD65 AD66 AD67 AD68 AD69 AD70 AD71 AD72 AD73 AD74 AD75 AD76 AD77 AD78 AD79 AD80 ∗4: The execution times listed here apply when fosc = 300 kHz. The execution times differ when the oscillator frequency fosc differs. 27 μs × X DA0 DA1 DA2 DA3 DA4 DA5 VS0 VS1 VS2 VS3 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X SC 1 0 0 0 0 0 0 0 if a “CGRAM data write” instruction is executed in double write mode. (See detailed instruction descriptions.) ∗9, ∗10: Note that the data format differs when a “CGRAM data write” instruction is executed in double write mode (WM = 1). Also note that the execution time is 40.5 µs (when fosc = 300 kHz) Also note that the execution time is ti µs (when fosc = 300 kHz) if a “DCRAM data write” instruction is executed in super-increment mode. (See detailed instruction descriptions.) ∗7, ∗8: Note that the data format differs when a “DCRAM data write” instruction is executed in normal increment mode (IM1 = 1, IM2 = 0) or super-increment mode (IM1 = 0, IM2 = 1). Notes Set display contrast CGRAM data write (∗9) ALATCH data write DCRAM data write (∗7) X A DT1 DT2 FC VA0 VA1 VA2 VA3 HA0 HA1 HA2 X Set AC and SC addresses X HS0 HS1 HS2 OZ1 OZ2 DW 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 Display scroll • • • DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12 DG13 DG14 DG15 DG16 M D0 D1 • • •D55 D56 D57 • • • D79 D80 D81 Display on/off control Set display technique Instruction Instruction Table X: don’t care 0 μs 27 μs/40.5 μs (∗10) 0 μs 27 μs/ti μs (∗8) 27 μs 27 μs/162 μs (∗6) 0 μs/27 μs (∗5) 0 μs Execution time (∗4) LC75810E/T Page 10 LC75810E/T Detailed Instruction Descriptions • Set display technique • • • Code D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 OZ1 OZ2 DW X X X X X DT1 DT2 FC 0 0 0 0 1 X:don’t care DT1, DT2: Set the display technique DT1 DT2 0 0 1 0 Output pins Display technique S80/COM9 S79/COM10 1/8 duty, 1/4 bias drive S80 S79 0 1/9 duty, 1/4 bias drive COM9 S79 1 1/10 duty, 1/4 bias drive COM9 COM10 ∗11: Sn (n = 79, 80): Segment output COMn (n = 9, 10): Common output FC: Set the frame frequency of the common and segment output waveforms Frame frequency FC 1/8 duty, 1/4 bias drive f8[Hz] 1/9 duty, 1/4 bias drive f9[Hz] fosc fosc fosc 3072 3456 3840 0 1 1/10 duty, 1/4 bias drive f10[Hz] fosc fosc fosc 1536 1728 1920 OZ1, OZ2: Set the display structure OZ1 OZ2 0 0 64 digits × 1 line display structure Display structure 1 0 32 digits × 2 lines display structure 0 1 16 digits × 4 lines display structure ∗12: See block functions (DCRAM) DW: Set the dot font width DW Dot font width 0 5-dot font width 16 digits × 1 line (5 × 7 dots), 15 digits × 1 line (5 × 8 or 5 × 9 dots) 1 6-dot font width 13 digits × 1 line (6 × 7, 6 × 8, or 6 × 9 dots) • 5-dot font width (5 × 7, 5 × 8, or 5 × 9 dots) COM1 S76 S77 S78 COM10/S79 COM9/S80 S71 S72 S73 S74 S75 6-dot font width (6 × 7, 6 × 8, or 6 × 9 dots) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S79/COM10 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 • S6 S7 S8 S9 S10 S1 S2 S3 S4 S5 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S79/COM10 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 ∗13: Number of display digits Page 11 LC75810E/T • Display on/off control • • • Code D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 DG1 0 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG1 1 DG1 2 DG1 3 DG1 4 DG1 5 DG1 6 M A SC BU 0 0 1 0 M, A: Specifies the data to be turned on or off. M A 0 0 Display operating state Both MDATA and ADATA are turned off. (The display is forcibly turned off, regardless of the DG1 to DG16 data.) 0 1 Only ADATA is turned on. (The ADATA of display digits specified by the DG1 to DG16 data are turned on.) 1 0 Only MDATA is turned on. (The MDATA of display digits specified by the DG1 to DG16 data are turned on.) 1 1 Both MDATA and ADATA are turned on. (The MDATA and ADATA of display digits specified by the DG1 to DG16 data are turned on.) *14: MDATA, ADATA 5 × 8 dot matrix 5 × 7 dot matrix • • • • • ADATA • • • MDATA • 6 × 7 dot matrix • 5 × 9 dot matrix • • • • • ADATA • • • MDATA • 6 × 8 dot matrix • • • • • • ADATA • • • • • • • • ADATA MDATA 6 × 9 dot matrix • • • • • MDATA • ADATA • • • • • • • MDATA ADATA • • MDATA DG1 to DG16: Specifies the display digit. Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Display digit data DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12 DG13 DG14 DG15 DG16 For example, if DG1 to DG8 are 1, and DG9 to DG16 are 0, then display digits 1 to 8 will be turned on, and display digits 9 to 16 will be turned off (blanked). SC: Controls the common and segment output pins. SC Common and segment output pin states 0 Output of LCD drive waveforms 1 Fixed at the VSS level (all segments off) Note ∗15: When SC is 1, the S1 to S80 and COM1 to COM10 output pins are set to the VSS level, regardless of the M, A, and DG1 to DG16 data. BU: Controls the normal mode and power saving mode. BU 0 Mode Normal mode Power saving mode 1 (In this mode, the OSC pin oscillator is stopped, and the common and segment pins are set to the VSS level. In this mode, instructions other than the “display on/off control” and “set display contrast” instructions cannot be executed. Thus applications must set the IC to normal mode before executing any of the other instructions.) Page 12 LC75810E/T • Display scroll • • • Code D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 HS0 HS1 HS2 X X X X X VS0 VS1 VS2 VS3 X X X X R/L D/U X 0 0 0 1 1 X: don’t care HS0 to HS2: Set the amount of smooth scrolling to be applied to MDATA in the left/right direction. HS0 HS1 HS2 0 0 0 No shift in either the left or right direction Amount of smooth scrolling to be applied to MDATA in the left/right direction 1 0 0 Shift 1 dot to the left or right. (The shift direction (left or right) is specified with the R/L data.) 0 1 0 Shift 2 dots to the left or right. (The shift direction (left or right) is specified with the R/L data.) 1 1 0 Shift 3 dots to the left or right. (The shift direction (left or right) is specified with the R/L data.) 0 0 1 Shift 4 dots to the left or right. (The shift direction (left or right) is specified with the R/L data.) 1 0 1 Shift 5 dots to the left or right. (The shift direction (left or right) is specified with the R/L data.) 0 1 1 Shift 6 dots to the left or right. (The shift direction (left or right) is specified with the R/L data.) VS0 to VS3: Set the amount of smooth scrolling to be applied to MDATA in the up/down direction. VS0 VS1 VS2 VS3 0 0 0 0 No shift in either the up or down direction Amount of smooth scrolling to be applied to MDATA in the up/down direction 1 0 0 0 Shift 1 dot to the up or down. (The shift direction (up or down) is specified with the D/U data.) 0 1 0 0 Shift 2 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) 1 1 0 0 Shift 3 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) 0 0 1 0 Shift 4 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) 1 0 1 0 Shift 5 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) 0 1 1 0 Shift 6 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) 1 1 1 0 Shift 7 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) 0 0 0 1 Shift 8 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) 1 0 0 1 Shift 9 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) (∗16) 0 1 0 1 Shift 10 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) (∗17) Notes: ∗16: This shift cannot be used when MDATA is 5 × 7 or 6 × 7 dots. ∗17: This shift cannot be used when MDATA is 5 × 7, 5 × 8, 6 × 7 or 6 × 8 dots. R/L: Specifies the MDATA shift direction (left or right). D/U: Specifies the MDATA shift direction (up or down). R/L MDATA shift direction (left or right) D/U 0 Shift left 0 MDATA shift direction (up or down) Shift up 1 Shift right 1 Shift down ∗18 Example of the “display scroll” instruction execution Assume that a 32 digits × 2 lines display structure (OZ1 = 1, OZ2 = 0) has been set up with the “set display technique” instruction, and that the following data has been written to DCRAM with the “DCRAM data write” instruction. Display digit First line 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z < > z y x w 1 2 3 4 5 6 7 8 9 a b c d e f g h i j k l m n o p q r s t u v DCRAM data Second line 0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Page 13 LC75810E/T • Display state (1) With no shifting in any direction, left, right, up, or down. HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U 0 0 0 0 0 0 0 X X X: don’t care (5 × 7 dot matrix) (6 × 7 dot matrix) • Display state (2) Shifted 3 dots to the left relative to display state (1) HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U 1 1 0 0 0 0 0 0 0 (5 × 7 dot matrix) (6 × 7 dot matrix) • Display state (3) Shifted 6 dots to the left relative to display state (1) Shifted 3 dots to the left relative to display state (2) HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 (5 × 7 dot matrix) (6 × 7 dot matrix) Page 14 LC75810E/T • Display state (4) Shifted 4 dots to the up relative to display state (1) HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U 0 0 0 0 0 1 0 0 0 (5 × 7 dot matrix) (6 × 7 dot matrix) • Display state (5) Shifted 8 dots to the up relative to display state (1) Shifted 4 dots to the up relative to display state (4) HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 (5 × 7 dot matrix) (6 × 7 dot matrix) • Display state (6) Shifted 3 dots to the left and 4 dots to the up relative to display state (1) HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U 1 1 0 0 0 1 0 0 0 (5 × 7 dot matrix) (6 × 7 dot matrix) Page 15 LC75810E/T • Display state (7) Shifted 6 dots to the left and 8 dots to the up relative to display state (1) Shifted 8 dots to the up relative to display state (3) HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 Shifted 6 dots to the left relative to display state (5) Shifted 3 dots to the left and 4 dots to the up relative to display state (6) HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U HS0 HS1 HS2 VS0 VS1 VS2 VS3 R/L D/U 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 (5 × 7 dot matrix) (6 × 7 dot matrix) • Set AC and SC addresses pattern for SC.> • • • (1B) z (1C) y (1D) x (1E) w (1F) Second line (DCRAM address (hexadecimal)) g (30) h (31) i (32) j (33) k (34) l (35) m (36) n (37) o (38) p (39) q (3A) r (3B) s (3C) t (3D) u (3E) v (3F) Page 17 LC75810E/T • When DA0 to 5 is set to 07H, HA0 to 2 is set to 0H, and VA0 to 3 is set to 0H. HA0 HA1 HA2 VA0 VA1 VA2 VA3 DA0 DA1 DA2 DA3 DA4 DA5 0 0 0 0 0 0 0 1 1 1 0 0 0 (5 × 7 dot matrix) (6 × 7 dot matrix) • When DA0 to 5 is set to 09H, HA0 to 2 is set to 4H, and VA0 to 3 is set to 0H. HA0 HA1 HA2 VA0 VA1 VA2 VA3 DA0 DA1 DA2 DA3 DA4 DA5 0 0 1 0 0 0 0 1 0 0 1 0 0 (5 × 7 dot matrix) (6 × 7 dot matrix) • When DA0 to 5 is set to 0FH, HA0 to 2 is set to 0H, and VA0 to 3 is set to 3H. HA0 HA1 HA2 VA0 VA1 VA2 VA3 DA0 DA1 DA2 DA3 DA4 DA5 0 0 0 1 1 0 0 1 1 1 1 0 0 (5 × 7 dot matrix) (6 × 7 dot matrix) Page 18 LC75810E/T • When DA0 to 5 is set to 14H, HA0 to 2 is set to 1H, and VA0 to 3 is set to 2H. HA0 HA1 HA2 VA0 VA1 VA2 VA3 DA0 DA1 DA2 DA3 DA4 DA5 1 0 0 0 1 0 0 0 0 1 0 1 0 (5 × 7 dot matrix) (6 × 7 dot matrix) • When DA0 to 5 is set to 34H, HA0 to 2 is set to 3H, and VA0 to 3 is set to 6H. HA0 HA1 HA2 VA0 VA1 VA2 VA3 DA0 DA1 DA2 DA3 DA4 DA5 1 1 0 0 1 1 0 0 0 1 0 1 1 (5 × 7 dot matrix) (6 × 7 dot matrix) • DCRAM data write • • • Code D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D 132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X IM1 IM2 X 0 0 1 0 1 X: don’t care DA0 to DA5: DCRAM address DA0 DA1 DA2 DA3 DA4 LSB DA5 MSB ↑ ↑ Least significant bit Most significant bit AC0 to AC7: DCRAM data (character code) AC0 AC1 LSB ↑ Least significant bit AC2 AC3 AC4 AC5 AC6 AC7 MSB ↑ Most significant bit This instruction writes the 8 bits of data AC0 to AC7 to DCRAM. This data is a character code, and is converted to a 5 × 7, 5 × 8, or 5 × 9 dot matrix display data using CGROM or CGRAM. Page 19 LC75810E/T IM1 and IM2: Sets the method of writing data to DCRAM IM1 IM2 0 0 Normal DCRAM data write (Specifies the DCRAM address and writes the DCRAM data.) 1 0 Normal increment mode DCRAM data write (Increments the DCRAM address by +1 each time data is written to DCRAM.) 0 1 Super-increment mode DCRAM data write (Writes 2 to 16 characters of DCRAM data in a single operation.) ∗21 • DCRAM data write method DCRAM data write method when IM1 is 0 and IM2 is 0. CE CCB address CCB address DI CCB address CCB address (1) (1) (1) (1) 24 bits 24 bits 24 bits 24 bits DCRAM Instruction execution time (27 µs) • Instruction execution time (27 µs) DCRAM data write finishes Instruction execution time (27 µs) DCRAM data write finishes Instruction execution time (27 µs) DCRAM data write finishes DCRAM data write finishes DCRAM data write method when IM1 is 1 and IM2 is 0. (Instructions other than the “DCRAM data write” instruction cannot be executed.) CE CCB address CCB address DI CCB address CCB address CCB address CCB address (2) (3) (3) (3) (3) 24 bits 8 bits 8 bits 8 bits 8 bits Instruction execution time (27 µs) Instruction execution time (27 µs) Instruction execution time (27 µs) Instruction execution time (27 µs) (4) 16 bits DCRAM Instruction execution time (27 µs) DCRAM data write finishes DCRAM data write finishes DCRAM data write finishes DCRAM data write finishes Instruction execution time (27 µs) DCRAM data write finishes DCRAM data write finishes (Instructions other than the “DCRAM data write” instruction cannot be executed.) • DCRAM data write method when IM1 is 0 and IM2 is 1. CE CCB address CCB address DI CCB address (5) (5) (5) n bit n bit n bit Instruction execution time (ti μs) Instruction execution time (ti μs) Instruction execution time (ti μs) DCRAM DCRAM data write finishes DCRAM data write finishes DCRAM data write finishes n ti = 13.5μs × ( -1) (n = 8m + 16, m is an integer between 2 and 16 that is the number of characters written as DCRAM 8 data.) For example When n = 32 bits (m = 2): ti = 40.5 μs (when fosc = 300 kHz) When n = 80 bits (m = 8): ti = 121.5 μs (when fosc = 300 kHz) When n = 144 bits (m = 16): ti = 229.5 μs (when fosc = 300 kHz) Note that the instruction execution time of 27 μs and ti values in µs apply when fosc = 300 kHz, and that these times will differ when the oscillator frequency fosc differs. Page 20 LC75810E/T Data format (1) (24 bits) Code D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X 0 0 X 0 0 1 0 1 X: don’t care Data format (2) (24 bits) Code D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X 1 0 X 0 0 1 0 1 X: don’t care Data format (3) (8 bits) Code D136 D137 D138 D139 D140 D141 D142 D143 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 Data format (4) (16 bits) Code D128 D129 D130 D131 D132 D133 D134 D135 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 D136 D137 0 0 D138 X D139 D140 0 D141 0 1 D142 D143 0 1 X:don’t care Data format (5) (n bits) Code Dz Dz+1 Dz+2 Dz+3 Dz+4 Dz+5 Dz+6 Dz+7 AC01 AC11 AC21 AC31 AC41 AC51 AC61 AC71 ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ D112 D113 D114 D115 D116 D117 D118 D119 AC0m-1 AC1m-1 AC2m-1 AC3m-1 AC4m-1 AC5m-1 AC6m-1 AC7m-1 Code D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 AC0m AC1m AC2m AC3m AC4m AC5m AC6m AC7m DA01 DA11 DA21 DA31 DA41 DA51 X X 0 1 X 0 0 1 0 1 X: don’t care Here, n = 8m + 16, z = 128 - 8m (m is an integer between 2 and 16 that is the number of characters written as DCRAM data.) Correspondence between the DCRAM address and the DCRAM data DCRAM address DCRAM data DA01 to DA51 AC01 to AC71 (DA01 to DA51) + 1 AC02 to AC72 (DA01 to DA51) + 2 AC03 to AC73 (DA01 to DA51) + (m − 3) AC0m-2 to AC7m-2 (DA01 to DA51) + (m − 2) AC0m-1 to AC7m-1 (DA01 to DA51) + (m − 1) AC0m to AC7m Page 21 LC75810E/T Example 1: When n = 32 bits (m = 2: 2 characters DCRAM data write operation) Code D112 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127 AC01 AC11 AC21 AC31 AC41 AC51 AC61 AC71 AC02 AC12 AC22 AC32 AC42 AC52 AC62 AC72 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 DA01 DA11 DA21 DA31 DA41 DA51 X X 0 1 X 0 0 1 0 1 Code X: don’t care Correspondence between the DCRAM address and the DCRAM data DCRAM address DCRAM data DA01 to DA51 AC01 to AC71 (DA01 to DA51) + 1 AC02 to AC72 Example 2: When n = 80 bits (m = 8: 8 characters DCRAM data write operation) Code D64 D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 AC01 AC11 AC21 AC31 AC41 AC51 AC61 AC71 AC02 AC12 AC22 AC32 AC42 AC52 AC62 AC72 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 AC03 AC13 AC23 AC33 AC43 AC53 AC63 AC73 AC04 AC14 AC24 AC34 AC44 AC54 AC64 AC74 D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 AC05 AC15 AC25 AC35 AC45 AC55 AC65 AC75 AC06 AC16 AC26 AC36 AC46 AC56 AC66 AC76 D112 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127 AC07 AC17 AC27 AC37 AC47 AC57 AC67 AC77 AC08 AC18 AC28 AC38 AC48 AC58 AC68 AC78 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 DA01 DA11 DA21 DA31 DA41 DA51 X X 0 1 X 0 0 1 0 1 Code Code Code Code X: don’t care Correspondence between the DCRAM address and the DCRAM data DCRAM address DCRAM data DA01 to DA51 AC01 to AC71 (DA01 to DA51) + 1 AC02 to AC72 (DA01 to DA51) + 2 AC03 to AC73 (DA01 to DA51) + 3 AC04 to AC74 (DA01 to DA51) + 4 AC05 to AC75 (DA01 to DA51) + 5 AC06 to AC76 (DA01 to DA51) + 6 AC07 to AC77 (DA01 to DA51) + 7 AC08 to AC78 Page 22 LC75810E/T Example 3: When n = 144 bits (m = 16: 16 characters DCRAM data write operation) Code D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 AC00 AC10 AC20 AC30 AC40 AC50 AC60 AC70 AC01 AC11 AC21 AC31 AC41 AC51 AC61 AC71 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 AC03 AC13 AC23 AC33 AC43 AC53 AC63 AC73 AC04 AC14 AC24 AC34 AC44 AC54 AC64 AC74 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 AC05 AC15 AC25 AC35 AC45 AC55 AC65 AC75 AC06 AC16 AC26 AC36 AC46 AC56 AC66 AC76 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 AC07 AC17 AC27 AC37 AC47 AC57 AC67 AC77 AC08 AC18 AC28 AC38 AC48 AC58 AC68 AC78 D64 D65 D66 D67 D68 D69 D70 D71 D73 D74 D75 D76 D77 D78 D79 AC09 AC19 AC29 AC39 AC49 AC59 AC69 AC79 D80 D81 D82 D83 D84 D85 D86 D87 Code Code Code Code D72 AC010 AC110 AC210 AC310 AC410 AC510 AC610 AC710 Code D88 D89 D90 D91 D92 D93 D94 D95 AC011 AC111 AC211 AC311 AC411 AC511 AC611 AC711 AC012 AC112 AC212 AC312 AC412 AC512 AC612 AC712 Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 AC013 AC113 AC213 AC313 AC413 AC513 AC613 AC713 AC014 AC114 AC214 AC314 AC414 AC514 AC614 AC714 Code D112 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127 AC015 AC115 AC215 AC315 AC415 AC515 AC615 AC715 AC016 AC116 AC216 AC316 AC416 AC516 AC616 AC716 Code D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 DA01 DA11 DA21 DA31 DA41 DA51 X X 0 1 X 0 0 1 0 1 X: don’t care Correspondence between the DCRAM address and the DCRAM data DCRAM address DCRAM data DCRAM address DCRAM data DA01 to DA51 AC01 to AC71 (DA01 to DA51) + 8 AC09 to AC79 (DA01 to DA51) + 1 AC02 to AC72 (DA01 to DA51) + 9 AC010 to AC710 (DA01 to DA51) + 2 AC03 to AC73 (DA01 to DA51) + 10 AC011 to AC711 (DA01 to DA51) + 3 AC04 to AC74 (DA01 to DA51) + 11 AC012 to AC712 (DA01 to DA51) + 4 AC05 to AC75 (DA01 to DA51) + 12 AC013 to AC713 (DA01 to DA51) + 5 AC06 to AC76 (DA01 to DA51) + 13 AC014 to AC714 (DA01 to DA51) + 6 AC07 to AC77 (DA01 to DA51) + 14 AC015 to AC715 (DA01 to DA51) + 7 AC08 to AC78 (DA01 to DA51) + 15 AC016 to AC716 Page 23 LC75810E/T • ALATCH data write • • • • • Code D56 D57 D58 D59 D60 D61 D62 D63 D64 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 D88 D89 D90 D91 D92 D93 D94 D95 AD33 AD34 AD35 AD36 AD37 AD38 AD39 AD40 D104 D105 D106 D107 D108 D109 D110 D111 D112 AD49 AD50 AD51 AD52 AD53 AD54 AD55 AD56 AD57 AD58 AD59 AD60 AD61 AD62 AD63 AD64 D120 D121 D122 D123 D124 D125 D126 D127 D128 AD65 AD66 AD67 AD68 AD69 AD70 AD71 AD72 AD73 AD74 AD75 AD76 AD77 AD78 AD79 AD80 D136 D137 D138 D139 D140 D141 D142 D143 X X X 0 0 1 1 0 AD10 AD11 AD12 AD13 AD14 AD15 AD16 Code D80 D81 D82 D83 D84 D85 D86 D87 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD32 Code D96 D97 D98 D99 D100 D101 D102 D103 AD41 AD42 AD43 AD44 AD45 AD46 AD47 AD48 Code D113 D114 D115 D116 D117 D118 D119 Code D129 D130 D131 D132 D133 D134 D135 Code X: don’t care AD1 to AD80: ADATA display data In addition to the 5 × 7, 5 × 8, 5 × 9, 6 × 7, 6 × 8, or 6 × 9 dot matrix display data (MDATA), the LC75810E/T also supports an accessory display of 5 or 6 segments (ADATA) at each display digit, and allows arbitrary data to be displayed directly without going through CGROM or CGRAM. The figure below shows the correspondence between that data and the display. When ADn = 1 (where n is an integer between 1 and 80), the segment corresponding to that data will be turned on. AD71 AD72 AD73 AD74 AD75 AD76 AD77 AD78 AD79 AD80 S76 S77 S78 COM10/S79 COM9/S80 AD6 AD7 AD8 AD9 AD10 S71 S72 S73 S74 S75 AD1 AD2 AD3 AD4 AD5 S6 S7 S8 S9 S10 COM1 S1 S2 S3 S4 S5 5-dot font width (5 × 7, 5 × 8, or 5 × 9 dots) COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S79/COM10 Page 24 LC75810E/T 6-dot font width (6 × 7, 6 × 8, or 6 × 9 dots) COM1 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD67 AD68 AD69 AD70 AD71 AD72 AD73 AD74 AD75 AD76 AD77 AD78 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S79/COM10 Correspondence between ADATA and the output pins ADATA Corresponding output pin ADATA Corresponding output pin ADATA Corresponding output pin AD1 S1 AD31 S31 AD61 S61 AD2 S2 AD32 S32 AD62 S62 AD3 S3 AD33 S33 AD63 S63 AD4 S4 AD34 S34 AD64 S64 AD5 S5 AD35 S35 AD65 S65 AD6 S6 AD36 S36 AD66 S66 AD7 S7 AD37 S37 AD67 S67 AD8 S8 AD38 S38 AD68 S68 AD9 S9 AD39 S39 AD69 S69 AD10 S10 AD40 S40 AD70 S70 AD11 S11 AD41 S41 AD71 S71 AD12 S12 AD42 S42 AD72 S72 AD13 S13 AD43 S43 AD73 S73 AD14 S14 AD44 S44 AD74 S74 AD15 S15 AD45 S45 AD75 S75 AD16 S16 AD46 S46 AD76 S76 AD17 S17 AD47 S47 AD77 S77 AD18 S18 AD48 S48 AD78 S78 AD19 S19 AD49 S49 AD79 S79 AD20 S20 AD50 S50 AD80 S80 AD21 S21 AD51 S51 AD22 S22 AD52 S52 AD23 S23 AD53 S53 AD24 S24 AD54 S54 AD25 S25 AD55 S55 AD26 S26 AD56 S56 AD27 S27 AD57 S57 AD28 S28 AD58 S58 AD29 S29 AD59 S59 AD30 S30 AD60 S60 Page 25 LC75810E/T • CGRAM data write • • • • • Code D80 D81 D82 D83 D84 D85 D86 D87 D88 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD31 CD32 D112 D113 D114 D115 D116 D117 D118 D119 CD33 CD34 CD35 CD36 CD37 CD38 CD39 CD40 CD41 CD42 CD43 CD44 CD45 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 WM X X 0 CD10 CD11 CD12 CD13 CD14 CD15 CD16 Code D104 D105 D106 D107 D108 D109 D110 D111 Code D120 D121 D122 D123 D124 D125 D126 D127 X X X D140 D141 D142 D143 0 1 1 1 Code X:don’t care CA0 to CA7: CGRAM address CA0 CA1 CA2 CA3 CA4 LSB CA5 CA6 CA7 MSB ↑ ↑ Least significant bit Most significant bit CD1 to CD45: CGRAM data (5 × 7, 5 × 8, or 5 × 9 dot matrix display data) The bit CDn (where n is an integer between 1 and 45) corresponds to the 5 × 7, 5 × 8, or 5 × 9 dot matrix display data. The figure below shows that correspondence. When CDn is 1, the dots which correspond to that data will be turned on. CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 CD11 CD12 CD13 CD14 CD15 CD16 CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD31 CD32 CD33 CD34 CD35 CD36 CD37 CD38 CD39 CD40 CD41 CD42 CD43 CD44 CD45 *22: CD1 to CD35: 5 × 7 dot matrix display data CD1 to CD40: 5 × 8 dot matrix display data CD1 to CD45: 5 × 9 dot matrix display data Page 26 LC75810E/T WM: Sets the method of writing data to CGRAM. WM CGRAM data write method 0 Normal CGRAM data write (Specifies a CGRAM address and write a CGRAM data.) 1 Double write mode CGRAM data write (Specifies two CGRAM addresses and writes two CGRAM data to those addresses.) ∗23: • CGRAM data write method when WM is 0. CE CCB address CCB address CCB address CCB address (6) (6) (6) (6) 64 bits 64 bits 64 bits 64 bits DI CGRAM Instruction execution time (27 µs) • Instruction execution time (27 µs) CGRAM data write finishes Instruction execution time (27 µs) CGRAM data write finishes Instruction execution time (27 µs) CGRAM data write finishes CGRAM data write finishes CGRAM data write method when WM is 1. CE CCB address CCB address CCB address (7) (7) (7) 120 bits 120 bits 120 bits DI CGRAM Instruction execution time (40.5μs) Instruction execution time (40.5μs) CGRAM data write finishes Instruction execution time (40.5μs) CGRAM data write finishes CGRAM data write finishes Note that the instruction execution times of 27 µs and 40.5 µs apply when fosc = 300 kHz, and that these times will differ when the oscillator frequency fosc differs. Data format (6) (64 bits) Code D80 D81 D82 D83 D84 D85 D86 D87 D88 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD31 CD32 D112 D113 D114 D115 D116 D117 D118 D119 CD33 CD34 CD35 CD36 CD37 CD38 CD39 CD40 CD41 CD42 CD43 CD44 CD45 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 0 X X 0 CD10 CD11 CD12 CD13 CD14 CD15 CD16 Code D104 D105 D106 D107 D108 D109 D110 D111 Code D120 D121 D122 D123 D124 D125 D126 D127 X X X D140 D141 D142 D143 0 1 1 1 Code X: don’t care Page 27 LC75810E/T Data format (7) (120 bits) Code D24 D25 D26 D27 D28 D29 D30 D31 D32 CD11 CD21 CD31 CD41 CD51 CD61 CD71 CD81 CD91 D40 D41 D42 D43 D44 D45 D46 D47 D33 D34 D35 D36 D37 D38 D39 CD101 CD111 CD121 CD131 CD141 CD151 CD161 Code D48 D49 D50 D51 D52 D53 D54 D55 CD171 CD181 CD191 CD201 CD211 CD221 CD231 CD241 CD251 CD261 CD271 CD281 CD291 CD301 CD311 CD321 Code D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 CD331 CD341 CD351 CD361 CD371 CD381 CD391 CD401 CD411 CD421 CD431 CD441 CD451 D69 D70 D71 X X X Code D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 CA01 CA11 CA21 CA31 CA41 CA51 CA61 CA71 CD12 CD22 CD32 CD42 CD52 CD62 CD72 CD82 D88 D89 D90 D91 D92 D93 D94 D95 D97 D98 D99 D100 D101 D102 D103 Code D96 CD92 CD102 CD112 CD122 CD132 CD142 CD152 CD162 CD172 CD182 CD192 CD202 CD212 CD222 CD232 CD242 D104 D105 Code D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 CD252 CD262 CD272 CD282 CD292 CD302 CD312 CD322 CD332 CD342 CD352 CD362 CD372 CD382 CD392 CD402 Code D120 D121 D122 D123 D124 CD412 CD422 CD432 CD442 CD452 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 X X X CA02 CA12 CA22 CA32 CA42 CA52 CA62 CA72 Code D136 D137 D138 D139 D140 D141 D142 D143 1 X X 0 0 1 1 1 X: don’t care Correspondence between the CGRAM address and the CGRAM data CGRAM address CGRAM data CA01 to CA71 CD11 to CD451 CA02 to CA72 CD12 to CD452 Page 28 LC75810E/T • Set display contrast • • • • • Code D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 CT0 CT1 CT2 CT3 X X X X CTC X X 0 1 0 0 0 X:don’t care CT0 to CT3: Sets the display contrast (11 steps) CT0 CT1 CT2 CT3 0 0 0 0 0.94VLCD = VLCD-(0.03VLCD × 2) LCD drive 4/4 bias voltage supply VLCD0 level 1 0 0 0 0.91VLCD = VLCD-(0.03VLCD × 3) 0 1 0 0 0.88VLCD = VLCD-(0.03VLCD × 4) 1 1 0 0 0.85VLCD = VLCD-(0.03VLCD × 5) 0 0 1 0 0.82VLCD = VLCD-(0.03VLCD × 6) 1 0 1 0 0.79VLCD = VLCD-(0.03VLCD × 7) 0 1 1 0 0.76VLCD = VLCD-(0.03VLCD × 8) 1 1 1 0 0.73VLCD = VLCD-(0.03VLCD × 9) 0 0 0 1 0.70VLCD = VLCD-(0.03VLCD × 10) 1 0 0 1 0.67VLCD = VLCD-(0.03VLCD × 11) 0 1 0 1 0.64VLCD = VLCD-(0.03VLCD × 12) CTC: Sets the display contrast adjustment circuit state CTC Display contrast adjustment circuit state 0 The display contrast adjustment circuit is disabled, and the VLCD0 pin level is forced to the VLCD level. 1 The display contrast adjustment circuit operates, and the display contrast is adjusted. Note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it is also possible to be adjusted by varying the voltage level on the LCD driver block power supply VLCD pin. However, the level on VLCD0 must be greater than or equal to 4.5V. Page 29 LC75810E/T Notes on the Power On and Power Off Sequences The following sequences must be observed when power is turned on and off. (See Figure 3.) • At power on: Logic block power supply (VDD) on → LCD driver block power supply (VLCD) on. • At power off: LCD driver block power supply (VLCD) off → Logic block power supply (VDD) off. However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off at the same time. t2 t1 ≈ t3 ≈ VDD VLCD VIL Instruction execution VIH ≈ ≈ ≈ ≈ RES ≈ tWRES Initial state settings Display state Display on Display off “Display on/off control” Display off “Display on/off control” instruction execution instruction execution (Turning the display on) (Turning the display off) Initial state setting • Set display technique • DCRAM data write • t1 ≥ 0 • ALATCH data write (If ALATCH is used) • t2 > 0 • t3 ≥ 0 (t2 > t3) • tWRES • • • 1μs min • CGRAM data write (If CGRAM is used) • Set AC and SC addresses • Set display contrast (If the display contrast adjustment circuit is used) Figure 3 Page 30 LC75810E/T 1/8 Duty, 1/4 Bias Drive Technique VLCD0 VLCD1 COM1 VLCD2 VLCD3 VSS VLCD0 VLCD1 COM2 VLCD2 VLCD3 VSS VLCD0 VLCD1 COM8 VLCD2 VLCD3 VSS VLCD0 LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned off VLCD1 VLCD2 VLCD3 VSS VLCD0 VLCD1 LCD driver output when only LCD segments corresponding to COM1 are turned on VLCD2 VLCD3 VSS VLCD0 VLCD1 LCD driver output when only LCD segments corresponding to COM2 are turned on VLCD2 VLCD3 VSS VLCD0 LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned on VLCD1 VLCD2 VLCD3 VSS T8 8 T8 T8 = 1 f8 When a “set display technique” instruction with FC = 0 is executed: f8 = When a “set display technique” instruction with FC = 1 is executed: f8 = fosc 3072 fosc 1536 Page 31 LC75810E/T 1/9 Duty, 1/4 Bias Drive Technique VLCD0 VLCD1 VLCD2 COM1 VLCD3 VSS VLCD0 VLCD1 COM2 VLCD2 VLCD3 VSS VLCD0 VLCD1 VLCD2 COM9 VLCD3 VSS VLCD0 LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned off VLCD1 VLCD2 VLCD3 VSS VLCD0 VLCD1 LCD driver output when only LCD segments corresponding to COM1 are turned on VLCD2 VLCD3 VSS VLCD0 VLCD1 LCD driver output when only LCD segments corresponding to COM2 are turned on VLCD2 VLCD3 VSS VLCD0 LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned on VLCD1 VLCD2 VLCD3 VSS T9 9 T9 T9= 1 f9 When a “set display technique” instruction with FC = 0 is executed: f9 = When a “set display technique” instruction with FC = 1 is executed: f9 = fosc 3456 fosc 1728 Page 32 LC75810E/T 1/10 Duty, 1/4 Bias Drive Technique VLCD0 VLCD1 COM1 VLCD2 VLCD3 VSS VLCD0 VLCD1 VLCD2 COM2 VLCD3 VSS VLCD0 VLCD1 COM10 VLCD2 VLCD3 VSS VLCD0 LCD driver output when all LCD segments corresponding to COM1 to COM10 are turned off VLCD1 VLCD2 VLCD3 VSS VLCD0 VLCD1 LCD driver output when only LCD segments corresponding to COM1 are turned on VLCD2 VLCD3 VSS VLCD0 VLCD1 LCD driver output when only LCD segments corresponding to COM2 are turned on VLCD2 VLCD3 VSS VLCD0 LCD driver output when all LCD segments corresponding to COM1 to COM10 are turned on VLCD1 VLCD2 VLCD3 VSS T10 10 T10 T10 = 1 f10 When a “set display technique” instruction with FC = 0 is executed: f10 = When a “set display technique” instruction with FC = 1 is executed: f10 = fosc 3840 fosc 1920 Page 33 LC75810E/T Sample Application Circuit 1 5 × 7 dot matrix, 1/8 duty, 1/4 bias drive (for use with normal panels) LCD panel +5 V +8 V VDD COM1 VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 VLCD OPEN VLCD0 VLCD1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 VLCD2 C C C VLCD3 C ≥ 0.047 μF OSC RES From the CE CL DI controller S76 S77 S78 COM10/S79 COM9/S80 Sample Application Circuit 2 5 × 7 dot matrix, 1/8 duty, 1/4 bias drive (for use with large panels) LCD panel +5 V +8 V VDD COM1 VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 VLCD VLCD0 R VLCD1 R VLCD2 R VLCD3 C C C R C ≥ 0.047 μF 10 kΩ ≥ R ≥ 2.2 kΩ OSC From the RES controller CE CL DI S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S76 S77 S78 COM10/S79 COM9/S80 Page 34 LC75810E/T Sample Application Circuit 3 5 × 8 dot matrix, 1/9 duty, 1/4 bias drive (for use with normal panels) LCD panel +5 V +8 V VDD COM1 VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 VLCD OPEN VLCD0 VLCD1 VLCD2 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 VLCD3 C C C C ≥ 0.047 μF OSC RES From the controller CE CL DI S76 S77 S78 COM10/S79 Sample Application Circuit 4 5 × 8 dot matrix, 1/9 duty, 1/4 bias drive (for use with large panels) LCD panel +5 V +8 V VDD COM1 VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 VLCD VLCD0 R VLCD1 R VLCD2 R VLCD3 C C ≥ 0.047 μF 10 kΩ ≥ R ≥ 2.2 kΩ From the controller C C R OSC RES CE CL DI S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S76 S77 S78 COM10/S79 Page 35 LC75810E/T Sample Application Circuit 5 5 × 9 dot matrix, 1/10 duty, 1/4 bias drive (for use with normal panels) LCD panel +5 V +8 V VDD COM1 VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S79/COM10 VLCD OPEN VLCD0 VLCD1 VLCD2 VLCD3 C C C C ≥ 0.047 μF OSC S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 RES From the controller CE CL DI S76 S77 S78 Sample Application Circuit 6 5 × 9 dot matrix, 1/10 duty, 1/4 bias drive (for use with large panels) LCD panel +5 V +8 V VDD COM1 VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S79/COM10 VLCD VLCD0 R VLCD1 R VLCD2 R VLCD3 C C ≥ 0.047 μF 10 kΩ ≥ R ≥ 2.2 kΩ From the controller C C R OSC RES CE CL DI S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S76 S77 S78 Page 36 LC75810E/T Sample Application Circuit 7 6 × 7 dot matrix, 1/8 duty, 1/4 bias drive (for use with normal panels) LCD panel +5 V +8 V VDD COM1 VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 VLCD OPEN VLCD0 VLCD1 VLCD2 VLCD3 C C C C ≥ 0.047 μF OSC RES From the controller CE CL DI S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S73 S74 S75 S76 S77 S78 COM10/S79 COM9/S80 OPEN Sample Application Circuit 8 6 × 7 dot matrix, 1/8 duty, 1/4 bias drive (for use with large panels) LCD panel +5 V +8 V VDD COM1 VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 VLCD VLCD0 R VLCD1 R VLCD2 R VLCD3 C C ≥ 0.047 μF 10 kΩ ≥ R ≥ 2.2 kΩ From the controller C C R OSC RES CE CL DI S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S73 S74 S75 S76 S77 S78 COM10/S79 COM9/S80 OPEN Page 37 LC75810E/T Sample Application Circuit 9 6 × 8 dot matrix, 1/9 duty, 1/4 bias drive (for use with normal panels) LCD panel +5 V +8 V VDD COM1 VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 VLCD OPEN VLCD0 VLCD1 VLCD2 VLCD3 C C C C ≥ 0.047 μF OSC RES From the controller CE CL DI S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S73 S74 S75 S76 S77 S78 COM10/S79 OPEN Sample Application Circuit 10 6 × 8 dot matrix, 1/9 duty, 1/4 bias drive (for use with large panels) LCD panel +5 V VDD COM1 VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 VLCD +8 V VLCD0 R VLCD1 R VLCD2 R VLCD3 C C ≥ 0.047 μF 10 kΩ ≥ R ≥ 2.2 kΩ From the controller C C R OSC RES CE CL DI S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S73 S74 S75 S76 S77 S78 COM10/S79 OPEN Page 38 LC75810E/T Sample Application Circuit 11 6 × 9 dot matrix, 1/10 duty, 1/4 bias drive (for use with normal panels) LCD panel +5 V +8 V VDD COM1 VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S79/COM10 VLCD OPEN VLCD0 VLCD1 VLCD2 VLCD3 C C C C ≥ 0.047μF OSC RES From the controller CE CL DI S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S73 S74 S75 S76 S77 S78 Sample Application Circuit 12 6 × 9 dot matrix, 1/10 duty, 1/4 bias drive (for use with large panels) LCD panel +5 V +8 V VDD COM1 VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S79/COM10 VLCD VLCD0 R VLCD1 R VLCD2 R VLCD3 C C ≥ 0.047 μF 10 kΩ ≥ R ≥ 2.2 kΩ From the controller C C R OSC RES CE CL DI S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S73 S74 S75 S76 S77 S78 Page 39 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 No. Instruction (hexadecimal) MSB 0 5 0 0 DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) 3 DCRAM data write (normal increment mode) 1 Set display technique 1 8 5 7 3 C 0 3 9 0 F 9 E 1 1 0 Power application (initialization with the RES pin) 3 3 3 3 4 4 2 4 4 2 4 5 4 4 A 8 D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 LSB Display Continued on next page. Writes the display data “1” to DCRAM address 0EH. Writes the display data “8” to DCRAM address 0DH. Writes the display data “5” to DCRAM address 0CH. Writes the display data “7” to DCRAM address 0BH. Writes the display data “C” to DCRAM address 0AH. Writes the display data “L” to DCRAM address 09H. Writes the display data “ ” to DCRAM address 08H. Writes the display data “C” to DCRAM address 07H. Writes the display data “I” to DCRAM address 06H. Writes the display data “ ” to DCRAM address 05H. Writes the display data “O” to DCRAM address 04H. Writes the display data “Y” to DCRAM address 03H. Writes the display data “N” to DCRAM address 02H. Writes the display data “A” to DCRAM address 01H. Writes the display data “S” to DCRAM address 00H. Sets to the 1/8 duty 1/4 bias display technique, the 32 digits × 2 lines display structure, and the 5-dot font width at each digit. Initializes the IC. The display is in the off state. Operation Sample 1 showing the Correspondence between Instructions and the Display (Using the LC75810-8725 with a 5 × 7 dots, 16 digits × 1 line display) LC75810E/T Page 40 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 No. Instruction (hexadecunal) MSB DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) 0 0 0 0 0 2 5 6 9 2 4 0 4 3 C 0 0 2 2 2 2 2 5 4 5 4 5 4 2 4 4 4 2 3 D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 LSB Continued from perceding page. Display Continued on next page. Writes the display data “ ” to DCRAM address 1FH. Writes the display data “ ” to DCRAM address 1EH. Writes the display data “ ” to DCRAM address 1DH. Writes the display data “ ” to DCRAM address 1CH. Writes the display data “ ” to DCRAM address 1BH. Writes the display data “R” to DCRAM address 1AH. Writes the display data “E” to DCRAM address 19H. Writes the display data “V” to DCRAM address 18H. Writes the display data “I” to DCRAM address 17H. Writes the display data “R” to DCRAM address 16H. Writes the display data “D” to DCRAM address 15H. Writes the display data “ ” to DCRAM address 14H. Writes the display data “D” to DCRAM address 13H. Writes the display data “C” to DCRAM address 12H. Writes the display data “L” to DCRAM address 11H. Writes the display data “ ” to DCRAM address 10H. Writes the display data “0” to DCRAM address 0FH. Operation LC75810E/T Page 41 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 No. Instruction (hexadecimal) MSB 0 0 0 0 0 Set AC and SC addresses 0 0 2 DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) 0 0 5 0 9 4 0 8 9 2 4 1 D 0 4 F 4 2 A 4 5 5 5 2 5 4 5 5 4 4 2 5 4 4 D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 LSB Continued from preceding page. Display Page 42 Continued on next page. Sets AC to the DCRAM address 00H, SC to the horizontal dot address 0H and the vertical dot address 0H. Writes the display data “ ” to DCRAM address 2FH. Writes the display data “E” to DCRAM address 2EH. Writes the display data “P” to DCRAM address 2DH. Writes the display data “Y” to DCRAM address 2CH. Writes the display data “T” to DCRAM address 2BH. Writes the display data “ ” to DCRAM address 2AH. Writes the display data “X” to DCRAM address 29H. Writes the display data “I” to DCRAM address 28H. Writes the display data “R” to DCRAM address 27H. Writes the display data “T” to DCRAM address 26H. Writes the display data “A” to DCRAM address 25H. Writes the display data “M” to DCRAM address 24H. Writes the display data “ ” to DCRAM address 23H. Writes the display data “T” to DCRAM address 22H. Writes the display data “O” to DCRAM address 21H. Writes the display data “D” to DCRAM address 20H. Operation LC75810E/T 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 No. Instruction (hexadecimal) MSB 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 F F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll F Display on/off control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 C C C C C C C C C C C C C C C C 4 D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 LSB Continued from preceding page Display Continued on next page. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Turns on the LCD for all digits (16 digits) in MDATA. Operation LC75810E/T Page 43 82 81 80 79 78 77 76 75 74 73 72 71 70 69 No. Instruction (hexadecimal) MSB 0 0 0 0 0 F 0 0 0 0 0 0 3 3 3 3 3 3 0 0 0 0 0 0 0 2 2 2 2 0 F 0 0 Set AC and SC addresses F Display on/off control 0 Display on/off control 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Set AC and SC addresses 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 F 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 0 0 0 0 0 0 0 0 0 0 0 2 4 4 C C C C 2 C C C C C C D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 LSB Continued from preceding page. Display Sets AC to the DCRAM address 00H, SC to the horizontal dot address 0H and the vertical dot address 0H. Turns on the LCD for all digits (16 digits) in MDATA. Sets to power saving mode, turns off the LCD for all digits. Shifts just the MDATA display two dots to the up. Shifts just the MDATA display two dots to the up. Shifts just the MDATA display two dots to the up. Shifts just the MDATA display two dots to the up. Sets AC to the DCRAM address 00H, SC to the horizontal dot address 0H and the vertical dot address 0H. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Operation LC75810E/T Page 44 35 to 50 19 to 34 3 to 18 No. 35 to 50 19 to 34 3 to 18 No. Instruction MSB 4 0 7 D88 to D91 LSB 4 0 3 5 2 3 D92 to D95 4 2 5 4 4 4 4 3 E 5 4 4 2 4 5 Instruction 0 4 9 D 0 F 0 2 9 4 4 2 4 1 4 4 DCRAM data write (super-increment mode) 2 DCRAM data write (super-increment mode) 4 DCRAM data write (super-increment mode) MSB 5 5 4 9 0 5 5 2 3 0 0 8 1 3 0 0 2 0 5 5 4 0 DCRAM data write (super-increment mode) 2 DCRAM data write (super-increment mode) 3 DCRAM data write (super-increment mode) 2 2 3 0 0 0 2 1 0 2 2 2 A A A D96 to D99 D100 to D103 D104 to D107 D108 to D111 D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 F C 1 5 4 4 9 6 0 4 5 2 Display 8 5 C 5 4 4 0 2 3 2 5 4 Writes the display data "D" "O" "T" " " "M" "A" "T" "R" "I" "X" " " "T" "Y" "P" "E" " " to DCRAM addresses 20H to 2FH. Writes the display data " " "L" "C" "D" " " "D" "R" "I" "V" "E" "R" " " " " " " " " " " to DCRAM addresses 10H to 1FH. Writes the display data "S" "A" "N" "Y" "O" " " "I" "C" " " "L" "C" "7" "5" "8" "1" "0" to DCRAM addresses 00H to 0FH. 2 9 3 D 0 t o D 3 D 4 t o D 7 D8 to D11 D12 to D15 D16 to D19 D20 to D23 D24 to D27 D28 to D31 D32 to D35 D36 to D39 D40 to D43 D44 to D47 D48 to D51 D52 to D55 D56 to D59 D60 to D63 D64 to D67 D68 to D71 D72 to D75 D76 to D79 D80 to D83 D84 to D87 LSB Note that the sample below shows 48 characters of DCRAM data being divided into 3 separate “DCRAM data write” instruction executions in the super-increment mode. ∗25: The data format will have the following format if super-increment mode is used for the “DCRAM data write” instructions (numbers 3 to 50) in sample 1 showing the correspondence between instructions and the display. Notes ∗24: In sample 1 showing the correspondence between instructions and the display, a 16 digits × 1 line 5 × 7 dot matrix LCD is used, and CGRAM and ALATCH are not used. LC75810E/T Page 45 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 No Instruction (hexadecimal) MSB 0 5 0 0 DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) 3 DCRAM data write (normal increment mode) 5 Set display technique Power application (initialization with the RES pin) C 0 0 1 8 5 7 3 C 0 F 9 E 1 1 0 4 2 3 3 3 3 3 4 4 2 4 5 4 4 A 8 D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 LSB Display Continued on next page. Writes the display data "L" to DCRAM address 0EH. Writes the display data " " to DCRAM address 0DH. Writes the display data "0" to DCRAM address 0CH. Writes the display data "1" to DCRAM address 0BH. Writes the display data "8" to DCRAM address 0AH. Writes the display data "5" to DCRAM address 09H. Writes the display data "7" to DCRAM address 08H. Writes the display data "C" to DCRAM address 07H. Writes the display data "L" to DCRAM address 06H. Writes the display data " " to DCRAM address 05H. Writes the display data "O" to DCRAM address 04H. Writes the display data "Y" to DCRAM address 03H. Writes the display data "N" to DCRAM address 02H. Writes the display data "A" to DCRAM address 01H. Writes the display data "S" to DCRAM address 00H. Sets to the 1/8 duty 1/4 bias display technique, the 32 digits × 2 lines display structure, and the 6-dot font width at each digit. Initializes the IC. The display is in the off state. Operation Sample 2 showing the Correspondence between Instructions and the Display (Using the LC75810-8725 with a 6 × 7 dots, 13 digits × 1 line display) LC75810E/T Page 46 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 No. Instruction (hexadecimal) MSB 2 4 0 2 DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) 4 DCRAM data write (normal increment mode) 0 DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) 1 D 0 4 F 1 0 0 2 5 6 9 2 4 0 4 3 4 4 2 5 4 A A 2 5 4 5 4 5 4 2 4 4 D112 toD115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 LSB Continued from preceding page. Display Continued on next page. Writes the display data "A" to DCRAM address 25H. Writes the display data "M" to DCRAM address 24H. Writes the display data " " to DCRAM address 23H. Writes the display data "T" to DCRAM address 22H. Writes the display data "O" to DCRAM address 21H. Writes the display data "D" to DCRAM address 20H. Writes the display data " " to DCRAM address 19H. Writes the display data " " to DCRAM address 18H. Writes the display data "R" to DCRAM address 17H. Writes the display data "E" to DCRAM address 16H. Writes the display data "V" to DCRAM address 15H. Writes the display data "I" to DCRAM address 14H. Writes the display data "R" to DCRAM address 13H. Writes the display data "D" to DCRAM address 12H. Writes the display data " " to DCRAM address 11H. Writes the display data "D" to DCRAM address 10H. Writes the display data "C" to DCRAM address 0FH. Operation LC75810E/T Page 47 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 No. Instruction (hexadecimal) MSB 0 0 3 3 3 3 3 3 3 3 F 0 2 0 F 0 0 0 0 0 0 0 Page 48 0 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll F Display on/off control 0 0 0 0 0 0 0 0 0 1 0 Set AC and SC addresses 0 DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) DCRAM data write (normal increment mode) 0 0 0 0 0 0 0 0 1 0 0 0 0 8 9 2 4 C C C C C C C C 4 2 A 2 2 5 4 5 5 D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 LSB Continued from preceding page. Display Continued on next page. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Turns on the LCD for all digits (13 digits) in MDATA . Sets AC to the DCRAM address 00H, SC to the horizontal dot address 0H and the vertical dot address 0H. Writes the display data " " to DCRAM address 2CH. Writes the display data " " to DCRAM address 2BH. Writes the display data " " to DCRAM address 2AH. Writes the display data "X" to DCRAM address 29H. Writes the display data "I" to DCRAM address 28H. Writes the display data "R" to DCRAM address 27H. Writes the display data "T" to DCRAM address 26H. Operation LC75810E/T 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 No. Instruction (hexadecimal) MSB 0 0 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 Page 49 0 2 Display scroll 0 Display scroll 0 Set AC and SC addresses 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 Display scroll 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C C 2 C C C C C C C C C C C C C C D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 LSB Continued from preceding page. Display Continued on next page. Shifts just the MDATA display two dots to the up. Shifts just the MDATA display two dots to the up. Sets AC to the DCRAM address 00H, SC to the horizontal dot address 0H and the vertical dot address 0H. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Shifts just the MDATA display three dots to the left. Operation LC75810E/T 73 72 71 70 69 No. Instruction (hexadecimal) MSB 0 0 0 F 0 0 0 2 2 0 F 0 0 Set AC and SC addresses F Display on/off control 0 Display on/off control 0 Display scroll 0 Display scroll 0 1 0 0 0 0 1 8 0 0 2 4 4 C C D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 LSB Continued from preceding page. Display Sets AC to the DCRAM address 00H, SC to the horizontal dot address 0H and the vertical dot address 0H. Turns on the LCD for all digits (13 digits) in MDATA. Sets to power saving mode, turns off the LCD for all digits. Shifts just the MDATA display two dots to the up. Shifts just the MDATA display two dots to the up. Operation LC75810E/T Page 50 29 to 41 16 to 28 3 to 15 No. 29 to 41 16 to 28 3 to 15 No. Instruction MSB 4 2 5 F C 1 4 3 E Instruction 4 4 4 5 4 4 0 4 9 MSB 2 4 5 0 0 1 2 2 3 3 0 0 2 D 0 0 2 0 2 DCRAM data write (super-increment mode) 0 DCRAM data write (super-increment mode) 0 DCRAM data write (super-increment mode) 2 2 2 A A A D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 LSB 4 0 3 0 2 C 4 4 2 4 1 4 Operation 4 DCRAM data write (super-increment mode) 2 DCRAM data write (super-increment mode) 4 DCRAM data write (super-increment mode) 5 5 4 2 9 3 5 4 4 Writes the display data "D" "O" "T" " " "M" "A" "T" "R" "I" "X" " " " " " " to DCRAM addresses 20H to 2CH. Writes the display data " " "L" "C" "D" " " "D" "R" "I" "V" "E" "R" " " " " to DCRAM addresses 0DH to 19H. Writes the display data "S" "A" "N" "Y" "O" " " "L" "C" "7" "5" "8" "1" "0" to DCRAM addresses 00H to 0CH. D 0 F 9 6 7 4 5 3 8 5 5 5 4 3 0 2 8 2 5 3 D24 to D27 D28 to D31 D32 to D35 D36 to D39 D40 to D43 D44 to D47 D48 to D51 D52 to D55 D56 to D59 D60 to D63 D64 to D67 D68 to D71 D72 to D75 D76 to D79 D80 to D83 D84 to D87 D88 to D91 D92 to D95 D96 to D99 D100 to D103 D104 to D107 D108 to D111 LSB Notes ∗26: In sample 2 showing the correspondence between instructions and the display, a 13 digits × 1 line 6 × 7 dot matrix LCD is used, and CGRAM and ALATCH are not used. ∗27: The data format will have the following format if super-increment mode is used for the “DCRAM data write” instructions (numbers 3 to 41) in sample 2 showing the correspondence between instructions and the display. Note that the sample below shows 39 characters of DCRAM data being divided into 3 separate “DCRAM data write” instruction executions in the super-increment mode. LC75810E/T Page 51 LC75810E/T Page 52 LC75810E, LC75810T Package Dimensions unit : mm [LC75810E] PQFP100 14x20 / QIP100E CASE 122BV ISSUE A 0.80.2 23.20.2 17.20.2 100 14.00.1 20.00.1 12 0.65 0.30.05 0.10.1 (2.7) 3.0 MAX (0.58) 0.15 0.13 0 to 10 0.10 SOLDERING FOOTPRINT* 22.30 GENERIC MARKING DIAGRAM* 16.30 (Unit: mm) 0.43 XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data 1.30 0.65 XXXXXXXXX YMDDD NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 53 *This information is generic. LC75810E, LC75810T Package Dimensions unit : mm [LC75810T] TQFP100 14x14 / TQFP100 CASE 932AY ISSUE A 0.50.2 16.00.2 16.00.2 100 14.00.1 14.00.1 1 2 0.5 0.125 0.2 0.10 (1.0) 0 to 10  0.10.1 1.2 MAX (1.0) 0.10 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 15.40 XXXXXXXX YMDDD 15.40 (Unit: mm) XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data 0.50 0.28 1.00 *This information is generic. NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 54 LC75810E, LC75810T ORDERING INFORMATION Device Package Shipping (Qty / Packing) LC75810E-8725-E PQFP100 14x20 / QIP100E (Pb-Free) 250 / Tray Foam LC75810T-8725-E TQFP100 14x14 / TQFP100 (Pb-Free) 450 / Tray JEDEC LC75810TS-8725-E TQFP100 14x14 / TQFP100 (Pb-Free) 90 / Tray JEDEC ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. 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