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LE25U20AFD
Serial Flash Memory
2 Mb (256K x 8)
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Overview
The LE25U20AFD is a serial interface-compatible flash memory device
with a 256K 8-bit configuration. It uses a single 2.5 V power supply.
While making the most of the features inherent to a serial flash memory
device, the LE25U20AFD is housed in an 8-pin ultra-miniature package.
These features make this device ideally suited to storing program codes in
applications such as portable information devices, which are required to
have increasingly more compact dimensions. Moreover, by using the small
sector erase function this product is also suitable for the parameter or the
date storage usage with comparatively little rewriting times that becomes a
capacity shortage in EEPROM.
VSOIC8 NB
Features
Read / write operations enabled by single 2.5 V power supply :
2.30 to 3.60 V supply voltage range
Operating frequency
: 30 MHz
Temperature range
: 40 to +85C
Serial interface
: SPI mode 0, mode 3 supported
Sector size
: 4K bytes/small sector, 64K bytes/sector
Small sector erase, sector erase, chip erase functions
Page program function (256 bytes / page)
Block protect function
Status functions
: Ready/busy information, protect information
Highly reliable read/write
Number of rewrite times : 100,000 times
Small sector erase time : 40 ms (typ), 150 ms (max)
Sector erase time
: 80 ms (typ), 250 ms (max)
Chip erase time
: 250 ms (typ), 1.6 s (max)
Page program time
: 4.0 ms / 256 bytes (typ), 5.0 ms / 256 bytes (max)
Data retention period
: 20 years
Package
: VSOIC8 NB
* This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 21 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
February 2017 - Rev. 0
1
Publication Order Number :
LE25U20AFD/D
LE25U20AFD
Package Dimensions
unit : mm
VSOIC8 NB
CASE 753AA
ISSUE O
D
A
8
NOTE 5
2X
0.10 C D
5
F
NOTE 6
E
E1
A1
NOTE 4
L2
2X 4 TIPS
0.20 C
L
4
1
NOTE 5
8X
B
b
0.25
C
DETAIL A
M
SEATING
PLANE
C A-B D
TOP VIEW
2X
NOTE 4
D
0.10 C A-B
0.10 C
A
DETAIL A
8X
0.10 C
e
SIDE VIEW
C
SEATING
PLANE
END VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.10mm IN EXCESS OF MAXIMUM MATERIAL
CONDITION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH,
PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15mm PER SIDE. DIMENSION E DOES
NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25mm PER
SIDE. DIMENSIONS D AND E ARE DETERMINED AT
DATUM F.
5. DATUMS A AND B ARE TO BE DETERMINED AT
DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
DIM
A
A1
b
c
D
E
E1
e
L
L2
MILLIMETERS
MIN
MAX
0.65
0.85
0.05
0.31
0.51
0.17
0.25
4.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
0.40
1.27
0.25 BSC
GENERIC
MARKING DIAGRAM*
8
RECOMMENDED
SOLDERING FOOTPRINT*
XXXXXXXXX
ALYWX
1
8X 1.52
7.00
XXXXX
A
L
Y
W
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
(Note: Microdot may be in either location)
1
8X
0.60
1.27
PITCH
DIMENSION: MILLIMETERS
*This information is generic. Please refer
to device data sheet for actual part
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
or not be present.
Figure 1 Pin Assignments
CS
1
8
VDD
SO
2
7
HOLD
WP
3
6
SCK
VSS
4
5
SI
Top view
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2
LE25U20AFD
Figure 2 Block Diagram
2M Bit
Flash EEPROM
Cell Array
XDECODER
ADDRESS
BUFFERS
&
LATCHES
Y-DECODER
I/O BUFFERS
&
DATA LATCHES
CONTROL
LOGIC
SERIAL INTERFACE
CS
SCK
SI
SO
WP
HOLD
Table 1 Pin Description
Symbol
SCK
Pin Name
Serial clock
Description
This pin controls the data input/output timing.
The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is
output synchronized to the falling edge of the serial clock.
SI
Serial data input
The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the
serial clock.
SO
Serial data output
CS
Chip select
The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock.
The device becomes active when the logic level of this pin is low; it is deselected and placed in standby
status when the logic level of the pin is high.
WP
Write protect
The status register write protect (SRWP) takes effect when the logic level of this pin is low.
HOLD
Hold
Serial communication is suspended when the logic level of this pin is low.
VDD
Power supply
This pin supplies the 2.30 to 3.60 V supply voltage.
VSS
Ground
This pin supplies the 0 V supply voltage.
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3
LE25U20AFD
Device Operation
The LE25U20AFD features electrical on-chip erase functions using a single 2.5 V power supply, that have been
added to the EPROM functions of the industry standard that support serial interfaces. Interfacing and control are
facilitated by incorporating the command registers inside the chip. The read, erase, program and other required
functions of the device are executed through the command registers. The command addresses and data input in
accordance with "Table 2 Command Settings" are latched inside the device in order to execute the required
operations. "Figure 3 Serial Input Timing" shows the timing waveforms of the serial data input. First, at the falling
CS edge the device is selected, and serial input is enabled for the commands, addresses, etc. These inputs are
introduced internally in sequence starting with bit 7 in synchronization with the rising SCK edge. At this time,
output pin SO is in the high-impedance state. The output pin is placed in the low-impedance state when the data is
output in sequence starting with bit 7 synchronized to the falling clock edge during read, status register read and
silicon ID. Refer to "Figure 4 Serial Output Timing" for the serial output timing.
The LE25U20AFD supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is
automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of
SCK is high.
Table 2 Command Settings
Command
Read
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
03h
A23-A16
A15-A8
A7-A0
0Bh
A23-A16
A15-A8
A7-A0
D7h/20h
A23-A16
A15-A8
A7-A0
Sector erase
D8h
A23-A16
A15-A8
A7-A0
Chip erase
C7h
Page program
02h
A23-A16
A15-A8
A7-A0
Write enable
06h
X
X
Small sector erase
Write disable
04h
Power down
B9h
Status register read
05h
Status register write
01h
Read silicon ID 1
9Fh
Read silicon ID 2
ABh
Exit power down mode
ABh
5th bus cycle
6th bus cycle
Nth bus cycle
PD *
PD *
X
PD *
DATA
X
Explanatory notes for Table 2
"X" signifies "don't care" (that is to say, any value may be input).
The "h" following each code indicates that the number given is in hexadecimal notation.
Addresses A23 to A18 for all commands are "Don't care".
In order for commands other than the read command to be recognized, CS must rise after all the bus cycle input.
*: "PD" stands for page program data.
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4
LE25U20AFD
Figure 3 Serial Input Timing
tCPH
CS
tCSH
tCLHI
tCSS
tCLLO tCSH
tCSS
SCK
tDS
SI
SO
tDH
DATA VALID
High Impedance
High Impedance
Figure 4 Serial Output Timing
CS
SCK
tCLZ
SO
tHO
tCHZ
DATA VALID
tV
SI
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5
LE25U20AFD
Description of Commands and Their Operations
"Table 2 Command Settings" provides a list and overview of the commands. A detailed description of the functions
and operations corresponding to each command is presented below.
1. Read
There are two read commands, the 4 bus cycle read command and 5 bus cycle read command. Consisting of the first
through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses following (03h), and the data in
the designated addresses is output synchronized to SCK. The data is output from SO on the falling clock edge of
fourth bus cycle bit 0 as a reference. "Figure 5-a 4 Bus Read" shows the timing waveforms.
Consisting of the first through fifth bus cycles, the 5 bus cycle read command inputs the 24-bit addresses and 8
dummy bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a
reference. "Figure 5-b 5 Bus Read" shows the timing waveforms. The only difference between these two commands
is whether the dummy bits in the fifth bus cycle are input.
When SCK is input continuously after the read command has been input and the data in the designated addresses has
been output, the address is automatically incremented inside the device while SCK is being input, and the
corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the
highest address (3FFFFh), the internal address returns to the lowest address (00000h), and data output is continued.
By setting the logic level of CS to high, the device is deselected, and the read cycle ends. While the device is
deselected, the output pin SO is in a high-impedance state.
Figure 5-a 4 Bus Read
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
31 32
23 24
39 40
47
Mode0
8CLK
SI
03h
Add.
Add.
Add.
N
High Impedance
SO
DATA
MSB
N+1
N+2
DATA
DATA
MSB
MSB
Figure 5-b 5 Bus Read
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55
Mode0
8CLK
SI
SO
0Bh
Add.
Add.
High Impedance
Add.
X
N
N+1
N+2
DATA
DATA
DATA
MSB
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6
MSB
MSB
LE25U20AFD
2. Status Registers
The status registers hold the operating and setting statuses inside the device, and this information can be read (status
register read) and the protect information can be rewritten (status register write). There are 8 bits in total, and "Table
3 Status registers" gives the significance of each bit.
Table 3 Status Registers
Bit
Bit0
Bit1
Name
RDY
Logic
Function
0
Ready
Power-on Time Information
1
Erase/Program
0
Write disabled
1
Write enabled
0
WEN
0
0
Bit2
Bit3
BP0
Nonvolatile information
1
Block protect information
0
See status register descriptions on BP0 and BP1.
BP1
Nonvolatile information
1
Bit4
0
Reserved bits
Bit5
Bit6
Bit7
0
0
0
Status register write enabled
1
Status register write disabled
SRWP
Nonvolatile information
2-1. Status Register Read
The contents of the status registers can be read using the status register read command. This command can be
executed even during the following operations.
Small sector erase, sector erase, chip erase
Page program
Status register write
"Figure 6 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus
cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the
clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the
first to be output, and each time one clock is input, all the other bits up to RDY (bit 0) are output in sequence,
synchronized to the falling clock edge. If the clock input is continued after RDY (bit 0) has been output, the data is
output by returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock
input is continued. The data can be read by the status register read command at any time (even during a program or
erase cycle).
Figure 6 Status Register Read
CS
Mode 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23
Mode 0
8CLK
SI
SO
05h
High Impedance
DATA
MSB
DATA
MSB
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DATA
MSB
LE25U20AFD
2-2. Status Register Write
The information in status registers BP0, BP1, and SRWP can be rewritten using the status register write command.
RDY, WEN, bit 4, bit 5, and bit 6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, and
SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at
power-down. "Figure 7 Status Register Write" shows the timing waveforms of status register write, and Figure 20
shows a status register write flowchart. Consisting of the first and second bus cycles, the status register write
command initiates the internal write operation at the rising CS edge after the data has been input following (01h).
Erase and program are performed automatically inside the device by status register write so that erasing or other
processing is unnecessary before executing the command. By the operation of this command, the information in bits
BP0, BP1, and SRWP can be rewritten. Since bits RDY (bit 0), WEN (bit 1), bit 4, bit 5, and bit 6 of the status
register cannot be written, no problem will arise if an attempt is made to set them to any value when rewriting the
status register. Status register write ends can be detected by RDY of status register read. Information in the status
registers can be rewritten 1,000 times (min.). To initiate status register write, the logic level of the WP pin must be
set high and status register WEN must be set to "1".
Figure 7 Status Register Write
Self-timed
Write Cycle
tSRW
CS
tWPH
tWPS
WP
Mode3
SCK
0 1 2 3 4 5 6 7 8
15
Mode0
8CLK
SI
SO
01h
DATA
High Impedance
2-3. Contents of Each Status Register
RDY (bit 0)
The RDY register is for detecting the write (program, erase and status register write) end. When it is "1", the device
is in a busy state, and when it is "0", it means that write is completed.
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LE25U20AFD
WEN (bit 1)
The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will
not perform the write operation even if the write command is input. If it is set to "1", the device can perform write
operations in any area that is not block-protected.
WEN can be controlled using the write enable and write disable commands. By inputting the write enable command
(06h), WEN can be set to "1"; by inputting the write disable command (04h), it can be set to "0". In the following
states, WEN is automatically set to "0" in order to protect against unintentional writing.
At power-on
Upon completion of small sector erase, sector erase or chip erase
Upon completion of page program
Upon completion of status register write
* If a write operation has not been performed inside the LE25U20AFD because, for instance, the command input for
any of the write operations (small sector erase, sector erase, chip erase, page program, or status register write) has
failed or a write operation has been performed for a protected address, WEN will retain the status established prior
to the issue of the command concerned. Furthermore, its state will not be changed by a read operation.
BP0, BP1 (bits 2, 3)
Block protect BP0 and BP1 are status register bits that can be rewritten, and the memory space to be protected can
be set depending on these bits. For the setting conditions, refer to "Table 4 Protect level setting conditions".
Table 4 Protect Level Setting Conditions
Status Register Bits
Protect Level
Protected Area
BP1
BP0
0 (Whole area unprotected)
0
0
None
1 (1/4 protected)
0
1
30000h to 3FFFFh
2 (1/2 protected)
1
0
20000h to 3FFFFh
3 (Whole area protected)
1
1
00000h to 3FFFFh
* Chip erase is enabled only when the protect level is 0.
SRWP (bit 7)
Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten.
When SRWP is "1" and the logic level of the WP pin is low, the status register write command is ignored, and status
registers BP0, BP1, and SRWP are protected. When the logic level of the WP pin is high, the status registers are not
protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 5 SRWP setting
conditions".
Table 5 SRWP Setting Conditions
WP Pin
SRWP
Status Register Protect State
0
Unprotected
0
1
Protected
0
Unprotected
1
Unprotected
1
Bits 4, Bits 5, and Bits 6 are reserved bits, and have no significance.
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LE25U20AFD
3. Write Enable
Before performing any of the operations listed below, the device must be placed in the write enable state. Operation
is the same as for setting status register WEN to "1", and the state is enabled by inputting the write enable command.
"Figure 8 Write Enable" shows the timing waveforms when the write enable operation is performed. The write
enable command consists only of the first bus cycle, and it is initiated by inputting (06h).
Small sector erase, sector erase, chip erase
Page program
Status register write
4. Write Disable
The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 9 Write
Disable" shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is
initiated by inputting (04h). The write disable state (WEN "0") is exited by setting WEN to "1" using the write
enable command (06h).
Figure 8 Write Enable
Figure 9 Write Disable
CS
CS
Mode3
SCK
Mode3
0 1 2 3 4 5 6 7
SCK
Mode0
Mode0
8CLK
SI
8CLK
SI
06h
High Impedance
SO
0 1 2 3 4 5 6 7
04h
High Impedance
SO
5. Power-down
The power-down command sets all the commands, with the exception of the silicon ID read command and the
command to exit from power-down, to the acceptance prohibited state (power-down). "Figure 10 Power-down"
shows the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by
inputting (B9h). However, a power-down command issued during an internal write operation will be ignored. The
power-down state is exited using the power-down exit command (power-down is exited also when one bus cycle or
more of the silicon ID read command (ABh) has been input). "Figure 11 Exiting from Power-down" shows the
timing waveforms of the power-down exit command.
Figure 10 Power-down
Figure 11 Exiting from Power-down
Power down
mode
Power down
mode
CS
CS
tPRB
tDP
Mode3
SCK
Mode3
0 1 2 3 4 5 6 7
SCK
Mode0
8CLK
SI
SO
0 1 2 3 4 5 6 7
Mode0
8CLK
SI
B9h
High Impedance
SO
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10
ABh
High Impedance
LE25U20AFD
6. Small Sector Erase
Small sector erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of
4K bytes. "Figure 12 Small Sector Erase" shows the timing waveforms, and Figure 21 shows a small sector erase
flowchart. The small sector erase command consists of the first through fourth bus cycles, and it is initiated by
inputting the 24-bit addresses following (D7h/20h). Addresses A17 to A12 are valid, and Addresses A23 to A18 are
"don't care". After the command has been input, the internal erase operation starts from the rising CS edge, and it
ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register
RDY.
Figure 12 Small Sector Erase
Self-timed
Erase Cycle
tSSE
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
Mode0
8CLK
SI
D7h/20h
Add.
Add.
Add.
High Impedance
SO
7. Sector Erase
Sector erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 64K bytes.
"Figure 13 Sector Erase" shows the timing waveforms, and Figure 21 shows a sector erase flowchart. The sector
erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses
following (D8h). Addresses A17 to A16 are valid, and Addresses A23 to A18 are "don't care". After the command
has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control
exercised by the internal timer. Erase end can also be detected using status register RDY.
Figure 13 Sector Erase
Self-timed
Erase Cycle
tSE
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
Mode0
8CLK
SI
SO
D8h
Add.
Add.
Add.
High Impedance
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31
LE25U20AFD
8. Chip Erase
Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 14 Chip Erase" shows the
timing waveforms, and Figure 21 shows a chip erase flowchart. The chip erase command consists only of the first
bus cycle, and it is initiated by inputting (C7h). After the command has been input, the internal erase operation starts
from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also
be detected using status register RDY.
Figure 14 Chip Erase
Self-timed
Erase Cycle
tCHE
CS
Mode3
SCK
0 1 2 3 4 5 6 7
Mode0
8CLK
SI
C7h
High Impedance
SO
9. Page Program
Page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page
(page addresses: A17 to A8). Before initiating page program, the data on the page concerned must be erased using
small sector erase, sector erase, or chip erase. "Figure 15 Page Program" shows the page program timing waveforms,
and Figure 22 shows a page program flowchart. After the falling CS, edge, the command (02H) is input followed by
the 24-bit addresses. Addresses A17 to A0 are valid. The program data is then loaded at each rising clock edge until
the rising CS edge, and data loading is continued until the rising CS edge. If the data loaded has exceeded 256 bytes,
the 256 bytes loaded last are programmed. The program data must be loaded in 1-byte increments, and the program
operation is not performed at the rising CS edge occurring at any other timing. The page program time is 2.0 ms
(typ.) when 256 bytes (1 page) are programmed at one time.
Figure 15 Page Program
Self-timed
Program Cycle
tPP
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47
2079
Mode0
8CLK
SI
SO
02h
Add.
Add.
Add.
High Impedance
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12
PD
PD
PD
LE25U20AFD
10. Silicon ID Read
Silicon ID read is an operation that reads the manufacturer code and device code information. The silicon ID read
command is not accepted during writing.
Two methods are used for silicon ID reading. The first method involves inputting the 9Fh command: the setting is
completed with only the first bus cycle input, and in subsequent bus cycles the manufacturer code 62h, 2 bytes of
device ID code (Memory type, Memory capacity) and reserved code are repeatedly output in succession so long as
the clock input is continued. Refer to "Figure 16-a Silicon ID Read 1" for the waveforms. "Table 6_1 Silicon ID
Read 1" lists the silicon ID read1 codes.
The second method involves inputting the ABh command. This command consists of the first through fourth bus
cycles, and the 1 byte silicon ID can be read when 24 dummy bits are input after (ABh). Refer to "Figure 16-b
Silicon ID Read 2" for the waveforms. "Table 6_2 Silicon ID Read 2" lists the silicon ID read2 code. If, after the
device code has been read, the SCK input is continued, the device code is output repeatedly.
The data is output starting with the falling clock edge of the fourth bus cycle bit 0, and silicon ID reading ends at the
rising CS edge.
Table 6_1 Silicon ID Read 1
Table 6_2 Silicon ID Read 2
Output Code
Output Code
Manufacturer code
2Byte
Device ID
1Byte
62h
Memory Type
Memory Capacity
code
44h
Device ID
06h
12h(2MBit)
Reserved code
00h
Figure 16-a Silicon ID Read 1
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
39
31 32
Mode0
8CLK
SI
9Fh
High Impedance
SO
62h
MSB
06h
MSB
12h
MSB
00h
MSB
06h
MSB
Figure 16-b Silicon ID Read 2
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
31 32
23 24
39
Mode0
8CLK
SI
SO
ABh
X
X
High Impedance
X
44h
MSB
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44h
MSB
LE25U20AFD
11. Hold Function
Using the HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure 17
HOLD" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the
logic level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is
high, HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is
exited and serial communication is reset at the rising CS edge. In the hold status, the SO output is in the highimpedance state, and SI and SCK are "don't care".
Figure 17 HOLD
Active
CS
Active
HOLD
tHS
tHS
SCK
tHH
tHH
HOLD
tHHZ
tHLZ
High Impedance
SO
12. Power-on
In order to protect against unintentional writing, CS must be kept at VCC At power-on. After power-on, the supply
voltage has stabilized at 2.30 V or higher, wait for 100 s (tPU_READ) before inputting the command to start a read
operation. Similarly, wait for 10ms (tPU_WRITE) after the voltage has stabilized before inputting the command to
start a write operation.
Figure 18 Power-on Timing
Program, Erase and Write Command not Allowed
Full Access Allowed
VDD
Chip selection not Allowed
Read Access Allowed
VDD(Max)
VDD(Min)
tPU_READ
tPU_WRITE
0V
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14
LE25U20AFD
13. Hardware Data Protection
In order to protect against unintentional writing at power-on, the LE25U20AFD incorporates a power-on reset
function. The following conditions must be met in order to ensure that the power reset circuit will operate stably.
No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period.
Figure 19 Power-down Timing
Program, Erase and Write Command not Allowed
VDD
VDD(Max)
No Device Access Allowed
VDD(Min)
tPU_READ
tPU_WRITE
tPD
0V
vBOT
14. Software Data Protection
The LE25U20AFD eliminates the possibility of unintentional operations by not recognizing commands under the
following conditions.
When a write command is input and the rising CS edge timing is not in a bus cycle (8 CLK units of SCK)
When the page program data is not in 1-byte increments
When the status register write command is input for 2 bus cycles or more
15. Decoupling Capacitor
A 0.1 F ceramic capacitor must be provided to each device and connected between VDD and VSS in order to
ensure that the device will operate stably.
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15
LE25U20AFD
Specifications
Absolute Maximum Ratings
Parameter
Symbol
Conditions
Ratings
unit
Maximum supply voltage
VDD max
With respect to VSS
0.5 to +4.6
DC voltage (all pins)
VIN/VOUT
With respect to VSS
0.5 to VDD+0.5
V
Storage temperature
Tstg
55 to +150
C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Operating Conditions
Parameter
Symbol
Conditions
Ratings
unit
Operating supply voltage
VDD
2.30 to 3.60
V
Operating ambient temperature
Topr
40 to +85
C
Allowable DC Operating Conditions
Parameter
Read mode operating current
Symbol
ICCR
Write mode operating current
(erase+page program)
ICCW
CMOS standby current
ISB
Power-down standby current
IDSB
Input leakage current
ILI
Output leakage current
ILO
Input low voltage
Input high voltage
VIL
VIH
Output low voltage
VOL
Conditions
Ratings
min
typ
CS = 0.1VDD, HOLD = WP = 0.9VDD
SI = 0.1VDD / 0.9VDD, SO = open
operating frequency = 30 MHz,
VDD = VDD max
6
mA
VDD = VDD max, tSSE = 40 ms,
tSE = 80 ms, tCHE = 160 ms,
tPP = 5.0 ms
15
mA
CS = HOLD = WP = VDD,
SI = VSS / VDD, SO = open,
VDD = VDD max
50
A
CS = HOLD = WP = VDD,
SI = VSS / VDD, SO = open,
VDD = VDD max
10
A
VIN = VSS to VDD, VDD = VDD max
VIN = VSS to VDD, VDD = VDD max
VDD = VDD max
VDD = VDD min
IOL = 100 A, VDD = VDD min
0.3
0.7VDD
2
A
2
A
0.3VDD
VDD+0.3
V
VOH
IOH = 100 A, VDD = VDD min
V
0.2
IOL = 1.6 mA, VDD = VDD min
Output high voltage
unit
max
V
0.4
VCC0.2
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Power-on Timing
Parameter
Ratings
Symbol
min
unit
max
Time from power-on to read operation
tPU_READ
100
s
Time from power-on to write operation
tPU_WRITE
10
ms
Power-down time
tPD
10
Power-down voltage
vBOT
ms
0.2
V
Pin Capacitance at Ta = 25C, f = 1 MHz
Parameter
Output pin capacitance
Input pin capacitance
Symbol
CDQ
CIN
Conditions
VDQ = 0 V
VIN = 0 V
Ratings
unit
max
12
pF
6
pF
Note : These parameter values do not represent the results of measurements undertaken for all devices but rather values for some of
the sampled devices.
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16
LE25U20AFD
AC Characteristics
Ratings
Parameter
Symbol
unit
min
typ
max
Clock frequency
fCLK
SCK logic high level pulse width
tCLHI
16
30
ns
SCK logic low level pulse width
tCLLO
16
ns
Input signal rising/falling time
tRF
CS setup time
tCSS
10
ns
CS hold time
tCSH
10
ns
Data setup time
tDS
5
ns
Data hold time
tDH
CS wait pulse width
tCPH
Output high impedance time from CS
tCHZ
Output data time from SCK
tV
Output data hold time
tHO
1
ns
HOLD setup time
tHS
7
ns
HOLD hold time
tHH
3
Output low impedance time from HOLD
tHLZ
9
ns
Output high impedance time from HOLD
tHHZ
9
ns
20
MHz
ns
5
ns
25
ns
10
WP setup time
tWPS
20
WP hold time
tWPH
20
Write status register time
tSRW
15
ns
15
ns
ns
ns
ns
5
15
ms
Page programming cycle time
tPP
4.0
5.0
ms
Small sector erase cycle time
tSSE
0.04
0.15
s
Sector erase cycle time
tSE
0.08
0.25
s
Chip erase cycle time
tCHE
0.25
1.6
s
Power-down time
tDP
3
s
Power-down recovery time
tPRB
3
s
Output low impedance time from SCK
tCLZ
0
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
AC Test Conditions
Input pulse level ············· 0 V, 2.5 V
Input rising/falling time ···· 5 ns
Input timing level ··········· 0.3VDD, 0.7VDD
Output timing level ········· 1/2 VDD
Output load ·················· 30 pF
Note : As the test conditions for "typ," the measurements are conducted using 2.5 V for VDD at room temperature.
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17
LE25U20AFD
Figure 20 Status Register Write Flowchart
Status register write
Start
06h
01h
Write enable
Set status register write
command
Data
Program start on rising
edge of CS
05h
NO
Set status register read
command
Bit 0= “0” ?
YES
End of status register
write
* Automatically placed in write disabled state
at the end of the status register write
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18
LE25U20AFD
Figure 21 Erase Flowcharts
Small sector erase
Sector erase
Start
Start
06h
Write enable
06h
D8h
D7h/20h
Address 1
NO
Address 1
Set small sector erase
command
Address 2
Address 2
Address 3
Address 3
Start erase on rising
edge of CS
Start erase on rising
edge of CS
Set status register read
command
05h
Write enable
05h
NO
Bit 0 = “0” ?
Set sector erase
command
Set status register read
command
Bit 0 = “0” ?
YES
YES
End of erase
End of erase
* Automatically placed in write disabled
state at the end of the erase
* Automatically placed in write disabled
state at the end of the erase
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19
LE25U20AFD
Figure 22 Page Program Flowchart
Page program
Chip erase
Start
Start
06h
06h
Write enable
C7h
Set chip erase
command
Write enable
02h
Address 1
Start erase on rising edge
of CS
05h
Set page program
command
Address 2
Address 3
Set status register read
command
Data 0
Data n
Bit 0 = “0” ?
YES
NO
Start program on rising
edge of CS
End of erase
* Automatically placed in write disabled state at
the end of the erase
Set status register read
command
05h
NO
Bit 0= “0” ?
YES
End of
programming
* Automatically placed in write disabled state at
the end of the programming operation.
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20
LE25U20AFD
ORDERING INFORMATION
Device
LE25U20AFD-AH
Package
Shipping (Qty / Packing)
VSOIC8 NB
(Pb-Free / Halogen Free)
3000 / Tape & Reel
† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
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