MAC4DSM, MAC4DSN
Preferred Device
Triacs
Silicon Bidirectional Thyristors
Designed for high volume, low cost, industrial and consumer
applications such as motor control; process control; temperature, light
and speed control.
• Small Size Surface Mount DPAK Package
• Passivated Die for Reliability and Uniformity
• Blocking Voltage to 800 V
• On–State Current Rating of 4.0 Amperes RMS at 108°C
• Low IGT — 10 mA Maximum in 3 Quadrants
• High Immunity to dv/dt — 50 V/ms at 125°C
• Device Marking: Device Type with “M’’ truncated, e.g.,
MAC4DSM: AC4DSM, Date Code
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TRIACS
4.0 AMPERES RMS
600 thru 800 VOLTS
MT2
MT1
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Peak Repetitive Off–State Voltage(1)
(TJ = –40 to 125°C, Sine Wave,
50 to 60 Hz, Gate Open)
MAC4DSM
MAC4DSN
VDRM,
VRRM
On–State RMS Current
(Full Cycle Sine Wave, 60 Hz,
TC = 108°C)
Peak Non-Repetitive Surge Current
(One Full Cycle Sine Wave, 60 Hz,
TJ = 125°C)
Circuit Fusing Consideration
(t = 8.3 msec)
Peak Gate Power
(Pulse Width ≤ 10 msec, TC = 108°C)
Average Gate Power
(t = 8.3 msec, TC = 108°C)
Value
Unit
4
600
800
IT(RMS)
4.0
ITSM
40
1
2
Amps
1 2
3
D–PAK
CASE 369
STYLE 6
3
D–PAK
CASE 369A
STYLE 6
Amps
PIN ASSIGNMENT
I2t
6.6
A2sec
PGM
0.5
Watt
PG(AV)
0.1
Watt
Peak Gate Current
(Pulse Width ≤ 10 msec, TC = 108°C)
IGM
0.2
Amp
Peak Gate Voltage
(Pulse Width ≤ 10 msec, TC = 108°C)
VGM
5.0
Volts
Operating Junction Temperature Range
TJ
– 40 to 125
°C
Tstg
– 40 to 150
°C
Storage Temperature Range
4
Volts
1
Main Terminal 1
2
Main Terminal 2
3
Gate
4
Main Terminal 2
ORDERING INFORMATION
(1) VDRM and VRRM for all types can be applied on a continuous basis. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the device are exceeded.
Device
Package
Shipping
MAC4DSMT4
DPAK 369A
16mm Tape
and Reel
(2.5K/Reel)
MAC4DSM–1
DPAK 369
75 Units/Rail
MAC4DSNT4
DPAK 369A
16mm Tape
and Reel
(2.5K/Reel)
MAC4DSN–1
DPAK 369
75 Units/Rail
Preferred devices are recommended choices for future use
and best overall value.
Semiconductor Components Industries, LLC, 2000
May, 2000 – Rev. 3
1
Publication Order Number:
MAC4DSM/D
MAC4DSM, MAC4DSN
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
R JC
R JA
R JA
q
q
q
3.5
88
80
°C/W
TL
260
°C
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient(1)
Maximum Lead Temperature for Soldering Purposes(2)
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted; Electricals apply in both directions)
Characteristic
Symbol
Min
Typ
Max
Unit
—
—
—
—
0.01
2.0
—
1.3
1.6
2.9
2.9
2.9
4.0
5.0
7.0
10
10
10
0.5
0.5
0.5
0.7
0.65
0.7
1.3
1.3
1.3
VGD
0.2
0.4
—
Volts
Holding Current
(VD = 12 V, Gate Open, Initiating Current = ± 200 mA)
IH
2.0
5.5
15
mA
Latching Current (VD = 12 V, IG = 10 mA)
MT2(+), G(+)
MT2(+), G(–)
MT2(–), G(–)
IL
—
—
—
6.0
10
6.0
30
30
30
Symbol
Min
Typ
Max
Unit
di/dt(c)
3.0
4.0
—
A/ms
dv/dt
50
175
—
V/ s
OFF CHARACTERISTICS
Peak Repetitive Blocking Current
(VD = Rated VDRM, VRRM; Gate Open)
TJ = 25°C
TJ = 125°C
IDRM,
IRRM
mA
ON CHARACTERISTICS
Peak On–State Voltage(3)
(ITM = ± 6.0 A)
VTM
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100
MT2(+), G(+)
MT2(+), G(–)
MT2(–), G(–)
Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100
MT2(+), G(+)
MT2(+), G(–)
MT2(–), G(–)
W)
IGT
W)
VGT
W
Gate Non–Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 )
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–)
TJ = 125°C
Volts
mA
Volts
mA
DYNAMIC CHARACTERISTICS
Characteristic
Rate of Change of Commutating Current
(VD = 400 V, ITM = 3.5 A, Commutating dv/dt = 10 V/ sec,
Gate Open, TJ = 125°C, f = 500 Hz, CL = 5.0 F, LL = 20 mH,
No Snubber)
See Figure 16
m
m
Critical Rate of Rise of Off–State Voltage
(VD = 0.67 X Rated VDRM, Exponential Waveform,
Gate Open, TJ = 125°C)
(1) Surface mounted on minimum recommended pad size.
(2) 1/8″ from case for 10 seconds.
(3) Pulse Test: Pulse Width ≤ 2.0 msec, Duty Cycle ≤ 2%.
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2
m
MAC4DSM, MAC4DSN
Voltage Current Characteristic of Triacs
(Bidirectional Device)
+ Current
Symbol
Parameter
VDRM
IDRM
Peak Forward Blocking Current
VRRM
IRRM
VTM
IH
VTM
Peak Repetitive Forward Off State Voltage
Quadrant 1
MainTerminal 2 +
on state
IH
IRRM at VRRM
Peak Repetitive Reverse Off State Voltage
Peak Reverse Blocking Current
Maximum On State Voltage
off state
IH
Holding Current
Quadrant 3
VTM
MainTerminal 2 –
Quadrant Definitions for a Triac
MT2 POSITIVE
(Positive Half Cycle)
+
(+) MT2
Quadrant II
(+) MT2
(–) IGT
GATE
Quadrant I
(+) IGT
GATE
MT1
MT1
REF
REF
IGT –
+ IGT
(–) MT2
Quadrant III
(–) MT2
Quadrant IV
(+) IGT
GATE
(–) IGT
GATE
MT1
MT1
REF
REF
–
MT2 NEGATIVE
(Negative Half Cycle)
All polarities are referenced to MT1.
With in–phase signals (using standard AC lines) quadrants I and III are used.
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3
+ Voltage
IDRM at VDRM
P(AV) , AVERAGE POWER DISSIPATION (WATTS)
125
a = 30°
120
60°
90°
115
α
α
110
120°
a = CONDUCTION ANGLE
180°
dc
105
0
0.5
1.0
1.5
2.5
2.0
3.0
3.5
α
120°
α
4.0
90°
a = CONDUCTION ANGLE
3.0
2.0
60°
a = 30°
1.0
0
1.0
2.0
3.0
4.0
IT(RMS), RMS ON–STATE CURRENT (AMPS)
IT(RMS), RMS ON–STATE CURRENT (AMPS)
Figure 1. RMS Current Derating
Figure 2. On–State Power Dissipation
TYPICAL @ TJ = 25°C
MAXIMUM @ TJ = 125°C
10
MAXIMUM @ TJ = 25°C
1.0
0.1
1.0
0
2.0
3.0
1.0
0.1
ZqJC(t) = RqJC(t)Sr(t)
0.01
5.0
4.0
0.1
10
1.0
100
1000
VT, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS)
t, TIME (ms)
Figure 3. On–State Characteristics
Figure 4. Transient Thermal Response
10 k
1.0
18
VGT, GATE TRIGGER VOLTAGE(VOLTS)
Q3
I GT, GATE TRIGGER CURRENT (mA)
dc
180°
5.0
0
100
16
14
12
10
Q2
8.0
6.0
6.0
4.0
r(t) , TRANSIENT RESISTANCE (NORMALIZED)
IT, INSTANTANEOUS ON–STATE CURRENT (AMPS)
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( °C)
MAC4DSM, MAC4DSN
Q1
4.0
2.0
0
–50
Q3
0.8
Q1
Q2
0.6
0.4
0.2
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Typical Gate Trigger Current versus
Junction Temperature
Figure 6. Typical Gate Trigger Voltage versus
Junction Temperature
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4
125
MAC4DSM, MAC4DSN
14
25
Q2
IL, LATCHING CURRENT (mA)
IH , HOLDING CURRENT (mA)
12
10
MT2 NEGATIVE
8.0
6.0
MT2 POSITIVE
4.0
2.0
20
Q1
15
Q3
10
5.0
0
0
–50
–25
0
25
50
75
125
100
–50
–25
50
75
125
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Typical Holding Current versus
Junction Temperature
Figure 8. Typical Latching Current versus
Junction Temperature
1200
TJ = 125°C
TJ = 125°C
VPK = 400 V
1000
STATIC dv/dt (V/ ms)
800
STATIC dv/dt (V/ ms)
25
TJ, JUNCTION TEMPERATURE (°C)
1000
600
VPK = 400 V
400
600 V
200
800
600
600 V
400
200
800 V
800 V
0
0
100
1000
10 k
1000
100
10 k
RG–MT1, GATE–MT1 RESISTANCE (OHMS)
RG–MT1, GATE–MT1 RESISTANCE (OHMS)
Figure 9. Exponential Static dv/dt versus
Gate–MT1 Resistance, MT2(+)
Figure 10. Exponential Static dv/dt versus
Gate–MT1 Resistance, MT2(–)
2000
800
GATE OPEN
GATE OPEN
1600
STATIC dv/dt (V/ ms)
600
STATIC dv/dt (V/ ms)
0
TJ = 100°C
400
110°C
125°C
200
TJ = 100°C
1200
110°C
800
125°C
400
0
0
400
500
600
700
800
400
500
600
700
VPK, PEAK VOLTAGE (VOLTS)
VPK, PEAK VOLTAGE (VOLTS)
Figure 11. Exponential Static dv/dt versus
Peak Voltage, MT2(+)
Figure 12. Exponential Static dv/dt versus
Peak Voltage, MT2(–)
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5
800
MAC4DSM, MAC4DSN
800
1600
GATE OPEN
VPK = 400 V
VPK = 400 V
1200
STATIC dv/dt (V/ ms)
400
600 V
200
1000
800
600 V
600
400
800 V
200
0
800 V
0
100
105
110
115
120
125
100
105
110
115
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. Typical Exponential Static dv/dt
versus Junction Temperature, MT2(+)
Figure 14. Typical Exponential Static dv/dt
versus Junction Temperature, MT2(–)
100
VPK = 400 V
dv/dt(c), CRITICAL RATE OF RISE OF
COMMUTATING VOLTAGE (V/ ms)
STATIC dv/dt (V/ ms)
600
GATE OPEN
1400
TJ = 125°C
100°C
75°C
10
tw
VDRM
f=
1
2 tw
6f I
(di/dt)c = TM
1000
1.0
0
10
5.0
15
di/dt(c), RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
Figure 15. Critical Rate of Rise of
Commutating Voltage
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6
20
125
MAC4DSM, MAC4DSN
LL
200 VRMS
ADJUST FOR
ITM, 60 Hz VAC
MEASURE
I
TRIGGER
CHARGE
CONTROL
NON-POLAR
CL
TRIGGER CONTROL
CHARGE
1N4007
–
+
1N914 51
W
200 V
MT2
MT1
G
Note: Component values are for verification of rated (di/dt)c. See AN1048 for additional information.
Figure 16. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Current (di/dt)c
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7
MAC4DSM, MAC4DSN
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
0.165
4.191
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.100
2.54
0.118
3.0
0.063
1.6
0.190
4.826
0.243
6.172
inches
mm
DPAK
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8
MAC4DSM, MAC4DSN
PACKAGE DIMENSIONS
D–PAK
CASE 369–07
ISSUE L
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
A
1
2
3
S
–T–
K
SEATING
PLANE
J
F
H
D
G
STYLE 6:
PIN 1.
2.
3.
4.
3 PL
0.13 (0.005)
M
INCHES
MIN
MAX
0.235
0.250
0.250
0.265
0.086
0.094
0.027
0.035
0.033
0.040
0.037
0.047
0.090 BSC
0.034
0.040
0.018
0.023
0.350
0.380
0.175
0.215
0.050
0.090
0.030
0.050
T
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.84
1.01
0.94
1.19
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.46
1.27
2.28
0.77
1.27
MT1
MT2
GATE
MT2
D–PAK
CASE 369A–13
ISSUE Z
–T–
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
4
Z
A
S
1
2
3
U
K
F
J
L
H
D
G
2 PL
0.13 (0.005)
M
T
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
INCHES
MIN
MAX
0.235
0.250
0.250
0.265
0.086
0.094
0.027
0.035
0.033
0.040
0.037
0.047
0.180 BSC
0.034
0.040
0.018
0.023
0.102
0.114
0.090 BSC
0.175
0.215
0.020
0.050
0.020
–––
0.030
0.050
0.138
–––
STYLE 6:
PIN 1.
2.
3.
4.
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9
MT1
MT2
GATE
MT2
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.84
1.01
0.94
1.19
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.45
5.46
0.51
1.27
0.51
–––
0.77
1.27
3.51
–––
MAC4DSM, MAC4DSN
Notes
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10
MAC4DSM, MAC4DSN
Notes
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11
MAC4DSM, MAC4DSN
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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