MC100EL1648
5 V ECL Voltage Controlled
Oscillator Amplifier
Description
Features
•
•
•
•
•
•
Typical Operating Frequency Up to 1100 MHz
Low−Power 19 mA at 5.0 Vdc Power Supply
PECL Mode Operating Range: VCC = 4.2 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V
to −5.5 V
Input Capacitance = 6.0 pF (TYP)
Pb−Free Packages are Available
NOTE:
The MC100EL1648 is NOT useable as a crystal oscillator.
VCC
EXTERNAL
TANK
CIRCUIT
BIAS POINT
OUTPUT
VEE
VEE
August, 2008 − Rev. 8
8
SOIC−8
D SUFFIX
CASE 751
8
1
K1648
ALYW
G
1
8
TSSOP−8
DT SUFFIX
CASE 948R
8
1
1
1648
ALYWG
G
14
SOEIAJ−14
M SUFFIX
CASE 965
14
1
KEL1648
ALYWG
1
DFN8
MN SUFFIX
CASE 506AA
1
4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
AGC
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
Figure 1. Logic Diagram
© Semiconductor Components Industries, LLC, 2008
MARKING
DIAGRAMS*
A
L
Y
W
M
G or G
VCC
TANK
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6L M G
G
The MC100EL1648 is a voltage controlled oscillator amplifier that
requires an external parallel tank circuit consisting of the inductor (L)
and capacitor (C). A varactor diode may be incorporated into the tank
circuit to provide a voltage variable input for the oscillator (VCO).
This device may also be used in many other applications requiring a
fixed frequency clock.
The MC100EL1648 is ideal in applications requiring a local
oscillator, systems that include electronic test equipment, and digital
high−speed telecommunications.
The MC100EL1648 is based on the VCO circuit topology of the
MC1648. The MC100EL1648 uses advanced bipolar process
technology which results in a design which can operate at an extended
frequency range.
The ECL output circuitry of the MC100EL1648 is not a traditional
open emitter output structure and instead has an on−chip termination
emitter resistor, RE, with a nominal value of 510 W. This facilitates
direct ac−coupling of the output signal into a transmission line.
Because of this output configuration, an external pull−down resistor is
not required to provide the output with a dc current path. This output is
intended to drive one ECL load (3.0 pF). If the user needs to fanout the
signal, an ECL buffer such as the EL16 (EL11, EL14) type Line
Receiver/Driver should be used.
1
Publication Order Number:
MC100EL1648/D
MC100EL1648
BIAS
VEE
VEE
8
7
6
5
14
13
12
11
10
9
8
1
2
3
4
1
2
3
4
5
6
7
VCC
OUT
VCC
NC
OUT
NC
AGC
NC
VEE
TANK VCC
AGC
VCC
NC TANK NC BIAS NC
8 Lead
VEE
14 Lead
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 2. Pinout Assignments
Table 1. PIN DESCRIPTION
Pin No.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
8 Lead
14 Lead
Symbol
Description
1
12
TANK
2, 3
1, 14
VCC
Positive Supply
4
3
OUT
ECL Output
5
5
AGC
Automatic Gain Control Input
6, 7
7, 8
VEE
Negative Output
8
10
BIAS
OSC Input Reference Voltage
2, 4, 7, 9, 11, 13
NC
No Connect
EP
(DFN8 only) Thermal exposed pad must be connected to a sufficient thermal
conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open.
Thermal
Exposed
Pad
OSC Input Voltage
Table 2. ATTRIBUTES
Characteristic
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
SOEIAJ−14
DFN8
Flammability Rating
Oxygen Index: 23 to 34
Transistor Count
> 1 kV
> 100 V
> 1 kV
Pb Pkg
Pb−Free Pkg
Level 1
Level 1
Level 3
Level 1
Level 1
Level 3
Level 3
Level 1
UL 94 V−0 @ 0.125 in
11
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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2
MC100EL1648
Table 3. MAXIMUM RATINGS
Rating
Unit
VCC
Symbol
Power Supply PECL Mode
Parameter
VEE = 0 V
Condition 1
7 to 0
V
VEE
Power Supply NECL Mode
VCC = 0 V
−7 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6 to 0
−6 to 0
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−8
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−14
SOIC−14
150
110
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−14
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol
Wave Solder
1 MW ).
8 pin (14 pin) Lead Package
0.1 mF
Tank Circuit Option #2, Fixed LC
Figure 3. Typical Test Circuit with Alternate Tank Circuits
50%
VP-P
ta
PRF = 1.0MHz
t
Duty Cycle (Vdc) - a
tb
tb
Figure 4. Output Waveform
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5
MC100EL1648
OPERATION THEORY
Q2 and Q3, in conjunction with output transistor Q1,
provide a highly buffered output that produces a square
wave. The typical output waveform can be seen in Figure 4.
The bias drive for the oscillator and output buffer is provided
by Q9 and Q11 transistors. In order to minimize current, the
output circuit is realized as an emitter−follower buffer with
an on chip pull−down resistor RE.
Figure 5 illustrates the simplified circuit schematic for the
MC100EL1648. The oscillator incorporates positive feedback
by coupling the base of transistor Q6 to the collector of Q7. An
automatic gain control (AGC) is incorporated to limit the
current through the emitter−coupled pair of transistors (Q7 and
Q6) and allow optimum frequency response of the oscillator.
In order to maintain the high quality factor (Q) on the oscillator,
and provide high spectral purity at the output, transistor Q4 is
used to translate the oscillator signal to the output differential
pair Q2 and Q3. Figure 16 indicates the high spectral purity
of the oscillator output (pin 4 on 8−pin SOIC). Transistors
VCC 2 (14)
800 W
VCC 3 (1)
1.36 KW
3.1 KW
660 W
167 W
Q9
Q1
Q3
1.6 KW
Q2
OUTPUT
4 (3)
Q4
Q11
Q10
Q7 Q6
D1
330 W
Q8
D2
400 W
Q5
16 KW
VEE
7 (8)
BIAS
8 (10)
TANK
1 (12)
VEE
6 (7)
82 W
AGC
5 (5)
Figure 5. Circuit Schematic
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6
400 W
660 W
510 W
8 pin (14 pin) Lead Package
MC100EL1648
30
Measured Frequency (MHz)
FREQUENCY (MHz)
25
Calculated Frequency (MHz)
20
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = 3.0−35 pF Variable Capacitance (@ 10 pF)
15
* The 1200 W resistor and the scope termination
impedance constitute a 25:1 attenuator probe.
Coax shall be CT−070−50 or equivalent.
10
5
0
8 pin (14 pin) Lead Package
0
300
500
1000
2000
10000
0.1mF
CAPACITANCE (pF)
2 (14)
8 (10)
10mF
3(1)
1200*
L
0.1mF
C
4 (3)
SIGNAL
UNDER
TEST
1 (12)
Tank #3
6 (7) 7 (8)
VEE
100 mF
0.01 mF
5 (5)
0.1 mF
0.1 mF
Figure 6. Low Frequency Plot
100
FREQUENCY (MHZ)
80
60
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = 3.0−35 pF Variable Capacitance (@ 10 pF)
40
20
* The 1200 W resistor and the scope termination
impedance constitute a 25:1 attenuator probe.
Coax shall be CT−070−50 or equivalent.
Measured Frequency (MHz)
Calculated Frequency (MHz)
0
0
0.2
0.3
8 pin (14 pin) Lead Package
300
0.1mF
CAPACITANCE (pF)
2 (14)
8 (10)
10mF
3(1)
1200*
L
0.1mF
Tank #3
C
4 (3)
1 (12)
6 (7) 7 (8)
VEE
100 mF
0.01 mF
Figure 7. High Frequency Plot
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7
0.1 mF
5 (5)
0.1 mF
SIGNAL
UNDER
TEST
MC100EL1648
FIXED FREQUENCY MODE
capacitors should have very low dielectric loss (high−Q). At
a minimum, the capacitors selected should be operating at
100 MHz below their series resonance point. As the desired
frequency of operation increases, the values of the tank
capacitor will decrease since the series resonance point is a
function of the capacitance value. Typically, the inductor is
realized as a surface−mount chip or a wound coil. In
addition, the lead inductance and board inductance and
capacitance also have an impact on the final operating point.
The following equation will help to choose the appropriate
values for your tank circuit design.
The MC100EL1648 external tank circuit components are
used to determine the desired frequency of operation as
shown in Figure 8, tank option #2. The tank circuit
components have direct impact on the tuning sensitivity, IEE,
and phase noise performance. Fixed frequency of the tank
circuit is usually realized by an inductor and capacitor (LC
network) that contains a high Quality factor (Q). The plotted
curve indicates various fixed frequencies obtained with a
single inductor and variable capacitor. The Q of the
components in the tank circuit has a direct impact on the
resulting phase noise of the oscillator. In general, when the
Q is high the oscillator will result in lower phase noise.
f0 +
570
FREQUENCY (MHz)
LT = Total Inductance
CT = Total Capacitance
Figure 9 and Figure 10 represent the ideal curve of
inductance/capacitance versus frequency with one known
tank component. This helps the designer of the tank circuit
to choose desired value of inductor/capacitor component for
the wanted frequency. The lead inductance and board
inductance and capacitance will also have an impact on the
tank component values (inductor and capacitor).
Calculated Frequency (MHz)
370
270
170
70
0
−30
50
0.3
300
500
1000
2000
45
10000
INDUCTANCE (nH)
CAPACITANCE (pF)
VCC
0.1 mF
8 (10)
0.1 mF
3 (1)
2 (14)
C
L
Tank #2
35
30
Inductance vs. Frequency with 5 pF Cap
25
20
15
5
FOUT
0
400
1 (12)
700
1000
1300
160
FREQUENCY (MHz)
6 (7) 7 (8)
VEE
100 mF
40
10
4 (3)
Figure 9. Capacitor Value Known (5 pF)
5 (5)
50
0.01 mF
0.1 mF
45
0.1 mF
40
CAPACITANCE (F)
0.1 mF
Test
Point
Ǹ LT * CT
Where
Measured Frequency (MHz)
470
1
2p
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = 3.0−35 pF Variable Capacitance (@ 10 pF)
Note 1 Capacitor for tank may be variable type.
(See Tank Circuit #3.)
Note 2 Use high impedance probe (> 1 MW ).
35
30
Capacitance vs. Frequency with 4 nH Inductance
25
20
15
10
8 pin (14 pin) lead package
5
QL ≥ 100
0
Figure 8. Fixed Frequency LC Tank
Only high quality surface−mount RF chip capacitors
should be used in the tank circuit at high frequencies. These
400
700
1000
FREQUENCY (Hz)
1300
Figure 10. Inductor Value Known (4 nH)
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8
160
MC100EL1648
VOLTAGE CONTROLLED MODE
The tank circuit configuration presented in Figure 11,
Voltage Controlled Varactor Mode, allows the VCO to be
tuned across the full operating voltage of the power supply.
Deriving from Figure 6, the tank capacitor, C, is replaced
with a varactor diode whose capacitance changes with the
voltage applied, thus changing the resonant frequency at
which the VCO tank operates as shown in Figure 3, tank
option #1. The capacitive component in Equation 1 also
needs to include the input capacitance of the device and
other circuit and parasitic elements.
When operating the oscillator in the voltage controlled
mode with Tank Circuit #1 (Figure 3), it should be noted that
the cathode of the varactor diode (D), pin 8 (for 8 lead
package) or pin 10 (for 14 lead package) should be biased at
least 1.4 V above VEE.
Typical transfer characteristics employing the
capacitance of the varactor diode (plus the input capacitance
of the device, about 6.0 pF typical) in the voltage controlled
mode is shown in Plot 1, Dual Varactor MMBV609 Vin vs.
Frequency. Figure 6, Figure 7, and Figure 8 show the
accuracy of the measured frequency with the different
variable capacitance values. The 1.0 kW resistor in Figure 11
is used to protect the varactor diode during testing. It is not
necessary as long as the dc input voltage does not cause the
diode to become forward biased. The tuning range of the
oscillator in the voltage controlled mode may be calculated
as follows:
190
FREQUENCY (MHz)
170
150
130
110
Ǹ CD(max) ) CS
f max
+
f min
Ǹ CD(min) ) CS
90
70
50
Where
0
2
4
6
8
10
f min +
Vin, INPUT VOLTAGE (V)
Figure 12. Plot 1. Dual Varactor MMBV609,
VIN vs. Frequency
Where
CS = Shunt Capacitance (input plus external
capacitance)
VCC
0.1 mF
8 (10)
2 (14)
VIN
Good RF and low−frequency bypassing is necessary on
the device power supply pins. Capacitors on the AGC pin
and the input varactor trace should be used to bypass the
AGC point and the VCO input (varactor diode),
guaranteeing only dc levels at these points. For output
frequency operation between 1.0 MHz and 50 MHz, a 0.1 mF
capacitor is sufficient. At higher frequencies, smaller values
of capacitance should be used; at lower frequencies, larger
values of capacitance. At high frequencies, the value of
bypass capacitors depends directly on the physical layout of
the system. All bypassing should be as close to the package
pins as possible to minimize unwanted lead inductance.
Several different capacitors may be needed to bypass
various frequencies.
4 (3)
L*
C
CD = Varactor Capacitance as a function of bias
voltage
0.1 mF
3 (1)
1 KW
Tank #1
1 (12)
6 (7) 7 (8)
VEE
100 mF
0.01 mF
0.1 mF
1
2p Ǹǒ L(CD(max) ) CS Ǔ
5 (5) **
0.1 mF FOUT
*Use high impedance probe (>1.0 MegW must be used).
**The 1200 W resistor and the scope termination impedance constitute a 25:1 attenuator probe. Coax shall be
CT−070−50 or equivalent.
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = MMBV609
8 pin (14 pin) lead package
Figure 11. Voltage Controlled Varactor Mode
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MC100EL1648
WAVE−FORM CONDITIONING − SINE OR SQUARE WAVE
Figure 13. At frequencies above 100 MHz typical, it may be
desirable to increase the tank circuit peak−to−peak voltage
in order to shape the signal into a more square waveform at
the output of the MC100EL1648. This is accomplished by
tying a series resistor (1.0 kW minimum) from the AGC to
the most positive power potential (+5.0 V if a positive volt
supply is used, ground if a −5.2 V supply is used). Figure 14
illustrates this principle.
The peak−to−peak swing of the tank circuit is set
internally by the AGC pin. Since the voltage swing of the
tank circuit provides the drive for the output buffer, the AGC
potential directly affects the output waveform. If it is desired
to have a sine wave at the output of the MC100EL1648, a
series resistor is tied from the AGC point to the most
negative power potential (ground if positive volt supply is
used, −5.2 V if a negative supply is used) as shown in
+5.0Vdc
1
+5.0Vdc
14
10
1
3
14
10
Output
3
Output
1.0k min
12
5
7
12
8
5
7
Figure 13. Method of Obtaining a Sine−Wave Output
8
Figure 14. Method of Extending the Useful Range
of the MC100EL1648 (Square Wave Output)
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10
MC100EL1648
10 dB / DEC
SPECTRAL PURITY
99.8
99.9
100.0
100.1
100.2
B.W. = 10 kHz, Center Frequency = 100 MHz
Scan Width = 50 kHz/div, Vertical Scale = 10 dB/div
Figure 15. Spectral Purity
0.1 mF
2 (14)
8 (10)
10 mF
3(1)
1200*
L
0.1 mF
C
4 (3)
SIGNAL
UNDER
TEST
1 (12)
Tank #3
6 (7) 7 (8)
VEE
100 mF
0.01 mF
0.1 mF
5 (5)
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = 3.0−35 pF Variable Capacitance (@ 10 pF)
** The 1200 W resistor and the scope termination
impedance constitute a 25:1 attenuator probe.
Coax shall be CT−070−50 or equivalent.
0.1 mF
8 pin (14 pin) Lead Package
Spectral Purity Test Circuit
Figure 16. Spectral Purity of Signal Output for 200 MHz Testing
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 17. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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11
MC100EL1648
ORDERING INFORMATION
Package
Shipping†
MC100EL1648D
SOIC−8, Narrow Body
98 Units / Rail
MC100EL1648DG
SOIC−8, Narrow Body
(Pb−Free)
98 Units / Rail
MC100EL1648DR2
SOIC−8, Narrow Body
2500 / Tape & Reel
MC100EL1648DR2G
SOIC−8, Narrow Body
(Pb−Free)
2500 / Tape & Reel
MC100EL1648DT
TSSOP−8
100 Units / Rail
MC100EL1648DTG
TSSOP−8
(Pb−Free)
100 Units / Rail
MC100EL1648DTR2
TSSOP−8
2500 / Tape & Reel
MC100EL1648DTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
MC100EL1648M
SOEAIJ−14
50 Units / Rail
MC100EL1648MG
SOEAIJ−14
(Pb−Free)
50 Units / Rail
MC100EL1648MEL
SOEAIJ−14
2000 / Tape & Reel
MC100EL1648MELG
SOEAIJ−14
(Pb−Free)
2000 / Tape & Reel
MC100EL1648MNR4
DFN8
1000 / Tape & Reel
DFN8
(Pb−Free)
1000 / Tape & Reel
Device
MC100EL1648MNR4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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12
MC100EL1648
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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13
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
MC100EL1648
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x
0.15 (0.006) T U
0.10 (0.004)
S
2X
L/2
L
8
5
1
PIN 1
IDENT
0.15 (0.006) T U
K REF
M
T U
V
S
0.25 (0.010)
B
−U−
4
M
A
−V−
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
−W−
G
DETAIL E
http://onsemi.com
14
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0_
6_
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0_
6_
MC100EL1648
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE A
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
8
Q1
E HE
L
7
1
M_
DETAIL P
Z
D
VIEW P
A
e
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
http://onsemi.com
15
DIM
A
A1
b
c
D
E
e
HE
0.50
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--1.42
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.004
0.008
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.056
MC100EL1648
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
B
PIN ONE
REFERENCE
2X
0.10 C
2X
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
TOP VIEW
0.10 C
0.08 C
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
1.10
1.30
2.00 BSC
0.70
0.90
0.50 BSC
0.20
−−−
0.25
0.35
A
0.10 C
8X
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
E
(A3)
SIDE VIEW
A1
C
D2
e
e/2
4
1
8X
L
E2
K
8
5
8X
b
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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