MC100EL30DW

MC100EL30 5V ECL Triple D Flip-Flop with Set and Reset The MC100EL30 is a triple master−slave D flip−flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the clock input. In addition to a common Set input individual Reset inputs are provided for each flip flop. Both the Set and Reset inputs function asynchronous and overriding with respect to the clock inputs. http://onsemi.com Features • • • • • • • • • • • • 1200 MHz Minimum Toggle Frequency 450 ps Typical Propagation Delays ESD Protection: >2 kV Human Body Model The 100 Series Contains Temperature Compensation. PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input 75 kW Pulldown Resistors Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity: Pb = Level 1 Pb−Free = Level 3 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 347 devices Pb−Free Packages are Available* SO−20 WB DW SUFFIX CASE 751D MARKING DIAGRAM* 20 100EL30 AWLYYWWG 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2008 November, 2008 − Rev. 6 1 Publication Order Number: MC100EL30/D MC100EL30 VCC Q0 Q0 VCC Q1 Q1 VCC Q2 Q2 VEE 20 19 18 17 16 15 14 13 12 11 Q Q S Q R Q S D Q R Pin Function D0−D2 R0−R2 CLK0−CLK2 S012 Q0−Q2; Q0−Q2 VCC VEE Q S D Table 1. PIN DESCRIPTION R D 1 2 3 4 5 6 7 8 9 10 S012 D0 CLK0 R0 D1 CLK1 R1 D2 CLK2 R2 Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. ECL Data Inputs ECL Reset Inputs ECL Clock Inputs ECL Common Set Input ECL Differential Data Outputs Positive Supply Negative Supply Table 2. FUNCTION TABLE Figure 1. Logic Diagram and Pinout: 20-Lead SOIC (Top View) R* S* D* CLK* Q Q L L H L H L L L H H L H X X X Z Z X X X L H L H Undef H L H L Undef Z = Low-to-High Transition X = Don’t Care *Pin will default low when left open. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 to 0 −6 to 0 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−20 SOIC−20 90 60 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−20 30 to 35 °C/W Tsol Wave Solder