MC100LVEL14DWR2G

MC100LVEL14 3.3 V ECL 1:5 Clock Distribution Chip Description The MC100LVEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14 but is designed to operate in ECL or PECL mode for a voltage supply range of −3.0 V to −3.8 V ( or 3.0 V to 3.8 V). The LVEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Features • • • • • • • • • • • • 50 ps Output-to-Output Skew Synchronous Enable/Disable Multiplexed Clock Input www.onsemi.com 20 1 SOIC−20 WB DW SUFFIX CASE 751D−05 MARKING DIAGRAM 20 100LVEL14 AWLYYWWG 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package ORDERING INFORMATION ESD Protection: Human Body Model > 2 kV Device The 100 Series Contains Temperature Compensation MC100LVEL14DWG PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V Internal Input Pulldown Resistors on CLK Package Shipping† SOIC−20 WB (Pb-Free) 38 Units / Tube MC100LVEL14DWR2G SOIC−20 WB 1000 Tape & Reel (Pb-Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Q Output will Default LOW with Inputs Open or at VEE Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity: Level 3 (Pb-Free) Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 303 Devices • • These Devices are Pb-Free, Halogen Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2016 July, 2016 − Rev. 10 1 Publication Order Number: MC100LVEL14/D MC100LVEL14 VCC EN VCC NC SCLK CLK CLK VBB SEL VEE 20 19 18 17 16 15 14 13 12 Table 1. PIN DESCRIPTION 11 PIN ECL Diff Clock Inputs SCLK ECL Scan Clock Input EN ECL Sync Enable SEL ECL Clock Select Input Q0−4, Q0−4 ECL Diff Clock Outputs 10 VBB Reference Voltage Output Q4 VCC Positive Supply VEE Negative Supply NC No Connect 1 0 D Q 1 Q0 2 Q0 3 Q1 4 Q1 5 Q2 6 Q2 7 Q3 8 Q3 9 Q4 FUNCTION CLK, CLK Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Pinout (Top View) and Logic Diagram Table 2. FUNCTION TABLE CLK SCLK SEL EN Q L H X X X X X L H X L L H H X L L L L H L H L H L* *On next negative transition of CLK or SCLK X = Don’t Care Table 3. MAXIMUM RATINGS Symbol Rating Unit VCC PECL Mode Power Supply Parameter VEE = 0 V Condition 1 Condition 2 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 to 0 −6 to 0 V Iout Output Current Continuous Surge 50 100 mA IBB VBB Sink/Source ±0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm SOIC−20 WB SOIC−20 WB 90 60 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC−20 WB 30 to 35 °C/W Tsol Wave Solder < 2 to 3 sec @ 260°C 265 °C VI ≤ VCC VI ≥ VEE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2 MC100LVEL14 Table 4. LVPECL DC CHARACTERISTICS (VCC = 3.3 V; VEE = 0 V (Note 1)) −40°C Symbol Min Characteristic 25°C Typ Max 32 40 Min 85°C Typ Max 32 40 Min Typ Max Unit 34 42 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV VOL Output LOW Voltage (Note 2) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV VIH Input HIGH Voltage (Single-Ended) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single-Ended) 1490 1825 1490 1825 1490 1825 mV VBB Output Voltage Reference 1.92 2.04 1.92 2.04 1.92 2.04 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) VPP < 500 mV VPP ≥ 500 mV IIH Input HIGH Current IIL Input LOW Current Others CLK V 1.3 1.5 2.9 2.9 1.2 1.4 2.9 2.9 150 1.2 1.4 2.9 2.9 150 0.5 −300 0.5 −300 150 mA mA 0.5 −300 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1.0 V. Table 5. LVNECL DC CHARACTERISTICS (VCC = 0.0 V; VEE = −3.3 V (Note 1)) −40°C Symbol Characteristic Min 25°C Typ Max 32 40 Min 85°C Typ Max 32 40 Min Typ Max Unit 34 42 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV VOL Output LOW Voltage (Note 2) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV VIH Input HIGH Voltage (Single-Ended) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single-Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) VPP < 500 mV VPP ≥ 500 mV IIH Input HIGH Current IIL Input LOW Current Others CLK V −2.0 −1.8 −0.4 −0.4 −2.1 −1.9 150 0.5 −300 −0.4 −0.4 −2.1 −1.9 150 0.5 −300 −0.4 −0.4 150 0.5 −300 mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1.0 V. www.onsemi.com 3 MC100LVEL14 Table 5. AC CHARACTERISTICS (VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 1) −40°C Symbol fmax tPLH tPHL Min Characteristic Maximum Toggle Frequency (Figure 2) Prop Delay Part-to-Part Skew Within-Device Skew (Note 2) tJITTER Random Clock Jitter (RMS) @ 1 Ghz (Figure 2) 25°C Max Min >1 CLK to Q (Diff) CLK to Q (SE) SCLK to Q tSKEW Typ 520 470 470 Typ Min Typ >1 720 770 770 580 530 530 680 680 680 200 50 0.2 85°C Max >1 780 830 830 630 580 580 200 50