MC34067DWG

MC34067, MC33067, NCV33067 High Performance Resonant Mode Controllers The MC34067/MC33067 are high performance zero voltage switch resonant mode controllers designed for off−line and dc−to−dc converter applications that utilize frequency modulated constant off−time or constant deadtime control. These integrated circuits feature a variable frequency oscillator, a precise retriggerable one−shot timer, temperature compensated reference, high gain wide bandwidth error amplifier, steering flip−flop, and dual high current totem pole outputs ideally suited for driving power MOSFETs. Also included are protective features consisting of a high speed fault comparator and latch, programmable soft−start circuitry, input undervoltage lockout with selectable thresholds, and reference undervoltage lockout. These devices are available in dual−in−line and surface mount packages. www.onsemi.com MARKING DIAGRAMS 16 16 1 Features PDIP−16 P SUFFIX CASE 648 • Zero Voltage Switch Resonant Mode Operation • Variable Frequency Oscillator with a Control Range • • • • • • • • • • VCC UVLO / Enable MC3x067DW AWLYYWWG 1 SOIC−16W DW SUFFIX CASE 751G x A WL YY WW G 1 = 3 or 4 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS 11 16 One-Shot RC OSC Charge 1 5 5.0 V Reference Vref Vref UVLO Variable Frequency Oscillator 15 VCC OSC RC 2 14 Drive Output A OSC Control Current 3 13 Power GND GND 4 14 16 Error Amp 6 Output Noninverting 8 Input Inverting Input 7 Soft-Start 16 15 Enable / 9 UVLO Adjust 1 OSC Charge 2 OSC RC Oscillator 3 Control Current One-Shot 1 16 Exceeding 1000:1 Precision One−Shot Timer for Controlled Off−Time Internally Trimmed Bandgap Reference 4.0 MHz Error Amplifier Dual High Current Totem Pole Outputs Selectable Undervoltage Lockout Thresholds with Hysteresis Enable Input Programmable Soft−Start Circuitry Low Startup Current for Off−Line Operation NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant VCC MC3x067P AWLYYWWG Steering Flip-Flop One-Shot Output A Error Amp Out 6 11 CSoft-Start Output B Inverting Input 7 Pwr GND Noninverting Input 8 10 Fault Input Enable/UVLO 9 Adjust 12 2.5 V Clamp 12 Drive Output B Vref 5 13 (Top View) Error Amp Soft-Start 10 Fault Detector/ Latch Fault Input ORDERING INFORMATION 4 See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Ground Figure 1. Simplified Block Diagram © Semiconductor Components Industries, LLC, 2015 August, 2015 − Rev. 15 1 Publication Order Number: MC34067/D MC34067, MC33067, NCV33067 MAXIMUM RATINGS Rating Power Supply Voltage Symbol Value Unit VCC 20 V Drive Output Current, Source or Sink (Note 1) − Continuous − Pulsed (0.5 ms), 25% Duty Cycle IO A Error Amplifier, Fault, One−Shot, Oscillator and Soft−Start Inputs Vin − 1.0 to + 6.0 V Vin(UVLO) − 1.0 to VCC V PD RqJA 862 145 mW °C/W PD RqJA 1.25 100 W °C/W Operating Junction Temperature TJ + 150 °C Operating Ambient Temperature MC34067 MC33067, NCV33067 TA Storage Temperature Tstg − 55 to + 150 °C ESD Capability, HBM Model per JEDEC JESD22−A114F − 2.0 kV ESD Capability, CDM Model per JEDEC JESD22−C101E − 1.0 kV 0.3 1.5 UVLO Adjust Input Power Dissipation and Thermal Characteristics DW Suffix, Plastic Package, Case 751G TA = 25°C Thermal Resistance, Junction−to−Air P Suffix, Plastic Package, Case 648 TA = 25°C Thermal Resistance, Junction−to−Air °C 0 to + 70 − 40 to + 85 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. NOTE: This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. ORDERING INFORMATION Package Shipping† MC33067DWG SOIC−16W (Pb−Free) 47 Units / Rail MC33067DWR2G SOIC−16W (Pb−Free) 1000 / Tape & Reel NCV33067DWR2G* SOIC−16W (Pb−Free) 1000 / Tape & Reel MC33067PG PDIP−16 (Pb−Free) 25 Units / Rail MC34067DWG SOIC−16W (Pb−Free) 47 Units / Rail MC34067DWR2G SOIC−16W (Pb−Free) 1000 / Tape & Reel MC34067PG PDIP−16 (Pb−Free) 25 Units / Rail Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 2 MC34067, MC33067, NCV33067 ELECTRICAL CHARACTERISTICS (VCC = 12 V [Note 2], ROSC= 18.2 k, RVFO = 2940 W, COSC = 300 pF, RT = 2370 W, CT = 300 pF, CL = 1.0 nF. For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies (Note 3), unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Vref 5.0 5.1 5.2 V Line Regulation (VCC = 10 V to 18 V) Regline − 1.0 20 mV Load Regulation (IO = 0 mA to 10 mA) Regload − 1.0 20 mV Vref 4.9 − 5.3 V 30 25 100 100 190 225 4.8 V REFERENCE SECTION Reference Output Voltage (IO = 0 mA, TJ = 25°C) Total Output Variation Over Line, Load, and Temperature Output Short Circuit Current (0°C to 70°C) (−40°C to 85°C) IO mA Reference Undervoltage Lockout Threshold Vth 3.8 4.3 ERROR AMPLIFIER Input Offset Voltage (VCM = 1.5 V) VIO − 1.0 10 mV Input Bias Current (VCM = 1.5 V) IIB − 0.2 1.0 mA Input Offset Current (VCM = 1.5 V) IIO − 0 0.5 mA Open Loop Voltage Gain (VCM = 1.5 V, VO = 2.0 V) AVOL 70 100 − dB Gain Bandwidth Product (f = 100 kHz) TA = 25°C TA = Tlow to Thigh GBW 3.0 2.7 5.0 − − − Input Common Mode Rejection Ratio (VCM = 1.5 V to 5.0 V) CMR 70 95 − dB Power Supply Rejection Ratio (VCC = 10 V to 18 V, f = 120 Hz) PSR 80 100 − dB Output Voltage Swing High State (Isource = 2.0 mA) Low State (Isink = 4.0 mA) VOH VOL 2.8 − 3.2 0.6 − 0.8 MHz V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. Maximum package power dissipation limits must be observed. 2. Adjust VCC above the Startup Threshold voltage before setting to 12 V. 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 4. Tlow = 0°C for MC34067 = − 40°C for MC33067, NCV33067 Thigh = + 70°C for MC34067 = + 85°C for MC33067, NCV33067 www.onsemi.com 3 MC34067, MC33067, NCV33067 ELECTRICAL CHARACTERISTICS (continued) (VCC = 12 V [Note 6], ROSC= 18.2 k, RVFO = 2940 W, COSC = 300 pF, RT = 2370 W, CT = 300 pF, CL = 1.0 nF. For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies (Note 7), unless otherwise noted.) Characteristic Symbol Min Typ Max Frequency (Error Amp Output Low) Total Variation (VCC = 10 V to 18 V, TA = TLow to THigh) fOSC(low) 490 525 550 Frequency (Error Amp Output High) Total Variation (VCC = 10 V to 18 V, TA = TLow to THigh) fOSC(high) 1850 2050 2200 Vin − 2.5 − 235 225 250 − 270 280 − − 9.5 9.0 0.8 1.5 10.3 9.7 1.2 2.0 − − Unit OSCILLATOR kHz kHz Oscillator Control Input Voltage, Pin 3 V ONE−SHOT Drive Output Off−Time TA = 25°C Total Variation (VCC = 10 V to 18 V, TA = TLow to THigh) tBlank ns DRIVE OUTPUTS V Output Voltage Low State (ISink = 20 mA) Low State (ISink = 200 mA) High State (ISource = 20 mA) High State (ISource = 200 mA) VOL VOH Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA) VOL(UVLO) − 0.8 1.2 V Output Voltage Rise Time (CL = 1.0 nF) tr − 20 50 ns Output Voltage Fall Time (CL = 1.0 nF) tf − 15 50 ns Input Threshold Vth 0.93 1.07 V Input Bias Current (VPin 10 = 0 V) IIB − − 2.0 − 10 mA tPLH(In/Out) − 60 100 ns Ichg 4.5 9.0 14 mA Idischg 3.0 8.0 − mA 14.8 8.0 16 9.0 17.2 10 8.0 7.6 9.0 8.6 10 9.6 FAULT COMPARATOR Propagation Delay to Drive Outputs (100 mV Overdrive) 1.0 SOFT−START Capacitor Charge Current (VPin 11 = 2.5 V) Capacitor Discharge Current (VPin 11 = 2.5 V) UNDERVOLTAGE LOCKOUT Startup Threshold, VCC Increasing Enable/UVLO Adjust Pin Open Enable/UVLO Adjust Pin Connected to VCC Vth(UVLO) Minimum Operating Voltage After Turn−On, VCC Decreasing Enable/UVLO Adjust Pin Open Enable/UVLO Adjust Pin Connected to VCC VCC(min) V V Enable/UVLO Adjust Shutdown Threshold Voltage Vth(Enable) 6.0 Enable/UVLO Adjust Input Current (Pin 9 = 0 V) Iin(Enable) − − 0.2 7.0 − 1.0 − − − 0.5 27 0.8 35 V mA TOTAL DEVICE Power Supply Current (Enable/UVLO Adjust Pin Open) Startup (VCC = 13.5 V) Operating (fOSC = 500 kHz) (Note 6) ICC mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Maximum package power dissipation limits must be observed. 6. Adjust VCC above the Startup Threshold voltage before setting to 12 V. 7. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 8. Tlow = 0°C for MC34067 = − 40°C for MC33067, NCV33067 Thigh = + 70°C for MC34067 = + 85°C for MC33067, NCV33067 www.onsemi.com 4 500 COSC = 200 pF 400 COSC = 500 pF 300 VCC = 12 V RVFO = ∞ RT = ∞ CT = 500 pF TA = 25°C 200 100 0 3500 COSC = 300 pF f OSC , OSCILLATOR FREQUENCY (kHz) ROSC, OSCILLATOR TIMING RESISTOR (kΩ ) MC34067, MC33067, NCV33067 Oscillator Discharge Time is Measured at the Drive Outputs. 0 20 40 60 80 tdischg, OSCILLATOR DISCHARGE TIME (ms) VCC = 12 V TA = 25°C ROSC = 18.2 k 3000 2500 2000 COSC = 300 pF 1500 1000 500 0 100 0 Figure 2. Oscillator Timing Resistor versus Discharge Time VOL, OUTPUT LOW STATE VOLTAGE (V) 60 RT, TIMING RESISTOR (k Ω ) 0.30 0.25 0.20 0.15 0.10 0 0.5 1.0 1.5 2.0 2.5 IOSC, OSCILLATOR CONTROL CURRENT (mA) 30 6.0 30 60 70 20 80 10 90 Phase 0 100 Phase Margin = 64° -10 110 -20 10 k 10M 0 0.3 0.6 1.0 3.0 tOS, ONE-SHOT PERIOD (ms) 6.0 10 -20 *Vref = 5.1 V VCC = 12 V RL = ∞ *Vref at TA = 25°C -30 -40 -50 120 *Vref = 5.0 V -10 -55 ∇ 100 k 1.0M f, FREQUENCY (Hz) V ref , REFERENCE OUTPUT VOLTAGE CHANGE (mV) Gain One-Shot Period is Measured at the Drive Outputs. Figure 5. One−Shot Timing Resistor versus Period 0, EXCESS PHASE (DEGREES) 40 CT = 500 pF 10 3.0 0.1 50 VCC = 12 V VO = 2.0 V RL = 100 k TA = 25°C CT = 200 pF CT = 300 pF 3.0 50 VCC = 12 V COSC = 500 pF ROSC = 100 k TA = 25°C 20 Figure 4. Error Amp Output Low State Voltage versus Oscillator Control Current A VOL, OPEN LOOP VOLTAGE GAIN (dB) 2000 Figure 3. Oscillator Frequency versus Oscillator Control Current 0.35 0.05 400 800 1200 1600 IOSC, OSCILLATOR CONTROL CURRENT (mA) Figure 6. Open Loop Voltage Gain and Phase versus Frequency *Vref = 5.2 V -25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 Figure 7. Reference Output Voltage Change versus Temperature www.onsemi.com 5 125 0 V sat , OUTPUT SATURATION VOLTAGE (V) V ref , REFERENCE OUTPUT VOLTAGE CHANGE (mV) MC34067, MC33067, NCV33067 TA = -40°C -10 TA = -20°C -20 TA = -125°C -30 -40 -50 VCC = 12 V 0 ∇ 20 40 60 80 Iref, REFERENCE SOURCE CURRENT (mA) 0 TA = 25°C -2.0 3.0 TA = -40°C 2.0 TA = 25°C 1.0 0 Source Saturation (Load to VCC) 0 CL = 1.0 nF TA = 25 °C 10% 1.6 0.8 0 VCC = 12 V Pin 10 = Vref TA = 25 °C 0 24 I CC, SUPPLY CURRENT (mA) f, OPERATING FREQUENCY (kHz) VCC = 12 V CL = 1.0 nF TA = 25 °C 1200 800 400 40 50 60 70 ICC, SUPPLY CURRENT (mA) 80 2.0 4.0 6.0 8.0 Idchg, CAPACITOR DISCHARGE CURRENT (mA) 10 Figure 11. Soft−Start Saturation Voltage versus Capacitor Discharge Current 2000 30 1.0 2.4 Figure 10. Drive Output Waveform 0 0.4 0.6 0.8 IO, OUTPUT LOAD CURRENT (A) 3.2 20 ns/DIV 1600 0.2 GND Figure 9. Drive Output Saturation Voltage versus Load Current V OL , SOFT-START SATURATION VOLTAGE (V) Figure 8. Reference Output Voltage Change versus Source Current 90% VCC = 12 V 80 ms Pulsed Load 120 Hz Rate TA = -40°C -3.0 100 Source Saturation (Load to Ground) VCC -1.0 20 Figure 12. Operating Frequency versus Supply Current Enable/UVLO Adjust Pin Open (Solid Line) 16 12 8.0 Enable/UVLO Adjust Pin to VCC (Dashed Line) 4.0 0 90 TA = 25 °C 0 4.0 8.0 12 VCC, SUPPLY VOLTAGE (V) 16 20 Figure 13. Supply Current versus Supply Voltage www.onsemi.com 6 MC34067, MC33067, NCV33067 VCC 15 50k Enable / UVLO Adjust 7.0k 7.0k 9 50k 5.1 V Reference VCC UVLO 8.0 V Vref Vref 5 Vref UVLO Vref OSC Charge 4.2/4.0 V D1 Q1 COSC Steering Flip-Flop Q T RQ Oscillator OSC RC ROSC 14 Q2 1 2 IOSC 4.9V/3.6 V One-Shot RC CT Oscillator 16 Control Current RT IOSC Error Amp Output 6 8 Noninverting Input Inverting Input 7 Soft-Start Power 13 Ground One-Shot Output B 12 4.9 V/3.6 V 3.1V 3 RVFO Q Error Amp Clamp Error Amp Output A R Fault Comparator Fault Input S 10 1.0 V Fault Latch 9.0 mA 11 4 Ground Figure 14. MC34067 Representative Block Diagram 5.1 V COSC 3. 6 V One-Shot 5.1 V 3.6 V Output A Output B tOS tOS tOS tOS High State Error Amp output, minimum IOSC current occurring at minimum input voltage, maximum load. tOS tOS Low State Error Amp output, maximum IOSC current occurring at maximum input voltage, minimum load. Figure 15. Timing Diagram www.onsemi.com 7 MC34067, MC33067, NCV33067 OPERATING DESCRIPTION Introduction frequencies exceeding 1.0 MHz. The Error Amplifier can control the oscillator frequency over a 1000:1 frequency range, and both the minimum and maximum frequencies are easily and accurately programmed by the proper selection of external components. The functional diagram of the Oscillator and One−Shot timer is shown in Figure 16. The oscillator capacitor (COSC) is initially charged by transistor Q1. When COSC exceeds the 4.9 V upper threshold of the oscillator comparator, the base of Q1 is pulled low allowing COSC to discharge through the external resistor, (ROSC), and the oscillator control current, (IOSC). When the voltage on COSC falls below the 3.6 V lower threshold of the comparator, Q1 turns on and again charges COSC. COSC charges from 3.6 V to 5.1 V in less than 50 ns. The high slew rate of COSC and the propagation delay of the comparator make it difficult to control the peak voltage. This accuracy issue is overcome by clamping the base of Q1 through a diode to a voltage reference. The peak voltage of the oscillator waveform is thereby precisely set at 5.1 V. As power supply designers have strived to increase power conversion efficiency and reduce passive component size, high frequency resonant mode power converters have emerged as attractive alternatives to conventional pulse−width modulated control. When compared to pulse−width modulated converters, resonant mode control offers several benefits including lower switching losses, higher efficiency, lower EMI emission, and smaller size. A new integrated circuit has been developed to support this trend in power supply design. The MC34067 Resonant Mode Controller is a high performance bipolar IC dedicated to variable frequency power control at frequencies exceeding 1.0 MHz. This integrated circuit provides the features and performance specifically for zero voltage switching resonant mode power supply applications. The primary purpose of the control chip is to provide a fixed off−time to the gates of external power MOSFETs at a repetition rate regulated by a feedback control loop. Additional features of the IC ensure that system startup and fault conditions are administered in a safe, controlled manner. A simplified block diagram of the IC is shown on the front page, which identifies the main functional blocks and the block−to−block interconnects. Figure 14 is a detailed functional diagram which accurately represents the internal circuitry. The various functions can be divided into two sections. The first section includes the primary control path which produces precise output pulses at the desired frequency. Included in this section are a variable frequency Oscillator, a One−Shot, a pulse Steering Flip−Flop, a pair of power MOSFET Drivers, and a wide bandwidth Error Amplifier. The second section provides several peripheral support functions including a voltage reference, undervoltage lockout, soft−start circuit, and a fault detector. VCC OSC Charge Vref VCC Q1 D1 1 OSC RC ROSC COSC Oscillator 2 IOSC 4.9 V/3.6 V One-Shot RC CT RT Oscillator 10 Control Current IOSC 3 RVFO 6 Error Amp Output One-Shot 4.9V/3.6V 3.1 V Error Amp Clamp Figure 16. Oscillator and One−Shot Timer Primary Control Path The output pulse width and repetition rate are regulated through the interaction of the variable frequency Oscillator, One−Shot timer and Error Amplifier. The Oscillator triggers the One−Shot which generates a pulse that is alternately steered to a pair of totem pole output drivers by a toggle Flip−Flop. The Error Amplifier monitors the output of the regulator and modulates the frequency of the Oscillator. High speed Schottky logic is used throughout the primary control channel to minimize delays and enhance high frequency characteristics. The frequency of the Oscillator is modulated by varying the current flowing out of the Oscillator Control Current (IOSC) pin. The IOSC pin is the output of a voltage regulator. The input of the voltage regulator is tied to the variable frequency oscillator. The discharge current of the Oscillator increases by increasing the current out of the IOSC pin. Resistor RVFO is used in conjunction with the Error Amp output to change the IOSC current. Maximum frequency occurs when the Error Amplifier output is at its low state with a saturation voltage of 0.1 V at 1.0 mA. The minimum oscillator frequency will result when the IOSC current is zero, and COSC is discharged through the external resistor (ROSC). This occurs when the Error Amplifier output is at its high state of 2.5 V. The minimum and maximum oscillator frequencies are programmed by the proper selection of resistor ROSC and RVFO. Oscillator The characteristics of the variable frequency Oscillator are crucial for precise controller performance at high operating frequencies. In addition to triggering the One−Shot timer and initiating the output deadtime, the oscillator also determines the initial voltage for the one−shot capacitor. The Oscillator is designed to operate at www.onsemi.com 8 MC34067, MC33067, NCV33067 Error Amplifier The minimum frequency is programmed by ROSC using Equation 1: A fully accessible high performance Error Amplifier is provided for feedback control of the power supply system. The Error Amplifier is internally compensated and features dc open loop gain greater than 70 dB, input offset voltage of less than 10 mV and a guaranteed minimum gain−bandwidth product of 2.5 MHz. The input common mode range extends from 1.5 V to 5.1 V, which includes the reference voltage. 1 − t PD t (max) − 70 ns ƒ(min) R OSC = = 0.348 C OSC C OSC ȏ n 5.1 3.6 where tPD is the internal propagation delay. ǒ Ǔ (eq. 1) The maximum oscillator frequency is set by the current through resistor RVFO. The current required to discharge COSC at the maximum oscillator frequency can be calculated by Equation 2: I (max) = C OSC 5.1 − 3.6 1 ƒ(max) Oscillator Control Current IOSC − IR OSC = 5.1 − 3.6 ε ROSC ǒ − = 1.5 R OSC ε RVFO 6 (eq. 2) Error Amp Clamp Error Amp Output The discharge current through ROSC must also be known and can be calculated by Equation 3: ǒ 3.1 V 3 = 1.5COSC ƒ(max) 1 ƒ (min) R OSC COSC 8 Noninverting Input Ǔ 1 Inverting Input Ǔ (eq. 3) Error Amp Figure 17. Error Amplifier and Clamp ƒ(min) R OSC COSC When the Error Amplifier output is coupled to the IOSC pin by RVFO, as illustrated in Figure 17, it provides the Oscillator Control Current, IOSC. The output swing of the Error Amplifier is restricted by a clamp circuit to improve its transient recovery time. Resistor RVFO can now be calculated by Equation 4: 2.5 − V EAsat RVFO = I(max) − I R OSC 7 (eq. 4) Output Section One−Shot Timer The pulse(tOS), generated by the Oscillator and One−Shot timer is gated to dual totem−pole output drives by the Steering Flip−Flop shown in Figure 18. Positive transitions of tOS toggle the Flip−Flop, which causes the pulses to alternate between Output A and Output B. The flip−flop is reset by the undervoltage lockout circuit during startup to guarantee that the first pulse appears at Output A. The One−Shot is designed to disable both outputs simultaneously providing a deadtime before either output is enabled. The One−Shot capacitor (CT) is charged concurrently with the oscillator capacitor by transistor Q1, as shown in Figure 16. The one−shot period begins when the oscillator comparator turns off Q1, allowing CT to discharge. The period ends when resistor RT discharges CT to the threshold of the One−Shot comparator. The lower threshold of the One−Shot is 3.6 V. By choosing CT, RT can by solved by Equation 5: RT = t OS ǒ Ǔ C T ȏn 5.1 3.6 = VCC t OS 0.348 C T Output A (eq. 5) Steering Flip-Flop Errors in the threshold voltage and propagation delays through the output drivers will affect the One−Shot period. To guarantee accuracy, the output pulse of the control chip is trimmed to within 5% of 250 ns with nominal values of RT and CT. The outputs of the Oscillator and One−Shot comparators are OR’d together to produce the pulse tOS, which drives the Flip−Flop and output drivers. The output pulse (tOS) is initiated by the Oscillator and terminated by the One−Shot comparator. With zero voltage resonant mode converters, the oscillator discharge time should never be set less than the one−shot period. Q T 14 Power Ground PWR GND 13 VCC RQ Output B 12 PWR GND Figure 18. Steering Flip−Flop and Output Drivers www.onsemi.com 9 MC34067, MC33067, NCV33067 The totem−pole output drivers are ideally suited for driving power MOSFETs and are capable of sourcing and sinking 1.5 A. Rise and fall times are typically 20 ns and 15 ns respectfully when driving a 1.0 nF load. High source/sink capability in a totem−pole driver normally increases the risk of high cross conduction current during output transitions. The MC34067 utilizes a unique design that virtually eliminates cross conduction, thus controlling the chip power dissipation at high frequencies. A separate power ground pin is provided to isolate the sensitive analog circuitry from large transient currents. VCC 15 50k Enable / UVLO Adjust 7.0k Vref 7.0k 5.1 V Reference 9 50k 8.0 V Vref 5 Vref UVLO VCC UVLO UVLO 4.2/4.0 V Figure 19. Undervoltage Lockout and Reference PERIPHERAL SUPPORT FUNCTIONS to external loads. The reference is trimmed to better than 2% initial accuracy and includes active short circuit protection. The MC34067 Resonant Controller provides a number of support and protection functions including a precision voltage reference, undervoltage lockout comparators, soft−start circuitry, and a fault detector. These peripheral circuits ensure that the power supply can be turned on and off in a controlled manner and that the system will be quickly disabled when a fault condition occurs. Fault Detection Converter protection from adverse operating conditions can be implemented with proper use of the Fault Comparator and Latch blocks that are illustrated in Figure 20. The Fault Comparator has an input threshold of 1.0 V and when exceeded, sets the Fault Latch and generates two logic signals that simultaneously disable the primary control path. The signal line labeled “Fault” connects directly to two gates that control the output drivers. This direct path reduces the driver turn−off propagation delay to approximately 70 ns. The Fault Latch output is OR’ed with the UVLO output that is derived from the Vref UVLO comparator, to produce the logic output labeled “UVLO+Fault”. This signal disables the Oscillator and the One−Shot by forcing both the COSC and CT capacitors to be continually charged. The Fault Latch is automatically reset during startup by a logic “1” that appears at the Vref UVLO comparator output. The latch can also be reset after startup by momentarily pulling the Enable/UVLO Adjust pin low to disable the Reference. Note that after activation, the Fault Latch will remain in a set state only as long as VCC is provided to the MC34067. Also, Drive Output B will assume a high state if the Fault input signal drops below the 1.0 V threshold level even after the Fault Latch has been set. In some applications this characteristic could be problematic but it can be easily remedied by AC coupling Drive Output B. Undervoltage Lockout and Voltage Reference Separate undervoltage lockout comparators sense the input VCC voltage and the regulated reference voltage as illustrated in Figure 19. When VCC increases to the upper threshold voltage, the VCC UVLO comparator enables the Reference Regulator. After the Vref output of the Reference Regulator rises to 4.2 V, the Vref UVLO comparator switches the UVLO signal to a logic zero state enabling the primary control path. Reducing VCC to the lower threshold voltage causes the VCC UVLO comparator to disable the Reference Regulator. The Vref UVLO comparator then switches the UVLO output to a logic one state disabling the controller. The Enable/UVLO Adjust pin allows the power supply designer to select the VCC UVLO threshold voltages. When this pin is open, the comparator switches the controller on at 16 V and off at 9.0 V. If this pin is connected to the VCC terminal, the upper and lower thresholds are reduced to 9.0 V and 8.6 V, respectively. Forcing the Enable/UVLO Adjust pin low will pull the VCC UVLO comparator input low (through an internal diode) turning off the controller. The Reference Regulator provides a precise 5.1 V reference to internal circuitry and can deliver up to 10 mA www.onsemi.com 10 MC34067, MC33067, NCV33067 Soft−Start Circuit Fault UVLO The Soft−Start circuit shown in Figure 20 forces the variable frequency Oscillator to start at the maximum frequency and ramp downward until regulated by the feedback control loop. The external capacitor at the CSoft−Start terminal is initially discharged by the UVLO+Fault signal. The low voltage on the capacitor passes through the Soft−Start Buffer to hold the Error Amplifier output low. After UVLO+Fault switches to a logic zero, the soft−start capacitor is charged by a 9.0 mA current source. The buffer allows the Error Amplifier output to follow the soft−start capacitor until it is regulated by the Error Amplifier inputs. The soft−start function is generally applicable to controllers operating below resonance and can be disabled by simply opening the CSoft−Start terminal. UVLO + Fault R Q S 9.0 mA Fault Latch Error Amp Clamp CSoft-Start Fault Fault Comparator Input 10 1.0 V Soft-Start Buffer 11 6 Ground Figure 20. Fault Detector and Soft−Start APPLICATIONS INFORMATION The desired resonant frequency for the application circuit is calculated by Equation 6: The MC34067 is specifically designed for zero voltage switching (ZVS) quasi−resonant converter (QRC) applications. The IC is optimized for double−ended push−pull or bridge type converters operating in continuous conduction mode. Operation of this type of ZVS with resonant properties is similar to standard push−pull or bridge circuits in that the energy is transferred during the transistor on−time. The difference is that a series resonant tank is usually introduced to shape the voltage across the power transistor prior to turn−on. The resonant tank in this topology is not used to deliver energy to the output as is the case with zero current switch topologies. When the power transistor is enabled the voltage across it should already be zero, yielding minimal switching loss. Figure 21 shows a timing diagram for a half−bridge ZVS QRC. An application circuit is shown in Figure 22. The circuit built is a dc to dc half−bridge converter delivering 75 W to the output from a 48 V source. When building a zero voltage switch (ZVS) circuit, the objective is to waveshape the power transistor’s voltage waveform so that the voltage across the transistor is zero when the device is turned on. The purpose of the control IC is to allow a resonant tank to waveshape the voltage across the power transistor while still maintaining regulation. This is accomplished by maintaining a fixed deadtime and by varying the frequency; thus the effective duty cycle is changed. Primary side resonance can be used with ZVS circuits. In the application circuit, the elements that make the resonant tank are the primary leakage inductance of the transformer (LL) and the average output capacitance (COSS) of a power MOSFET (CR). ƒr = 1 2π (eq. 6) L L 2C R In the application circuit, the operating voltage is low and the value of COSS versus Drain Voltage is known. Because the COSS of a MOSFET changes with drain voltage, the value of the CR is approximated as the average COSS of the MOSFET. For the application circuit the average COSS can be calculated by Equation 7: CR = 2 * C OSS measured at 1 V 2 in (eq. 7) The MOSFET chosen fixes CR and that LL is adjusted to achieve the desired resonant frequency. However, the desired resonant frequency is less critical than the leakage inductance. Figure 21 shows the primary current ramping toward its peak value during the resonant transition. During this time, there is circulating current flowing through the secondary inductance, which effectively makes the primary inductance appear shorted. Therefore, the current through the primary will ramp to its peak value at a rate controlled by the leakage inductance and the applied voltage. Energy is not transferred to the secondary during this stage, because the primary current has not overcome the circulating current in the secondary. The larger the leakage inductance, the longer it takes for the primary current to slew. The practical effect of this is to lower the duty cycle, thus reducing the operating range. www.onsemi.com 11 MC34067, MC33067, NCV33067 The maximum duty cycle is controlled by the leakage inductance, not by the MC34067. The One−Shot in the MC34067 only assures that the power switch is turned on under a zero voltage condition. Adjust the one−shot period so that the output switch is activated while the primary current is slewing but before the current changes polarity. The resonant stage should then be designed to be as long as the time for the primary current to go to 0 A. 5.1 V COSC 3.6 V 5.1 V 3.6 V One-Shot Drive Output A Drive Output B Vin 1/2 Vin Input Voltage 0V + Iprimary Primary Current 0A - Iprimary Vin/Turns Ratio Output Rectifier Voltage Figure 21. Application Timing Diagram www.onsemi.com 12 www.onsemi.com 13 1.1k 10k 25 mVp−p 83.5% 84.2% V in = 48 V, I O = 15 A, fswitch = 1.0 MHz V in = 48 V, I O = 10 A, fswitch = 1.7 MHz V in = 48 V, I O = 15 A, fswitch = 1.0 MHz Output Ripple Efficiency 1N5819 1N5819 470 T2 3.9k 1.0k 1.0k MTP33N10E 100 1.0 1.0 100 T3 T1 1N5819 x 4 500pF 51/0.5W MBR2535 CTL 500pF 51/0.5W 30 L1 L2 2 L2 = 5 turns #48 AWG (1300 strands litz wire) Core: 0.5″ diameter air code Inductance = 100 nH L1 = 2 turns #48 AWG (1300 strands litz wire) Core: Philips 3F3 EP10−3F3 Bobbin: Philips EP10PCB1−8 Inductance = 1.8 μH T3 = Coilcraft D1870 (100 turns) T2 = All windings: 8 turns #36 AWG Core: Philips 3F3 EP7−3F3 Bobbin: Philips EP7PCB1−6 T1 = Primary: 12 turns #48 AWG (1300 strands litz wire) Secondary: 6 turns center tapped #48 AWG (1300 strands litz wire) Core: Philips 3F3 4312 020 4124 Bobbin: Philips 4322 021 3525 Primary Leakage Inductance = 1.0 μH 470pF 10 12 13 14 5 Vin 36 V to 56 V Insulators = Berquist Sil−Pad 1500 Heatsinks = AAVID Engineering Inc. 533402B02552 with clip MC34067−5803 Figure 22. Application Circuit 4.0 mV = ±0.039% 20 mV = ±0.198% Results V in = 48 V, IO = 10 A to 15 A Conditions 4 Load Regulation 11 7 8 220pF 6 3 16 2 Reference V in = 40 V to 56 V, IO =15 A Test 0.01 1500pF 2.7k 18k 1 9 15 Line Regulation 16k 1.6k 330pF 100pF 330pF 10 VCC Vout 5.0 V MC34067, MC33067, NCV33067 MC34067, MC33067, NCV33067 (Top View) (Bottom View) 5.0″ 3.875″ Figure 23. Printed Circuit Board and Component Layout www.onsemi.com 14 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PDIP−16 CASE 648−08 ISSUE V 16 1 SCALE 1:1 D A 16 9 E H E1 1 NOTE 8 b2 8 c B TOP VIEW END VIEW WITH LEADS CONSTRAINED NOTE 5 A2 A e/2 NOTE 3 L A1 C D1 e SEATING PLANE M eB END VIEW 16X b SIDE VIEW 0.010 M C A M B M NOTE 6 DATE 22 APR 2015 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY. 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). DIM A A1 A2 b b2 C D D1 E E1 e eB L M INCHES MIN MAX −−−− 0.210 0.015 −−−− 0.115 0.195 0.014 0.022 0.060 TYP 0.008 0.014 0.735 0.775 0.005 −−−− 0.300 0.325 0.240 0.280 0.100 BSC −−−− 0.430 0.115 0.150 −−−− 10 ° MILLIMETERS MIN MAX −−− 5.33 0.38 −−− 2.92 4.95 0.35 0.56 1.52 TYP 0.20 0.36 18.67 19.69 0.13 −−− 7.62 8.26 6.10 7.11 2.54 BSC −−− 10.92 2.92 3.81 −−− 10 ° GENERIC MARKING DIAGRAM* 16 STYLE 1: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. CATHODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE 15. ANODE 16. ANODE DOCUMENT NUMBER: DESCRIPTION: STYLE 2: PIN 1. COMMON DRAIN 2. COMMON DRAIN 3. COMMON DRAIN 4. COMMON DRAIN 5. COMMON DRAIN 6. COMMON DRAIN 7. COMMON DRAIN 8. COMMON DRAIN 9. GATE 10. SOURCE 11. GATE 12. SOURCE 13. GATE 14. SOURCE 15. GATE 16. SOURCE 98ASB42431B PDIP−16 XXXXXXXXXXXX XXXXXXXXXXXX AWLYYWWG 1 XXXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 WB CASE 751G ISSUE E 1 SCALE 1:1 DATE 08 OCT 2021 GENERIC MARKING DIAGRAM* 16 XXXXXXXXXXX XXXXXXXXXXX AWLYYWWG 1 XXXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASB42567B SOIC−16 WB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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