MC74ACT161N

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 Synchronous Presettable Binary Counter The MC74AC161/74ACT161 and MC74AC163/74ACT163 are high−speed synchronous modulo−16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The MC74AC161/74ACT161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The MC74AC163/74ACT163 has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. Synchronous Counting and Loading High−Speed Synchronous Expansion Typical Count Rate of 125 MHz Outputs Source/Sink 24 mA ′ACT161 and ′ACT163 Have TTL Compatible Inputs These are Pb−Free Devices VCC TC Q0 Q1 Q2 Q3 CET PE 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 *R CP P0 P1 P2 P3 CEP GND MARKING DIAGRAM 16 SOIC−16 D SUFFIX CASE 751B 16 1 xxx16yG AWLYWW 1 xxx y A WL Y WW G Features • • • • • • www.onsemi.com = AC or ACT = 1 or 3 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. Figure 1. Pinout: 16−Lead Packages Conductors (Top View) PIN ASSIGNMENT PIN FUNCTION CEP Count Enable Parallel Input CET Count Enable Trickle Input CP Clock Pulse Input MR (′161) Asynchronous Master Reset Input SR (′163) Synchronous Reset Input P0−P3 Parallel Data Inputs PE Parallel Enable Input Q0 −Q3 Flip−Flop Outputs TC Terminal Count Output © Semiconductor Components Industries, LLC, 2015 January, 2015 − Rev. 8 1 Publication Order Number: MC74AC161/D MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip−flops on the next rising edge of CP. With PE and MR (′161) or SR (′163) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The MC74AC161/ACT161 and MC74AC163/ACT163 use D−type edge−triggered flip−flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the MC74AC568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip−flops, counters or registers. Logic Equations: Count Enable = CEP•CET•PE TC = Q0•Q1•Q2•Q3•CET PE P0 P1 P2 P3 CEP CET TC CP *R Q0 Q1 Q2 Q3 *MR for ′161 *SR for ′163 Figure 2. Logic Symbol FUNCTIONAL DESCRIPTION The MC74AC161/ACT161 and MC74AC163/ACT163 count modulo−16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip−flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the ′161) occur as a result of, and synchronous with, the LOW−to−HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (′161), synchronous reset (′163), parallel load, count−up and hold. Five control inputs − Master Reset (MR, ′161), Synchronous Reset (SR, ′163), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) − determine the mode of 0 MODE SELECT TABLE *SR PE CET CEP L H H H H X L H H H X X H L X X X H X L Action on the Rising Clock Edge ( ) Reset (Clear) Load (Pn → Qn) Count (Increment) No Change (Hold) No Change (Hold) 1 2 3 4 15 5 14 6 13 7 12 11 10 9 8 *For ′163 only H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Figure 3. State Diagram www.onsemi.com 2 MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 P0 P1 P2 P3 PE ′161 ′163 CEP CET ′163 ONLY TC ′161 ONLY CP CP CP D CD CP Q D Q Q0 Q0 DETAIL A DETAIL A DETAIL A Q1 Q2 Q3 DETAIL A MR ′161 SR ′163 Q0 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 4. Logic Diagram MAXIMUM RATINGS Symbol Parameter Value Unit *0.5 to )7.0 V *0.5 v VI v VCC )0.5 V *0.5 v VO v VCC )0.5 V VCC DC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current $20 mA IOK DC Output Diode Current $50 mA IO DC Output Sink/Source Current $50 mA ICC DC Supply Current per Output Pin $50 mA IGND DC Ground Current per Output Pin $50 mA TSTG Storage Temperature Range *65 to )150 °C TL Lead temperature, 1 mm from Case for 10 Seconds TJ Junction temperature under Bias qJA (Note 1) 260 °C )150 °C Thermal Resistance (Note 2) 69.1 °C/W PD Power Dissipation in Still Air at 65°C (Note 3) 500 mW MSL Moisture Sensitivity FR Flammability Rating VESD ESD Withstand Voltage Human Body Model (Note 4) Machine Model (Note 5) Charged Device Model (Note 6) > 2000 > 200 > 1000 V ILatch−Up Latch−Up Performance Above VCC and Below GND at 85°C (Note 7) $100 mA Level 1 Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. 2. The package thermal impedance is calculated in accordance with JESD51−7. 3. 500 mW at 65°C; derate to 300 mW by 10 mW/ from 65°C to 85°C. 4. Tested to EIA/JESD22−A114−A. 5. Tested to EIA/JESD22−A115−A. 6. Tested to JESD22−C101−A. 7. Tested to EIA/JESD78. www.onsemi.com 3 MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage VIN, VOUT DC Input Voltage, Output Voltage (Ref. to GND) tr, tf Input Rise and Fall Time (Note 1) ′AC Devices except Schmitt Inputs Min Typ Max Unit ′AC 2.0 5.0 6.0 ′ACT 4.5 5.0 5.5 0 − VCC VCC @ 3.0 V − 150 − VCC @ 4.5 V − 40 − VCC @ 5.5 V − 25 − VCC @ 4.5 V − 10 − VCC @ 5.5 V − 8.0 − − − 140 °C −40 25 85 °C V V ns/V tr, tf Input Rise and Fall Time (Note 2) ′ACT Devices except Schmitt Inputs TJ Junction Temperature (PDIP) TA Operating Ambient Temperature Range IOH Output Current − High − − −24 mA IOL Output Current − Low − − 24 mA ns/V 1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. DC CHARACTERISTICS Symbol Parameter VCC (V) 74AC 74AC TA = +25°C TA = −40°C to +85°C Typ VIH VIL VOH VOL Guaranteed Limits 3.0 4.5 5.5 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1 V or VCC − 0.1 V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1 V or VCC − 0.1 V Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V 3.0 4.5 5.5 − − − 2.56 3.86 4.86 2.46 3.76 4.76 3.0 4.5 5.5 0.002 0.001 0.001 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 5.5 − − − 0.36 0.36 0.36 0.44 0.44 0.44 5.5 − ±0.1 5.5 − 5.5 5.5 Maximum Low Level Output Voltage Maximum Input Leakage Current IOLD †Minimum Dynamic Output Current ICC Conditions Minimum High Level Input Voltage IIN IOHD Unit Maximum Quiescent Supply Current V *VIN = VIL or VIH −12 mA IOH −24 mA −24 mA IOUT = 50 mA V V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA ±1.0 mA VI = VCC, GND − 75 mA VOLD = 1.65 V Max − − −75 mA VOHD = 3.85 V Min − 8.0 80 mA VIN = VCC or GND *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. www.onsemi.com 4 IOUT = −50 mA MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) VCC* (V) Parameter Symbol 74AC161 74AC161 TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. fmax Maximum Count Frequency 3.3 5.0 70 110 111 167 − − 60 95 − − MHz 3−3 tPLH Propagation Delay CP to Qn (PE Input HIGH or LOW) 3.3 5.0 2.0 1.5 7.0 5.0 12.0 9.0 1.5 1.0 13.5 9.5 ns 3−6 tPHL Propagation Delay CP to Qn (PE Input HIGH or LOW) 3.3 5.0 1.5 1.5 7.0 5.0 12.0 9.5 1.5 1.5 13.0 10.0 ns 3−6 tPLH Propagation Delay CP to TC 3.3 5.0 3.0 2.0 9.0 6.0 15.0 10.5 2.5 1.5 16.5 11.5 ns 3−6 tPHL Propagation Delay CP to TC 3.3 5.0 3.5 2.0 8.5 6.5 14.0 11.0 2.5 2.0 15.5 11.5 ns 3−6 tPLH Propagation Delay CET to TC 3.3 5.0 2.0 1.5 5.5 3.5 9.5 6.5 1.5 1.0 11.0 7.5 ns 3−6 tPHL Propagation Delay CET to TC 3.3 5.0 2.5 2.0 6.5 5.0 11.0 8.5 2.0 1.5 12.5 9.5 ns 3−6 tPHL Propagation Delay MR to Qn 3.3 5.0 2.0 1.5 6.0 5.5 12.0 9.5 1.5 1.5 13.5 10.0 ns 3−6 tPHL Propagation Delay MR to TC 3.3 5.0 3.5 2.5 10.0 8.5 15.0 13.0 3.0 2.5 17.5 13.5 ns 3−6 *Voltage Range 3.3 V is 3.3 V ±0.3 V. *Voltage Range 5.0 V is 5.0 V ±0.5 V. AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) Symbol VCC* (V) Parameter 74AC163 74AC163 TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. fmax Maximum Count Frequency 3.3 5.0 70 110 95 140 − − 60 95 − − MHz 3−3 tPLH Propagation Delay CP to Qn (PE Input HIGH or LOW) 3.3 5.0 2.0 1.5 7.5 5.5 12.5 9.0 1.5 1.0 13.5 9.5 ns 3−6 tPHL Propagation Delay CP to Qn (PE Input HIGH or LOW) 3.3 5.0 1.5 1.5 8.5 6.0 12.0 9.5 1.5 1.5 13.0 10.0 ns 3−6 tPLH Propagation Delay CP to TC 3.3 5.0 3.0 2.0 9.5 7.0 15.0 10.5 2.5 1.5 16.5 11.5 ns 3−6 tPHL Propagation Delay CP to TC 3.3 5.0 3.5 2.0 11.0 8.0 14.0 11.0 2.5 2.0 15.5 11.5 ns 3−6 tPLH Propagation Delay CET to TC 3.3 5.0 2.0 1.5 7.5 5.5 9.5 6.5 1.5 1.0 11.0 7.5 ns 3−6 tPHL Propagation Delay CET to TC 3.3 5.0 2.5 2.0 8.5 6.0 11.0 8.5 2.0 1.5 12.5 9.5 ns 3−6 *Voltage Range 3.3 V is 3.3 V ±0.3 V. *Voltage Range 5.0 V is 5.0 V ±0.5 V. www.onsemi.com 5 MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 AC OPERATING REQUIREMENTS Symbol VCC* (V) Parameter Typ 74AC161 74AC161 TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Unit Fig. No. Guaranteed Minimum ts Setup Time, HIGH or LOW Pn to CP 3.3 5.0 6.0 3.5 13.5 8.5 16.0 10.5 ns 3−9 th Hold Time, HIGH or LOW Pn to CP 3.3 5.0 −7.0 −4.0 −1.0 0 −0.5 0 ns 3−9 ts Setup Time, HIGH or LOW PE to CP 3.3 5.0 6.5 4.0 11.5 7.5 14.0 8.5 ns 3−9 th Hold Time, HIGH or LOW PE to CP 3.3 5.0 −6.0 −3.5 0 0.5 0 1.0 ns 3−9 ts Setup Time, HIGH or LOW CEP or CET to CP 3.3 5.0 3.0 2.0 6.0 4.5 7.0 5.0 ns 3−9 th Hold Time, HIGH or LOW CEP or CET to CP 3.3 5.0 −3.5 −2.0 0 0 0 0.5 ns 3−9 tw Clock Pulse Width (Load) HIGH or LOW 3.3 5.0 2.0 2.0 3.5 2.5 4.0 3.0 ns 3−6 tw Clock Pulse Width (Count) HIGH or LOW 3.3 5.0 2.0 2.0 4.0 3.0 4.5 3.5 ns 3−6 tw MR Pulse Width, LOW 3.3 5.0 3.0 2.5 5.5 4.5 7.5 6.0 ns 3−6 trec Recovery TIme MR to CP 3.3 5.0 −2.0 −1.0 −0.5 0 0 0.5 ns 3−9 *Voltage Range 3.3 V is 3.3 V ±0.3 V. *Voltage Range 5.0 V is 5.0 V ±0.5 V. www.onsemi.com 6 MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 AC OPERATING REQUIREMENTS Symbol VCC* (V) Parameter Typ 74AC163 74AC163 TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Unit Fig. No. Guaranteed Minimum ts Setup Time, HIGH or LOW Pn to CP 3.3 5.0 5.5 4.0 13.5 8.5 16.0 10.5 ns 3−9 th Hold Time, HIGH or LOW Pn to CP 3.3 5.0 −7.0 −5.0 −1.0 0 −0.5 0 ns 3−9 ts Setup Time, HIGH or LOW SR to CP 3.3 5.0 5.5 4.0 14 9.5 16.5 11.0 ns 3−9 th Hold Time, HIGH or LOW SR to CP 3.3 5.0 −7.5 −5.5 −1.0 −0.5 −0.5 0 ns 3−9 ts Setup Time, HIGH or LOW PE to CP 3.3 5.0 5.5 4.0 11.5 7.5 14.0 8.5 ns 3−9 th Hold Time, HIGH or LOW PE to CP 3.3 5.0 −7.5 −5.0 −1.0 −0.5 −0.5 0 ns 3−9 ts Setup Time, HIGH or LOW CEP or CET to CP 3.3 5.0 3.5 2.5 6.0 4.5 7.0 5.0 ns 3−9 th Hold Time, HIGH or LOW CEP or CET to CP 3.3 5.0 −4.5 −3.0 0 0 0 0.5 ns 3−9 tw Clock Pulse Width (Load) HIGH or LOW 3.3 5.0 3.0 2.0 3.5 2.5 4.0 3.0 ns 3−6 tw Clock Pulse Width (Count) HIGH or LOW 3.3 5.0 3.0 2.0 4.0 3.0 4.5 3.5 ns 3−6 *Voltage Range 3.3 V is 3.3 V ±0.3 V. *Voltage Range 5.0 V is 5.0 V ±0.5 V. www.onsemi.com 7 MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 DC CHARACTERISTICS Symbol Parameter VCC (V) 74ACT 74ACT TA = +25°C TA = −40°C to +85°C Typ Guaranteed Limits Unit Conditions VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT = 0.1 V or VCC − 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT = 0.1 V or VCC − 0.1 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V 4.5 5.5 − − 3.86 4.86 3.76 4.76 4.5 5.5 0.001 0.001 0.1 0.1 0.1 0.1 4.5 5.5 − − 0.36 0.36 0.44 0.44 V *VIN = VIL or VIH 24 mA IOL 24 mA VOL Maximum Low Level Output Voltage V V IOUT = −50 mA *VIN = VIL or VIH −24 mA IOH −24 mA IOUT = 50 mA IIN Maximum Input Leakage Current 5.5 − ±0.1 ±1.0 mA VI = VCC, GND DICCT Additional Max. ICC/Input 5.5 0.6 − 1.5 mA VI = VCC − 2.1 V IOLD †Minimum Dynamic Output Current 5.5 − − 75 mA VOLD = 1.65 V Max 5.5 − − −75 mA VOHD = 3.85 V Min 5.5 − 8.0 80 mA VIN = VCC or GND IOHD ICC Maximum Quiescent Supply Current *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. www.onsemi.com 8 MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) VCC* (V) Parameter Symbol 74ACT161 74ACT161 TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. fmax Maximum Count Frequency 5.0 115 125 − 100 − MHz 3−3 tPLH Propagation Delay CP to Qn (PE Input HIGH or LOW) 5.0 1.5 8.0 9.5 1.5 10.5 ns 3−6 tPHL Propagation Delay CP or Qn (PE Input HIGH or LOW) 5.0 1.5 8.0 10.5 1.5 11.5 ns 3−6 tPLH Propagation Delay CP to TC 5.0 2.0 11.0 11.0 1.5 12.5 ns 3−6 tPHL Propagation Delay CP to TC 5.0 1.5 11.0 12.5 1.5 13.5 ns 3−6 tPLH Propagation Delay CET to TC 5.0 1.5 7.5 8.5 1.5 10.0 ns 3−6 tPHL Propagation Delay CET to TC 5.0 1.5 8.0 9.5 1.5 10.5 ns 3−6 tPHL Propagation Delay MR to Qn 5.0 1.5 8.0 10.0 1.5 11.0 ns 3−6 tPHL Propagation Delay MR to TC 5.0 2.5 10.0 13.5 2.0 14.5 ns 3−6 *Voltage Range 5.0 V is 5.0 V ±0.5 V. AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) Symbol VCC* (V) Parameter 74ACT163 74ACT163 TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Unit Fig. No. Min Typ Max Min Max 5.0 120 140 − 105 − MHz 3−3 Propagation Delay CP to Qn (PE Input HIGH or LOW) 5.0 1.5 5.5 10.0 1.5 11.0 ns 3−6 tPHL Propagation Delay CP to Qn (PE Input HIGH or LOW) 5.0 1.5 6.0 11.0 1.5 12.0 ns 3−6 tPLH Propagation Delay CP to TC 5.0 2.5 7.0 11.5 2.0 13.5 ns 3−6 tPHL Propagation Delay CP to TC 5.0 3.0 8.0 13.5 2.0 15.0 ns 3−6 tPLH Propagation Delay CET to TC 5.0 2.0 5.5 9.0 1.5 10.5 ns 3−6 tPHL Propagation Delay CET to TC 5.0 2.0 6.0 10.0 2.0 11.0 ns 3−6 fmax Maximum Count Frequency tPLH *Voltage Range 5.0 V is 5.0 V ±0.5 V. www.onsemi.com 9 MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) Typ 74ACT161 74ACT161 TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Unit Fig. No. Guaranteed Minimum ts Setup Time, HIGH or LOW Pn to CP 5.0 7.0 9.5 11.5 ns 3−9 th Hold Time, HIGH or LOW Pn to CP 5.0 −3.0 0 0 ns 3−9 ts Setup Time, HIGH or LOW PE to CP 5.0 6.0 8.5 9.5 ns 3−9 th Hold Time, HIGH or LOW PE to CP 5.0 −3.5 − 0.5 − 0.5 ns 3−9 ts Setup Time, HIGH or LOW CEP or CET to CP 5.0 4.0 5.5 6.5 ns 3−9 th Hold Time, HIGH or LOW CEP or CET to CP 5.0 −2.0 0 0 ns 3−9 tw Clock Pulse Width (Load) HIGH or LOW 5.0 2.0 3.0 3.5 ns 3−6 tw Clock Pulse Width (Count) HIGH or LOW 5.0 2.0 3.0 3.5 ns 3−6 tw MR Pulse Width, LOW 5.0 3.0 3.0 7.5 ns 3−6 trec Recovery Time MR to CP 5.0 0 0 0.5 ns 3−9 *Voltage Range 5.0 V is 5.0 V ±0.5 V. www.onsemi.com 10 MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) 74ACT163 74ACT163 TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Unit Fig. No. Guaranteed Minimum ts Setup Time, HIGH or LOW Pn to CP 5.0 4.0 10.0 12.0 ns 3−9 th Hold Time, HIGH or LOW Pn to CP 5.0 −5.0 0.5 0.5 ns 3−9 ts Setup Time, HIGH or LOW SR to CP 5.0 4.0 10.0 11.5 ns 3−9 th Hold Time, HIGH or LOW SR to CP 5.0 −5.5 −0.5 −0.5 ns 3−9 ts Setup Time, HIGH or LOW PE to CP 5.0 4.0 8.5 10.5 ns 3−9 th Hold Time, HIGH or LOW PE to CP 5.0 −5.5 −0.5 0 ns 3−9 ts Setup Time, HIGH or LOW CEP or CET to CP 5.0 2.5 5.5 6.5 ns 3−9 th Hold Time, HIGH or LOW CEP or CET to CP 5.0 −3.0 0 0.5 ns 3−9 tw Clock Pulse Width HIGH or LOW 5.0 2.0 3.5 3.5 ns 3−6 tw Clock Pulse Width (Count) HIGH or LOW 5.0 2.0 3.5 3.5 ns 3−6 *Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 45 pF VCC = 5.0 V ORDERING INFORMATION Device Package MC74AC161DG MC74AC161DR2G MC74ACT161DG 48 Units / Rail SOIC−16 (Pb−Free) MC74ACT161DR2G MC74ACT163DG 2500 / Tape & Reel 48 Units / Rail 2500 / Tape & Reel MC74AC163DG MC74AC163DR2G Shipping† 48 Units / Rail SOIC−16 (Pb−Free) MC74ACT163DR2G 2500 / Tape & Reel 48 Units / Rail 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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