MC74HC174ADTR2

MC74HC174A Hex D Flip-Flop with Common Clock and Reset High–Performance Silicon–Gate CMOS The MC74HC174A is identical in pinout to the LS174. The device inputs are compatible with standard CMOS outputs; with pull–up resistors, they are compatible with LSTTL outputs. This device consists of six D flip–flops with common Clock and Reset inputs. Each flip–flop is loaded with a low–to–high transition of the Clock input. Reset is asynchronous and active–low. • • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1.0
A In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 162 FETs or 40.5 Equivalent Gates http://onsemi.com MARKING DIAGRAMS 16 16 MC74HC174AN AWLYYWW 1 PDIP–16 N SUFFIX CASE 648 1 16 16 HC174A AWLYWW RESET 1 16 VCC 1 Q0 2 15 Q5 D0 3 14 D5 SO–16 D SUFFIX CASE 751B D1 4 13 D4 Q1 5 12 Q4 D2 6 11 D3 Q2 7 10 Q3 GND 8 9 1 16 16 HC 174A ALYW 1 CLOCK TSSOP–16 DT SUFFIX CASE 948F Figure 1. Pin Assignment 1 FUNCTION TABLE Inputs Reset Clock D Q L X X L H H H H H L H  Semiconductor Components Industries, LLC, 2001 May, 2001 – Rev. 8 A L, WL Y, YY W, WW Output L L X No Change X No Change = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device 1 Package Shipping MC74HC174AN PDIP–16 2000/Box MC74HC174AD SOIC–16 48/Rail MC74HC174ADR2 SOIC–16 2500/Reel MC74HC174ADT TSSOP–16 96/Rail MC74HC174ADTR2 TSSOP–16 2500/Reel Publication Order Number: MC74HC174A/D MC74HC174A DATA INPUTS D0 3 2 D1 4 5 D2 D3 6 7 Q2 11 10 Q3 D4 13 12 Q4 14 15 D5 CLOCK Q0 Q1 NONINVERTING OUTPUTS Q5 9 PIN 16 = VCC PIN 8 = GND RESET 1 Figure 2. Logic Diagram DESIGN/VALUE TABLE ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Design Criteria Value Units Internal Gate Count* 40.5 ea. Internal Gate Propagation Delay 1.5 ns Internal Gate Power Dissipation 5.0
W .0075 pJ Speed Power Product *Equivalent to a two–input NAND gate. http://onsemi.com 2 MC74HC174A MAXIMUM RATINGS (Note 1) Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) 0.5 to 7.0 V VIN DC Input Voltage (Referenced to GND) 1.5 to VCC 1.5 V VOUT DC Output Voltage (Referenced to GND) (Note 2) 0.5 to VCC 0.5 V IIN DC Input Current, per Pin
20 mA IOUT DC Output Current, per Pin
25 mA ICC DC Supply Current, VCC and GND Pins
50 mA TSTG Storage Temperature Range 65 to 150
C TL Lead Temperature, 1 mm from Case for 10 Seconds 260
C TJ Junction Temperature Under Bias 150
C JA Thermal Resistance PDIP SOIC TSSOP 78 112 148
C/W PD Power Dissipation in Still Air at 85
C PDIP SOIC TSSOP 750 500 450 mW MSL Moisture Sensitivity FR Flammability Rating VESD ESD Withstand Voltage Human Body Model (Note 3) Machine Model (Note 4) Charged Device Model (Note 5) 2000 100 500 V ILATCH–UP Latch–Up Performance Above VCC and Below GND at 85
C (Note 6)
300 mA PDIP, SOIC, TSSOP Level 1 Oxygen Index: 30% – 35% UL–94–VO (0.125 in) 1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. 2. IO absolute maximum rating must be observed. 3. Tested to EIA/JESD22–A114–A. 4. Tested to EIA/JESD22–A115–A. 5. Tested to JESD22–C101–A. 6. Tested to EIA/JESD78. 7. For high frequency or heavy load considerations, see the ON Semiconductor High–Speed CMOS Data Book (DL129/D). ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage VIN, VOUT DC Input Voltage, Output Voltage TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 4) Min Max Unit 2.0 6.0 V 0 VCC V 55 125
C 0 0 0 1000 500 400 ns (Referenced to GND) (Referenced to GND) (Note 8) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 8. Unused inputs may not be left open. All inputs must be tied to a high– or low–logic input voltage level. http://onsemi.com 3 MC74HC174A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Guaranteed Limit ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ Symbol Parameter Test Conditions V
55
C to 25
C 85
C 125
C Unit VIH Minimum High–Level Input Voltage VOUT = 0.1 V or VCC – 0.1 V |IOUT|  20
A 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low–Level Input Voltage VOUT = 0.1 V or VCC – 0.1 V |IOUT|  20
A 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V VOH Minimum High–Level Output Voltage VIN = VIH or VIL |IOUT|  20
A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN = VIH or VIL |IOUT|  4.0 mA |IOUT|  5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 VIN = VIH or VIL |IOUT|  4.0 mA |IOUT|  5.2 mA VOL Maximum Low–Level Output Voltage VIN = VIH or VIL |IOUT|  20
A V IIN Maximum Input Leakage Current VIN = VCC or GND 6.0
0.1
1.0
1.0
A ICC Maximum Quiescent Supply Current (per Package) VIN = VCC or GND IOUT = 0
A 6.0 4.0 40 160
A 9. Information on typical parametric values, along with high frequency or heavy load considerations, can be found in the ON Semiconductor High–Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) VCC Guaranteed Limit ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ Symbol Parameter V
55
C to 25
C 85
C 125
C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 4 and 7) 2.0 4.5 6.0 6.0 30 35 4.8 24 28 4.0 20 24 MHz tPLH tPHL Maximum Propagation Delay, Clock to Q (Figures 5 and 7) 2.0 4.5 6.0 110 22 19 140 28 24 165 33 28 ns tPLH tPHL Maximum Propagation Delay, Reset to Q (Figures 2 and 7) 2.0 4.5 6.0 110 21 19 140 28 24 160 32 27 ns tTLH tTHL Maximum Output Transition Time, Any Output (Figures 4 and 7) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns Cin Maximum Input Capacitance 10 10 10 pF 10. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High–Speed CMOS Data Book (DL129/D). Typical @ 25
C, VCC = 5.0 V CPD Power Dissipation Capacitance, per Enabled Output (Note 11) 62 pF 11. Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see the ON Semiconductor High–Speed CMOS Data Book (DL129/D). http://onsemi.com 4 MC74HC174A TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit
55
C to 25
C VCC 85
C 125
C ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ Symbol Parameter Figure V Min Max Min Max Min Max Unit tsu Minimum Setup Time, Data to Clock 6 2.0 4.5 6.0 50 10 9.0 65 13 11 75 15 13 ns th Minimum Hold Time, Clock to Data 6 2.0 4.5 6.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 ns trec Minimum Recovery Time, Reset Inactive to Clock 5 2.0 4.5 6.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 ns tw Minimum Pulse Width, Clock 4 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns tw Minimum Pulse Width, Reset 5 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns tr, tf Maximum Input Rise and Fall Times 4 2.0 4.5 6.0 CLOCK 9 D0 3 RESET 1 D1 4 D2 6 D3 11 1000 500 400 C D Q Q Q Q 13 D Q D5 D Q R Figure 3. Expanded Logic Diagram http://onsemi.com 5 Q2 10 Q3 12 Q4 R C 14 7 R C D4 Q1 R C D 5 R C D Q0 R C D 2 1000 500 400 15 Q5 1000 500 400 ns MC74HC174A tr CLOCK tf VCC 90% 50% 10% tw GND GND tPHL tPLH tPHL Q 90% 50% 10% trec VCC 50% tTLH CLOCK tTHL Figure 4. Switching Waveform GND Figure 5. Switching Waveform TEST POINT VALID VCC DATA VCC 50% 1/fmax Q tw RESET OUTPUT 50% DEVICE UNDER TEST GND tsu th CL * VCC CLOCK 50% GND *Includes all probe and jig capacitance Figure 6. Switching Waveform Figure 7. Test Circuit http://onsemi.com 6 MC74HC174A PACKAGE DIMENSIONS PDIP–16 N SUFFIX CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C DIM A B C D F G H J K L M S L S SEATING PLANE –T– K H G D M J 16 PL 0.25 (0.010) T A M M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0
10
0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0
10
0.51 1.01 SOIC–16 D SUFFIX CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45
C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 7 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0
7
5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0
7
0.229 0.244 0.010 0.019 MC74HC174A PACKAGE DIMENSIONS TSSOP–16 DT SUFFIX CASE 948F–01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B –U– L SECTION N–N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A –V– M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. N F DETAIL E –W– C 0.10 (0.004) –T– SEATING PLANE DETAIL E H D DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0
8
INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0
8
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