MC74LCX240DT

MC74LCX240 Low−Voltage CMOS Octal Buffer With 5 V−Tolerant Inputs and Outputs (3−State, Inverting) http://onsemi.com The MC74LCX240 is a high performance, inverting octal buffer operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows MC74LCX240 inputs to be safely driven from 5 V devices. The MC74LCX240 is suitable for memory address driving and all TTL level bus oriented transceiver applications. Current drive capability is 24 mA at the outputs. The Output Enable (OE) input, when HIGH, disables the outputs by placing them in a HIGH Z condition. Features MARKING DIAGRAMS 20 SOIC−20 DW SUFFIX CASE 751D 1 LCX240 AWLYYWWG 20 1 • • • • • • • • • • • Designed for 2.3 to 3.6 V VCC Operation 5 V Tolerant − Interface Capability With 5 V TTL Logic Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0 V LVTTL Compatible LVCMOS Compatible 24 mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (10 mA) Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 mA ESD Performance: Human Body Model >2000 V Machine Model >200 V Pb−Free Packages are Available* 20 TSSOP−20 DT SUFFIX CASE 948E 1 LCX 240 ALYWG G 20 1 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 1 March, 2006 − Rev. 7 Publication Order Number: MC74LCX240/D MC74LCX240 1OE VCC 20 2OE 19 1O0 18 2D0 17 1O1 16 2D1 15 1O2 14 2D2 13 1O3 12 2D3 11 1D0 1D1 1D2 1 1OE 2 1D0 3 2O0 4 1D1 5 2O1 6 1D2 7 2O2 8 1D3 9 2O3 10 GND 1D3 1 2 4 6 8 18 16 14 12 1O0 1O1 1O2 1O3 Figure 1. Pinout: 20−Lead (Top View) 2OE 2D0 19 17 15 13 11 3 5 7 9 2O0 2O1 2O2 2O3 PIN NAMES Pins nOE 1Dn, 2Dn 1On, 2On Function Output Enable Inputs Data Inputs 3−State Outputs 2D1 2D2 2D3 Figure 2. LOGIC DIAGRAM TRUTH TABLE INPUTS 1OE 2OE L L H H L Z X = = = = 1Dn 2Dn L H X OUTPUTS 1On, 2On H L Z High Voltage Level Low Voltage Level High Impedance State High or Low Voltage Level and Transitions Are Acceptable; for ICC reasons, DO NOT FLOAT Inputs http://onsemi.com 2 MC74LCX240 MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO ICC IGND Parameter DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current Per Supply Pin DC Ground Current Per Ground Pin Value −0.5 to +7.0 −0.5 ≤ VI ≤ +7.0 −0.5 ≤ VO ≤ +7.0 −0.5 ≤ VO ≤ VCC + 0.5 −50 −50 +50 ±50 ±100 ±100 Output in 3−State Note 1 VI < GND VO < GND VO > VCC Condition Unit V V V V mA mA mA mA mA mA TSTG Storage Temperature Range −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Output in HIGH or LOW State. IO absolute maximum rating must be observed. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO IOH IOL IOH IOL TA Dt/DV Supply Voltage Input Voltage Output Voltage (HIGH or LOW State) (3−State) Parameter Operating Data Retention Only Min 2.0 1.5 0 0 0 Typ 3.3 3.3 Max 3.6 3.6 5.5 VCC 5.5 −24 24 −12 12 −40 0 +85 10 Unit V V V mA mA mA mA °C ns/V HIGH Level Output Current, VCC = 3.0 V − 3.6 V LOW Level Output Current, VCC = 3.0 V − 3.6 V HIGH Level Output Current, VCC = 2.7 V − 3.0 V LOW Level Output Current, VCC = 2.7 V − 3.0 V Operating Free−Air Temperature Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V ORDERING INFORMATION Device MC74LCX240DT MC74LCX240DTR2 MC74LCX240DTR2G MC74LCX240DWR2 MC74LCX240DWR2G Package TSSOP−20* TSSOP−20* TSSOP−20* SOIC−20 SOIC−20 (Pb−Free) Shipping† 75 Units / Rail 2000 Tape & Reel 2000 Tape & Reel 1000 Tape & Reel 1000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. DC ELECTRICAL CHARACTERISTICS TA = −40°C to +85°C Symbol VIH VIL VOH Characteristic HIGH Level Input Voltage (Note 2) LOW Level Input Voltage (Note 2) HIGH Level Output Voltage Condition 2.7 V ≤ VCC ≤ 3.6 V 2.7 V ≤ VCC ≤ 3.6 V 2.7 V ≤ VCC ≤ 3.6 V; IOH = −100 mA VCC = 2.7 V; IOH = −12 mA VCC = 3.0 V; IOH = −18 mA VCC = 3.0 V; IOH = −24 mA 2. These values of VI are used to test DC electrical characteristics only. VCC − 0.2 2.2 2.4 2.2 Min 2.0 0.8 Max Unit V V V http://onsemi.com 3 MC74LCX240 DC ELECTRICAL CHARACTERISTICS (Continued) TA = −40°C to +85°C Symbol VOL Characteristic LOW Level Output Voltage Condition 2.7 V ≤ VCC ≤ 3.6 V; IOL = 100 mA VCC = 2.7 V; IOL= 12 mA VCC = 3.0 V; IOL = 16 mA VCC = 3.0 V; IOL = 24 mA II IOZ IOFF ICC DICC Input Leakage Current 3−State Output Current Power−Off Leakage Current Quiescent Supply Current 2.7 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 5.5 V 2.7 ≤ VCC ≤ 3.6 V; 0V ≤ VO ≤ 5.5 V; VI = VIH or V IL VCC = 0 V; VI or VO = 5.5 V 2.7 ≤ VCC ≤ 3.6 V; VI = GND or VCC 2.7 ≤ VCC ≤ 3.6 V; 3.6 ≤ VI or VO ≤ 5.5 V Increase in ICC per Input 2.7 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V Min Max 0.2 0.4 0.4 0.55 ±5.0 ±5.0 10 10 ±10 500 mA mA mA mA mA mA Unit V AC CHARACTERISTICS (tR = tF = 2.5 ns; CL = 50 pF; RL = 500 W) Limits TA = −40°C to +85°C VCC = 3.0 V to 3.6 V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Parameter Propagation Delay Input to Output Output Enable Time to High and Low Level Output Disable Time From High and Low Level Output−to−Output Skew (Note 3) Waveform 1 2 2 Min 1.5 1.5 1.5 1.5 1.5 1.5 Max 6.5 6.5 8.0 8.0 7.0 7.0 1.0 1.0 VCC = 2.7 V Max 7.5 7.5 9.0 9.0 8.0 8.0 Unit ns ns ns ns 3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. DYNAMIC SWITCHING CHARACTERISTICS TA = +25°C Symbol VOLP VOLV Characteristic Dynamic LOW Peak Voltage (Note 4) Dynamic LOW Valley Voltage (Note 4) Condition VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V Min Typ 0.8 0.8 Max Unit V V 4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is measured in the LOW state. CAPACITIVE CHARACTERISTICS Symbol CIN COUT CPD Parameter Input Capacitance Output Capacitance Power Dissipation Capacitance Condition VCC = 3.3 V, VI = 0 V or VCC VCC = 3.3 V, VI = 0 V or VCC 10 MHz, VCC = 3.3 V, VI = 0 V or VCC Typical 7 8 25 Unit pF pF pF http://onsemi.com 4 MC74LCX240 2.7 V 1Dn, 2Dn 1.5 V tPHL 1On, 2On 1.5 V 1.5 V 0V tPLH 1.5 V VOL WAVEFORM 1 − PROPAGATION DELAYS tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns VOH 2.7 V 1OE, 2OE tPZH 1On, 2On 1.5 V tPHZ 1.5 V 0V VCC VOH − 0.3 V ≈0V tPZL 1On, 2On 1.5 V VOL + 0.3 V GND WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns tPLZ ≈ 3.0 V Figure 3. Waveforms VCC R1 CL RL 6V OPEN GND PULSE GENERATOR RT DUT TEST tPLH, tPHL tPZL, tPLZ Open Collector/Drain tPLH and tPHL tPZH, tPHZ SWITCH Open 6V 6V GND CL = 50pF or equivalent (Includes jig and probe capacitance) RL = R1 = 500W or equivalent RT = ZOUT of pulse generator (typically 50W) Figure 4. Test Circuit http://onsemi.com 5 MC74LCX240 PACKAGE DIMENSIONS SOIC−20 DW SUFFIX CASE 751D−05 ISSUE G D A 11 X 45 _ q H M B M 20 10X 0.25 E NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 1 10 20X B 0.25 M B TA S B S A SEATING PLANE h 18X e A1 T C http://onsemi.com 6 L MC74LCX240 PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE B 20X K REF M 0.15 (0.006) T U S 0.10 (0.004) TU S V S 2X L/2 20 11 L PIN 1 IDENT 1 10 B −U− J J1 N 0.15 (0.006) T U S A −V− N F C D 0.100 (0.004) −T− SEATING PLANE G H DETAIL E ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 7 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ SECTION N−N 0.25 (0.010) M DETAIL E K K1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ −W− DIM A B C D F G H J J1 K K1 L M MC74LCX240/D