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MM74HC164
8-Bit Serial-in/Parallel-out Shift Register
Features
General Description
■ Typical operating frequency: 50MHz
The MM74HC164 utilizes advanced silicon-gate CMOS
technology. It has the high noise immunity and low consumption of standard CMOS integrated circuits. It also
offers speeds comparable to low power Schottky
devices.
■ Typical propagation delay: 19ns (clock to Q)
■ Wide operating supply voltage range: 2V to 6V
■ Low input current: 1µA maximum
■ Low quiescent supply current: 80µA maximum
(74HC Series)
■ Fanout of 10 LS-TTL loads
This 8-bit shift register has gated serial inputs and
CLEAR. Each register bit is a D-type master/slave flipflop. Inputs A & B permit complete control over the
incoming data. A LOW at either or both inputs inhibits
entry of new data and resets the first flip-flop to the low
level at the next clock pulse. A high level on one input
enables the other input which will then determine the
state of the first flip-flop. Data at the serial inputs may be
changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements
will be entered. Data is serially shifted in and out of the
8-bit register during the positive going transition of the
clock pulse. Clear is independent of the clock and
accomplished by a low level at the CLEAR input.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by
internal diode clamps to VCC and ground.
Ordering Information
Order Number
MM74HC164M
MM74HC164MTC
MM74HC164N
Package
Number
Package Description
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1983 Fairchild Semiconductor Corporation
MM74HC164 Rev. 1.5.0
www.fairchildsemi.com
MM74HC164 — 8-Bit Serial-in/Parallel-out Shift Register
February 2008
Truth Table
Inputs
Outputs
Clear
Clock
A
B
QA
QB ... QH
L
X
X
X
L
L ... L
H
L
X
X
QAO
QBO ... QHO
H
↑
H
H
H
QAn ... QGn
H
↑
L
X
L
QA ... QGn
H
↑
X
L
L
QAn ... QGn
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Irrelevant (any input, including transitions)
↑ = Transition from LOW-to-HIGH level.
QAO, QBO, QHO = the level of QA, QB, or QH,
respectively, before the indicated steady state input
conditions were established.
QAn, QGn = The level of QA or QG before the most
recent ↑ transition of the clock; indicated a one-bit shift.
Top View
Logic Diagram
©1983 Fairchild Semiconductor Corporation
MM74HC164 Rev. 1.5.0
www.fairchildsemi.com
2
MM74HC164 — 8-Bit Serial-in/Parallel-out Shift Register
Connection Diagram
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
VCC
Supply Voltage
VIN
DC Input Voltage
–1.5 to VCC+1.5V
DC Output Voltage
–0.5 to VCC+0.5V
VOUT
IIK, IOK
–0.5 to +7.0V
Clamp Diode Current
±20mA
IOUT
DC Output Current, per pin
±25mA
ICC
DC VCC or GND Current, per pin
±50mA
TSTG
PD
Storage Temperature Range
–65°C to +150°C
Power Dissipation
Note 2
600mW
S.O. Package only
TL
500mW
Lead Temperature (Soldering 10 seconds)
260°C
Notes:
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
VIN, VOUT
TA
t r, t f
Parameter
Min.
Max.
Units
Supply Voltage
2
6
V
DC Input or Output Voltage
0
VCC
V
–40
+85
°C
Operating Temperature Range
Input Rise or Fall Times
VCC = 2.0V
1000
ns
VCC = 4.5V
500
ns
VCC = 6.0V
400
ns
©1983 Fairchild Semiconductor Corporation
MM74HC164 Rev. 1.5.0
www.fairchildsemi.com
3
MM74HC164 — 8-Bit Serial-in/Parallel-out Shift Register
Absolute Maximum Ratings(1)
TA = –40°C
to 85°C
TA = 25°C
Symbol
Parameter
VCC (V)
VIH
Minimum HIGH Level
Input Voltage
2.0
1.5
1.5
1.5
4.5
3.15
3.15
3.15
6.0
4.2
4.2
4.2
2.0
0.5
0.5
0.5
4.5
1.35
1.35
1.35
6.0
1.8
1.8
1.8
2.0
1.9
1.9
1.9
4.5
4.4
4.4
4.4
6.0
5.9
5.9
5.9
VIL
VOH
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
2.0
4.5
Conditions
VIN = VIH or VIL,
|IOUT| ≤ 20µA
6.0
VOL
Maximum LOW Level
Output Voltage
Typ.
TA = –55°C
to 125°C
Guaranteed Limits
4.5
VIN = VIH or VIL,
|IOUT| ≤ 4.0mA
4.2
3.98
3.84
3.7
6.0
VIN = VIH or VIL,
|IOUT| ≤ 5.2mA
5.7
5.48
5.34
5.2
2.0
VIN = VIH or VIL,
|IOUT| ≤ 20µA
0
0.1
0.1
0.1
0
0.1
0.1
0.1
0
0.1
0.1
0.1
4.5
6.0
4.5
VIN = VIH or VIL,
|IOUT| ≤ 4.0mA
0.2
0.26
0.33
0.4
6.0
VIN = VIH or VIL,
|IOUT| ≤ 5.2mA
0.2
0.26
0.33
0.4
Units
V
V
V
V
IIN
Maximum Input
Current
6.0
VIN = VCC or GND
±0.1
±1.0
±1.0
µA
ICC
Maximum Quiescent
Supply Current
6.0
VIN = VCC or GND,
IOUT = 0µA
8.0
80
160
µA
Note:
3. For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V
values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V
respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at
the higher voltage and so the 6.0V values should be used.
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15pF, tr = tf = 6ns
Symbol
fMAX
Parameter
Conditions
Typ.
Maximum Operating Frequency
Guaranteed
Limit
Units
30
MHz
tPHL, tPLH
Maximum Propagation Delay, Clock to
Output
19
30
ns
tPHL
Maximum Propagation Delay, Clear to
Output
23
35
ns
tREM
Minimum Removal Time, Clear to Clock
–2
0
ns
tS
Minimum Setup Time, Data to Clock
12
20
ns
tH
Minimum Hold Time, Clock to Data
1
5
ns
tW
Minimum Pulse Width, Clear or Clock
10
16
ns
©1983 Fairchild Semiconductor Corporation
MM74HC164 Rev. 1.5.0
www.fairchildsemi.com
4
MM74HC164 — 8-Bit Serial-in/Parallel-out Shift Register
DC Electrical Characteristics(3)
CL = 50pF, tr = tf = 6ns (unless otherwise specified)
TA = 25°C
Symbol
fMAX
Parameter
Maximum Operating
Frequency
VCC (V)
Conditions
Typ.
TA = –40°C TA = –55°C
to 85°C
to 125°C
Guaranteed Limits
2.0
5
4
3
4.5
27
21
18
31
24
20
2.0
6.0
115
175
218
254
4.5
13
35
44
51
6.0
20
30
38
44
2.0
140
205
256
297
4.5
28
41
51
59
6.0
24
35
44
51
2.0
–7
0
0
0
4.5
–3
0
0
0
6.0
–2
0
0
0
2.0
25
100
125
150
4.5
14
20
25
30
6.0
12
17
21
25
2.0
–2
5
5
5
4.5
0
5
5
5
6.0
1
5
5
5
2.0
22
80
100
120
4.5
11
16
20
24
6.0
10
14
18
20
2.0
75
95
110
4.5
15
19
22
6.0
13
16
19
Maximum Input
Rise and Fall Time
2.0
1000
1000
1000
4.5
500
500
500
400
400
400
CPD
Power Dissipation
Capacitance(4)
5.0
CIN
Maximum Input
Capacitance
tPHL, tPLH Maximum Propagation
Delay, Clock to Output
tPHL
tREM
tS
tH
tW
Maximum Propagation
Delay, Clear to Output
Minimum Removal
Time, Clear to Clock
Minimum Setup Time,
Data to Clock
Minimum Hold Time,
Clock to Data
Minimum Pulse Width
Clear or Clock
tTHL, tTLH Maximum Output
Rise and Fall Time
tr, tf
6.0
(per package)
150
5
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
pF
10
10
10
pF
Note:
4. CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic
current consumption, IS = CPD VCC f + ICC.
©1983 Fairchild Semiconductor Corporation
MM74HC164 Rev. 1.5.0
www.fairchildsemi.com
5
MM74HC164 — 8-Bit Serial-in/Parallel-out Shift Register
AC Electrical Characteristics
0.65
A
0.43TYP
14
8
B
6.4
6.10
3.2
1
PIN#1 IDENT
0.2 C B A
7
TOP VIEW
1.65
ALL LEAD TIPS
0.45
RECOMMENDED LAND PATTERN
1.2 MAX
0.30
0.19
ALL LEAD TIPS
0.1 C
0.65
SEE DETAIL A
0.90+0.15
-0.10
0.13
A B
0.20
0.09
C
C
FRONT VIEW
0.09 MIN
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 2009.
E. LANDPATTERN STANDARD: SOP65P640X110-14M.
F. DRAWING FILE NAME: MKT-MTC14rev7.
GAGE PLANE
0.09 MIN
1.00
0.25
SEATING PLANE
DETAIL A
8.75
8.50
A
7.62
14
8
14
B
0.65
8
4.00
3.80
6.00
1
PIN #1
IDENT.
1.27
(0.33)
TOP VIEW
5.60
7
0.51
0.35
0.25 M C B A
1.75 MAX
1.70
1
1.27
LAND PATTERN RECOMMENDATION
A
C
1.50
1.25
FRONT VIEW
0.25
0.10
0.50
0.25 x 45
R0.10
GAGE
PLANE
R0.10
0.36
8°
0°
0.90
0.50
(1.04)
0.10 C
0.25
0.19
SIDE VIEW
NOTES:
A. CONFORMS TO JEDEC MS-012,
VARIATION AB, ISSUE C
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS
D. LAND PATTERN STANDARD:
SOIC127P600X145-14M
E. CONFORMS TO ASME Y14.5M, 2009
D. DRAWING FILENAME: MKT-M14Arev14
SEATING PLANE
DETAIL A
SCALE 16 : 1
7
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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