MSQA6V1W5T2G

MSQA6V1W5T2G, SZMSQA6V1W5T2G ESD Protection Diode Array Low Clamping Voltage This quad monolithic silicon voltage suppressor is designed for applications requiring transient overvoltage protection capability. It is intended for use in voltage and ESD sensitive equipment such as computers, printers, business machines, communication systems, medical equipment, and other applications. Its quad junction common anode design protects four separate lines using only one package. These devices are ideal for situations where board space is at a premium. www.onsemi.com SCALE 2:1 SC−88A/SOT−323 CASE 419A Features • • • • • • • Low Clamping Voltage Stand Off Voltage 3 V Low Leakage < 1 mA @ 3 V SC−88A Package Allows Four Separate Unidirectional Configurations IEC1000−4−2 Level 4 ESD Protection SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable Pb−Free Package is Available* 1 5 2 3 4 MARKING DIAGRAM Mechanical Characteristics: • • • • Void Free, Transfer−Molded, Thermosetting Plastic Case Corrosion Resistant Finish, Easily Solderable Package Designed for Optimal Automated Board Assembly Small Package Size for High Density Applications 61 M G G 61 = Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Package Shipping† MSQA6V1W5T2G SC−88A (Pb−Free) 3,000 / Tape & Reel SZMSQA6V1W5T2G SC−88A (Pb−Free) 3,000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2012 October, 2017 − Rev. 8 1 *T2 Suffix Devices are Packaged with Pin 1 Opposing Sprocket Hole. Publication Order Number: MSQA6V1W5T2/D MSQA6V1W5T2G, SZMSQA6V1W5T2G MAXIMUM RATINGS Rating Symbol Peak Power Dissipation @ 20 ms @TA ≤ 25°C (Note 1) Ppk Steady State Power − 1 Diode (Note 2) PD Value Unit 150 W 385 mW 325 3.1 °C/W mW/°C Thermal Resistance Junction−to−Ambient Above 25°C, Derate RqJA Maximum Junction Temperature TJmax 150 °C Operating Junction and Storage Temperature Range TJ Tstg −55 to +150 °C ESD Discharge MIL STD 883C − Method 3015−6 IEC1000−4−2, Air Discharge IEC1000−4−2, Contact Discharge VPP Lead Solder Temperature (10 s duration) 16 16 9 TL 260 kV °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Non−repetitive current per Figure 5. Derate per Figure 10. 2. Only 1 diode under power. For all 4 diodes under power, PD will be 25%. Mounted on FR−4 board with min pad. See Application Note AND8308/D for further description of survivability specs. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) I Parameter Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR VBR Working Peak Reverse Voltage VC VBR VRWM Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT IT Test Current IF Forward Current VF Forward Voltage @ IF Ppk Peak Power Dissipation C IF IR VF IT V IPP Uni−Directional Capacitance @ VR = 0 and f = 1.0 MHz *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS Breakdown Voltage VBR @ 1 mA (Vo) (Note 3) Device* MSQA6V1W5T2G Min Nom Max Leakage Current IRM @ VRWM = 3 V (mA) 6.1 6.6 7.2 1.0 Capacitance @ 0 V Bias (pF) Max VF @ IF = 200 mA (V) 90 1.25 3. VBR is measured with a pulse test current IT at an ambient temperature of 25°C. 4. For test procedure see Figures 3 and 4 and Application Note AND8307/D. *Include SZ-prefix devices where applicable. www.onsemi.com 2 VC Per IEC61000−4−2 (Note 4) Figures 1 and 2 See Below MSQA6V1W5T2G, SZMSQA6V1W5T2G Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec Device ESD Gun Under Oscilloscope Test 50 W Cable 50 W Figure 4. Diagram of ESD Test Setup www.onsemi.com 3 MSQA6V1W5T2G, SZMSQA6V1W5T2G The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 5. 8 x 20 ms Pulse Waveform www.onsemi.com 4 80 MSQA6V1W5T2G, SZMSQA6V1W5T2G 100 Ipp, PEAK PULSE CURRENT (AMPS) IF , FORWARD CURRENT (A) 1.0 0.1 0.01 0.001 0.7 0.8 0.9 1.0 1.1 2.5 ms SQUARE WAVE 1.0 1.2 0 10 20 15 25 VC, CLAMPING VOLTAGE (VOLTS) Figure 6. Forward Voltage Figure 7. Clamping Voltage versus Peak Pulse Current (Reverse Direction) 100 30 1000 10 1.0 2.5 ms SQUARE WAVE 100 10 NOTE: Non−Repetitive Surge. 0.1 1 0 2.0 4.0 6.0 8.0 12 10 100 VC, FORWARD CLAMPING VOLTAGE (VOLTS) Figure 9. Pulse Width 100 90 90 80 70 60 50 40 30 20 10 0 10 Figure 8. Clamping Voltage versus Peak Pulse Current (Forward Direction) 100 0 1 t, TIME (ms) TYPICAL CAPACITANCE (pF) 1 MHz FREQUENCY PEAK PULSE DERATING IN % OF PEAK POWER OR CURRENT @ TA = 25 ° C 5.0 VF, FORWARD VOLTAGE (VOLTS) Ppk , PEAK SURGE POWER (WATTS) Ipp, PEAK FORWARD PULSE CURRENT (AMPS) 0.6 10 25 50 75 100 125 150 175 200 80 70 60 50 40 30 20 10 0 0 TA, AMBIENT TEMPERATURE (°C) 1.0 2.0 3.0 BIAS VOLTAGE (VOLTS) Figure 10. Pulse Derating Curve Figure 11. Capacitance www.onsemi.com 5 1000 4.0 5.0 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SC−88A (SC−70−5/SOT−353) CASE 419A−02 ISSUE M SCALE 2:1 DATE 11 APR 2023 GENERIC MARKING DIAGRAM* XXXMG G *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. XXX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) STYLE 1: PIN 1. BASE 2. EMITTER 3. BASE 4. COLLECTOR 5. COLLECTOR STYLE 2: PIN 1. ANODE 2. EMITTER 3. BASE 4. COLLECTOR 5. CATHODE STYLE 3: PIN 1. ANODE 1 2. N/C 3. ANODE 2 4. CATHODE 2 5. CATHODE 1 STYLE 4: PIN 1. SOURCE 1 2. DRAIN 1/2 3. SOURCE 1 4. GATE 1 5. GATE 2 STYLE 6: PIN 1. EMITTER 2 2. BASE 2 3. EMITTER 1 4. COLLECTOR 5. COLLECTOR 2/BASE 1 STYLE 7: PIN 1. BASE 2. EMITTER 3. BASE 4. COLLECTOR 5. COLLECTOR STYLE 8: PIN 1. CATHODE 2. COLLECTOR 3. N/C 4. BASE 5. EMITTER STYLE 9: PIN 1. ANODE 2. CATHODE 3. ANODE 4. ANODE 5. ANODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42984B STYLE 5: PIN 1. CATHODE 2. COMMON ANODE 3. CATHODE 2 4. CATHODE 3 5. CATHODE 4 Note: Please refer to datasheet for style callout. If style type is not called out in the datasheet refer to the device datasheet pinout or pin assignment. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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