N64S830HAT22I

N64S830HA 64 kb Low Power Serial SRAMs 8 k x 8 Bit Organization Introduction The ON Semiconductor serial SRAM family includes several integrated memory devices including this 64 k serially accessed Static Random Access Memory, internally organized as 8 k words by 8 bits. The devices are designed and fabricated using ON Semiconductor’s advanced CMOS technology to provide both high−speed performance and low power. The devices operate with a single chip select (CS) input and use a simple Serial Peripheral Interface (SPI) serial bus. A single data in and data out line is used along with a clock to access data within the devices. The N64S830HA devices include a HOLD pin that allows communication to the device to be paused. While paused, input transitions will be ignored. The devices can operate over a wide temperature range of −40°C to +85°C and can be available in several standard package offerings. Features • • • • • • • • • • • • Power Supply Range: 2.5 to 3.6 V Very Low Standby Current: As low as 1 mA Very Low Operating Current: As low as 3 mA Simple Memory Control: Single chip select (CS) Serial input (SI) and serial output (SO) Flexible Operating Modes: Word read and write Page mode (32 word page) Burst mode (full array) Organization: 8 k x 8 bit Self Timed Write Cycles Built−in Write Protection (CS High) HOLD Pin for Pausing Communication High Reliability: Unlimited write cycles Green SOIC and TSSOP These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2012 June, 2012 − Rev. 12 1 http://onsemi.com MARKING DIAGRAMS B125 XXXXYZZ TSSOP−8 T SUFFIX CASE 948AL B115 XXXXYZZ SOIC−8 S SUFFIX CASE 751BD XXXX Y ZZ = Date Code = Assembly Code = Lot Traceability ORDERING INFORMATION Package Shipping† N64S830HAS22I SOIC−8 (Pb−Free) 100 Units / Tube N64S830HAT22I TSSOP−8 (Pb−Free) 100 Units / Tube N64S830HAS22IT SOIC−8 (Pb−Free) 3000 / Tape & Reel N64S830HAT22IT TSSOP−8 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: N64S830HA/D N64S830HA CS SO NC VSS 1 CS VCC HOLD SCK SI 1 VCC SO HOLD NC SCK VSS TSSOP−8 SI SOIC−8 Figure 1. Pin Connections (Top View) Table 1. DEVICE OPTIONS Part Number N64S830HAS2 N64S830HAT2 Density Power Supply (V) Speed (MHz) 64 Kb 3.0 20 Package Typical Standby Current Read/Write Operating Current 1 mA 3 mA @ 1 Mhz SOIC TSSOP Table 2. PIN NAMES Pin Name Pin Function CS Chip Select Input SCK Serial Clock Input SI Serial Data Input SO Serial Data Output HOLD Hold Input NC No Connect VCC Power VSS Ground SCK Clock Circuitry HOLD CS Decode Logic 64 Kb SRAM Array SDI Data In Receiver SDO Data Out Buffer Figure 2. Functional Block Diagram http://onsemi.com 2 N64S830HA Table 3. ABSOLUTE MAXIMUM RATINGS Item Symbol Rating Unit Voltage on any pin relative to VSS VIN,OUT –0.3 to VCC + 0.3 V Voltage on VCC Supply Relative to VSS VCC –0.3 to 4.5 V Power Dissipation PD 500 mW TSTG –40 to 125 °C TA −40 to +85 °C TSOLDER 260°C, 10 sec °C Storage Temperature Operating Temperature Soldering Temperature and Time Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. OPERATING CHARACTERISTICS (Over Specified Temperature Range) Item Symbol Test Conditions Min Supply Voltage VCC 3 V Device Input High Voltage Typ (Note 1) Max Unit 2.5 3.6 V VIH 0.7 x VCC VCC + 0.3 V Input Low Voltage VIL –0.3 0.8 V Output High Voltage VOH IOH = −0.4 mA Output Low Voltage VOL IOL = 1 mA 0.2 V VCC – 0.5 V Input Leakage Current ILI CS = VCC, VIN = 0 to VCC 0.5 mA Output Leakage Current ILO CS = VCC, VOUT = 0 to VCC 0.5 mA Read/Write Operating Current ICC1 F = 1 MHz, IOUT = 0 3 mA ICC2 F = 10 MHz, IOUT = 0 6 mA ICC3 F = fCLK MAX, IOUT = 0 10 mA ISB CS = VCC, VIN = VSS or VCC 1 4 mA Min Max Unit Standby Current 1. Typical values are measured at Vcc = Vcc Typ., TA = 25°C and are not 100% tested. Table 5. CAPACITANCE (Note 2) Symbol Test Condition Input Capacitance CIN VIN = 0 V, f = 1 MHz, TA = 25°C 7 pF I/O Capacitance CI/O VIN = 0 V, f = 1 MHz, TA = 25°C 7 pF Item 2. These parameters are verified in device characterization and are not 100% tested Table 6. TIMING TEST CONDITIONS Item Input Pulse Level 0.1 VCC to 0.9 VCC Input Rise and Fall Time 5 ns Input and Output Timing Reference Levels 0.5 VCC Output Load CL = 100 pF Operating Temperature −40 to +85°C http://onsemi.com 3 N64S830HA Table 7. TIMING Item Symbol Min Max Units Clock Frequency fCLK 20 MHz Clock Rise Time tR 2 ms Clock Fall Time tF 2 ms Clock High Time tHI 25 ns Clock Low Time tLO 25 ns Clock Delay Time tCLD 25 ns CS Setup Time tCSS 25 ns CS Hold Time tCSH 50 ns CS Disable Time tCSD 25 ns SCK to CS tSCS 5 ns Data Setup Time tSU 10 ns Data Hold Time tHD 10 ns Output Valid From Clock Low tV Output Hold Time tHO Output Disable Time tDIS 25 0 ns ns 20 ns HOLD Setup Time tHS 10 ns HOLD Hold Time tHH 10 ns HOLD Low to Output High−Z tHZ 10 ns HOLD High to Output Valid tHV http://onsemi.com 4 50 ns N64S830HA tCSD tCLD CS tR tCSH tF tSCS tCSS SCK tSU tHD MSB in SI LSB in High−Z SO Figure 3. Serial Input Timing CS tLO tHI tCSH SCK tV SO tDIS MSB out LSB out Don’t Care SI Figure 4. Serial Output Timing CS tHH tHS tHS SCK tHH SO n+2 n+1 n High−Z tHV n tSU tHZ SI n+2 n+1 n−1 n Don’t Care HOLD Figure 5. Hold Timing http://onsemi.com 5 n n−1 N64S830HA Table 8. CONTROL SIGNAL DESCRIPTIONS Signal Name I/O Description CS Chip Select I A low level selects the device and a high level puts the device in standby mode. If CS is brought high during a program cycle, the cycle will complete and then the device will enter standby mode. When CS is high, SO is in high−Z. CS must be driven low after power−up prior to any sequence being started. SCK Serial Clock I Synchronizes all activities between the memory and controller. All incoming addresses, data and instructions are latched on the rising edge of SCK. Data out is updated on SO after the falling edge of SCK. SI Serial Data In I Receives instructions, addresses and data on the rising edge of SCK. SO Serial Data Out O Data is transferred out after the falling edge of SCK. HOLD Hold I A high level is required for normal operation. Once the device is selected and a serial sequence is started, this input may be taken low to pause serial communication without resetting the serial sequence. The pin must be brought low while SCK is low for immediate use. If SCK is not low, the Hold function will not be invoked until the next SCK high to low transition. The device must remain selected during this sequence. SO is high−Z during the Hold time and SI and SCK are inputs are ignored. To resume operations, HOLD must be pulled high while the SCK pin is low. Lowering the HOLD input at any time will take to SO output to High−Z. Functional Operation Basic Operation The 64 Kb serial SRAM is designed to interface directly with a standard Serial Peripheral Interface (SPI) common on many standard micro−controllers. It may also interface with other non−SPI ports by programming discrete I/O lines to operate the device. The serial SRAM contains an 8−bit instruction register and is accessed via the SI pin. The CS pin must be low and the HOLD pin must be high for the entire operation. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared, the user can assert the HOLD input and place the device into a Hold mode. After releasing the HOLD pin, the operation will resume from the point where it was held. The following table contains the possible instructions and formats. All instructions, addresses and data are transferred MSB first and LSB last. Table 9. INSTRUCTION SET Instruction Instruction Format Description READ 0000 0011 Read data from memory starting at selected address WRITE 0000 0010 Write data to memory starting at selected address RDSR 0000 0101 Read status register WRSR 0000 0001 Write status register READ Operations addresses pointer will be wrapped to the 0 word address within the page and the operation can be continuously looped over the 32 words of the same page. If operating in burst mode, after the initial word of data is shifted out, the data stored at the next memory location can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each word of data is read out. This can be continued for the entire array and when the highest address is reached (1FFFh), the address counter wraps to the address 0000h. This allows the burst read cycle to be continued indefinitely. All READ operations are terminated by pulling CS high. The serial SRAM READ is selected by enabling CS low. First, the 8−bit READ instruction is transmitted to the device followed by the 16−bit address with the 3 MSBs being don’t care. After the READ instruction and addresses are sent, the data stored at that address in memory is shifted out on the SO pin after the output valid time from the clock edge. If operating in page mode, after the initial word of data is shifted out, the data stored at the next memory location on the page can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address on the page after each word of data is read out. This can be continued for the entire page length of 32 words long. At the end of the page, the http://onsemi.com 6 N64S830HA CS 0 1 2 3 4 5 6 7 8 9 10 21 11 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 16−bit address 0 0 1 15 1 14 13 12 2 1 0 Data Out High−Z SO 7 6 5 4 3 2 1 0 24 25 26 27 28 29 30 31 1 0 Figure 6. Word READ Sequence CS 0 1 2 3 4 5 6 7 8 9 10 21 11 22 23 SCK Instruction 0 SI 0 0 0 0 16−bit address 0 1 1 15 14 13 12 2 1 Don’t Care 0 ADDR 1 SO Data Out from ADDR 1 7 High−Z 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 6 5 4 3 2 47 Don’t Care Data Out from ADDR 3 Data Out from ADDR 2 7 6 5 4 3 2 1 0 7 6 5 4 3 2 Data Out from ADDR n 1 0 ... 7 Figure 7. Page and Burst READ Sequence http://onsemi.com 7 6 5 4 3 2 1 0 N64S830HA SI 16−bit address Page address (X) Word address (Y) Data Words: sequential, at the end of the page the address wraps back to the beginning of the page SO Page X Page X Page X Word Y Word Y+1 Word Y+2 Page X Page X Page X Word 31 Word 0 Word 1 Figure 8. Page READ Sequence SI Data Words: sequential, at the end of the page the address wraps to the beginning of the page and continues incrementing up to the starting word address. At that time, the address increments to the next page and the burst continues. 16−bit address Page address (X) Word address (Y) ... SO ... Page X Page X Page X Page X Page X Page X Word Y Word Y+1 Word 31 Word 0 Word 1 Word Y−1 Word Y Page X+1 Page X+1 Word Y+1 Figure 9. Burst READ Sequence WRITE Operations page and the operation can be continuously looped over the 32 words of the same page. The new data will replace data already stored in the memory locations. If operating in burst mode, after the initial word of data is shifted in, additional data words can be written to the next sequential memory locations by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each word of data is read out. This can be continued for the entire array and when the highest address is reached (1FFFh), the address counter wraps to the address 0000h. This allows the burst write cycle to be continued indefinitely. Again, the new data will replace data already stored in the memory locations. All WRITE operations are terminated by pulling CS high. The serial SRAM WRITE is selected by enabling CS low. First, the 8−bit WRITE instruction is transmitted to the device followed by the 16−bit address with the 3 MSBs being don’t care. After the WRITE instruction and addresses are sent, the data to be stored in memory is shifted in on the SI pin. If operating in page mode, after the initial word of data is shifted in, additional data words can be written as long as the address requested is sequential on the same page. Simply write the data on SI pin and continue to provide clock pulses. The internal address pointer is automatically incremented to the next higher address on the page after each word of data is written in. This can be continued for the entire page length of 32 words long. At the end of the page, the addresses pointer will be wrapped to the 0 word address within the CS 0 1 2 3 4 5 6 7 8 9 15 14 10 11 21 22 23 24 25 26 2 1 0 7 6 5 27 28 29 30 31 3 2 1 0 SCK Instruction SI SO 0 0 0 0 0 16−bit address 0 1 0 13 12 ... Data In High−Z Figure 10. Word WRITE Sequence http://onsemi.com 8 4 N64S830HA CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 2 1 0 7 6 5 4 3 2 1 0 SCK Instruction SI 0 0 0 0 16−bit address 0 0 1 0 15 14 13 12 ADDR 1 Data In to ADDR 1 High−Z SO 32 33 34 35 36 37 38 39 40 Data In to ADDR 2 7 6 5 4 3 41 42 43 44 45 46 47 Data In to ADDR 3 2 1 0 7 6 5 4 3 Data In to ADDR n 2 1 0 ... 7 6 5 4 3 2 1 0 High−Z Figure 11. Page and Burst WRITE Sequence Data Words: sequential, at the end of the page the address wraps back to the beginning of the page SI 16−bit address Page address (X) Word address (Y) Page X Page X Word Y Word Y+1 Word Y+2 Page X Page X Page X Page X Word 31 Word 0 Word 1 High−Z SO Figure 12. Page WRITE Sequence ... SI 16−bit address Page address (X) Word address (Y) ... Page X Page X Page X Page X Page X Page X Word Y Word Y+1 Word 31 Word 0 Word 1 Word Y−1 Word Y Page X+1 Page X+1 Word Y+1 Data Words: sequential, at the end of the page the address wraps to the beginning of the page and continues incrementing up to the starting word address. At that time, the address increments to the next page and the burst continues. SO High−Z Figure 13. Burst WRITE Sequence http://onsemi.com 9 N64S830HA WRITE Status Register Instruction (WRSR) This instruction provides the ability to write the status register and select among several operating modes. Several of the register bits must be set to a low ‘0’. The timing sequence to write to the status register is shown below, followed by the organization of the status register. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Status Register Data In Instruction 0 SI 0 0 0 0 0 0 SO 1 7 6 5 4 3 2 High−Z Figure 14. WRITE Status Register Sequence Bit 7 Bit 6 Mode 0 1 0 1 0 = Word Mode (Default) 0 = Page Mode 1 = Burst Mode 1 = Reserved Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved Hold Function Must = 0 0 = Hold (Default) 1 = No Hold Figure 15. Status Register − Data to Write http://onsemi.com 10 N64S830HA READ Status Register Instruction (RDSR) sequence. Bits 0, 6 and 7 contain the data for the functional operation and Bit 1 will read data type ‘1’ for the 64 Kb device. This instruction provides the ability to read the programmable bits of the Status Register. These register bits may be read at any time by performing the following timing CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction 0 SI 0 0 0 1 0 0 1 Status Register Data Out 7 High−Z SO 6 5 4 3 2 1 0 Figure 16. READ Status Register Instruction (RDSR) Bit 7 Bit 6 Mode 0 1 0 1 0 = Word Mode 0 = Page Mode 1 = Burst Mode 1 = Reserved Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 0 0 0 1 = 64 Kb Bit 0 Hold Function 0 = Hold 1 = No Hold Figure 17. Status Register Power−Up State The serial SRAM enters a know state at power−up time. The device is in low−power standby state with CS = 1. A low level on CS is required to enter an active state. http://onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 CASE 751AZ ISSUE B 8 1 SCALE 1:1 NOTES 4&5 0.10 C D 45 5 CHAMFER D h NOTE 6 D A 8 DATE 18 MAY 2015 H 2X 5 0.10 C D E E1 NOTES 4&5 L2 1 0.20 C D 4 8X B NOTE 6 TOP VIEW b 0.25 M L C DETAIL A C A-B D NOTES 3&7 NOTE 7 c 0.10 C e A1 C SIDE VIEW NOTE 8 DIM A A1 A2 b c D E E1 e h L L2 DETAIL A A2 A SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.004 mm IN EXCESS OF MAXIMUM MATERIAL CONDITION. 4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006 mm PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.010 mm PER SIDE. 5. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOT­ TOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTER­ MOST EXTREMES OF THE PLASTIC BODY AT DATUM H. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM H. 7. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO 0.25 FROM THE LEAD TIP. 8. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. SEATING PLANE END VIEW RECOMMENDED SOLDERING FOOTPRINT* MILLIMETERS MIN MAX --1.75 0.10 0.25 1.25 --0.31 0.51 0.10 0.25 4.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 0.25 0.41 0.40 1.27 0.25 BSC GENERIC MARKING DIAGRAM* 8X 0.76 8 8X 1.52 1 7.00 XXXXX A L Y W G 1 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON34918E SOIC−8 XXXXX ALYWX G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G”, may or not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−8 CASE 948S−01 ISSUE C DATE 20 JUN 2008 SCALE 2:1 K REF 8x 0.20 (0.008) T U 0.10 (0.004) S 2X L/2 8 0.20 (0.008) T U T U B −U− 1 J J1 4 V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S ÇÇÇÇ ÉÉÉÉ ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ K1 K A −V− S S 5 L PIN 1 IDENT M SECTION N−N −W− C 0.076 (0.003) D −T− SEATING DETAIL E G PLANE 0.25 (0.010) N M DIM A B C D F G J J1 K K1 L M N F MILLIMETERS MIN MAX 2.90 3.10 4.30 4.50 --1.10 0.05 0.15 0.50 0.70 0.65 BSC 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.114 0.122 0.169 0.177 --0.043 0.002 0.006 0.020 0.028 0.026 BSC 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* XXX YWW AG G DETAIL E XXX A Y WW G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: STATUS: 98AON00697D ON SEMICONDUCTOR STANDARD NEW STANDARD: © Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 − Rev. 0 TSSOP−8 http://onsemi.com 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. Case Outline Number: PAGE 1 OFXXX 2 DOCUMENT NUMBER: 98AON00697D PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION. 18 APR 2000 A ADDED MARKING DIAGRAM INFORMATION. REQ. BY V. BASS. 13 JAN 2006 B CORRECTED MARKING DIAGRAM PIN 1 LOCATION AND MARKING. REQ. BY C. REBELLO. 13 MAR 2006 C REMOVED EXPOSED PAD VIEW AND DIMENSIONS P AND P1. CORRECTED MARKING INFORMATION. REQ. BY C. REBELLO. 20 JUN 2008 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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