NBC12439AFAG

3.3 V/5 V Programmable PLL Synthesized Clock Generator 50 MHz to 800 MHz NBC12439A www.onsemi.com Description The NBC12439A is a general purpose, PLL based synthesized clock source. The VCO will operate over a frequency range of 400 MHz to 800 MHz. The VCO frequency is sent to the N−output divider, where it can be configured to provide division ratios of 1, 2, 4 or 8. The VCO and output frequency can be programmed using the parallel or serial interfaces to the configuration logic. Output frequency steps of 16 MHz, 8 MHz, 4 MHz, or 2 MHz can be achieved using a 16 MHz crystal, depending on the output divider settings. The PLL loop filter is fully integrated and does not require any external components. 1 32 QFN32 MN SUFFIX CASE 488AM MARKING DIAGRAM Features • • • • • • • • • • 1 Best−in−Class Output Jitter Performance, ±20 ps Peak−to−Peak 50 MHz to 800 MHz Programmable Differential PECL Outputs Fully Integrated Phase−Lock−Loop with Internal Loop Filter Parallel Interface for Programming Counter and Output Dividers During Powerup Minimal Frequency Overshoot Serial 3−Wire Programming Interface Crystal Oscillator Inputs 10 MHz to 20 MHz Operating Range: VCC = 3.135 V to 5.25 V Pin and Function Compatible with Motorola MC12439 and MPC9239 Powerdown of PECL Outputs (B16) • • −40°C to 85°C Ambient Operating Temperature • These Devices are Pb−Free and are RoHS Compliant May, 2021 − Rev. 15 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) CMOS and TTL Compatible Control Inputs © Semiconductor Components Industries, LLC, 2009 A WL YY WW G NBC12 439A AWLYYWWG G ORDERING INFORMATION Device NBC12439AMNG 1 Package Shipping QFN−32 (Pb−Free) 74 Units / Tube Publication Order Number: NBC12439/D NBC12439A +3.3 or 5.0 V PWR_DOWN PLL_VCC B2 FREF PHASE DETECTOR POWER DOWN XTAL_SEL +3.3 or 5.0 V VCO FREF_EXT XTAL1 10−20MHz 7−BIT B M COUNTER B2 VCC 400−800 MHz OSC FOUT BN (1, 2, 4, 8) FOUT TEST XTAL2 LATCH LATCH OE S_LOAD LATCH P_LOAD 0 S_DATA 1 0 1 2−BIT SR 7−BIT SR 3−BIT SR S_CLOCK 7 2 M[6:0] N[1:0] Figure 1. Block Diagram Table 1. OUTPUT DIVERSION Table 2. XTAL_SEL AND OE N [1:0] Output Division Input 0 1 00 01 10 11 2 4 8 1 PWR_DOWN XTAL_SEL OE* FOUT FREF_EXT Outputs Disabled FOUT B 16 XTAL Outputs Enabled *When disabled, FOUT goes LOW, FOUT goes HIGH. www.onsemi.com 2 VCC FOUT FOUT GND VCC VCC TEST GND NBC12439A 32 31 30 29 28 27 26 25 NC PLL_VCC 5 20 XTAL_SEL PWR_DOWN 6 19 M[6] FREF_EXT 7 18 M[5] XTAL1 8 17 M[4] 9 10 11 12 13 14 15 16 N/C PLL_VCC 21 M[3] N[0] 4 M[2] S_LOAD 22 M[1] N[1] 3 M[0] S_DATA 23 P_LOAD N/C 2 OE 24 XTAL2 S_CLOCK 1 Exposed Pad (EP) Figure 2. 32−Lead QFN (Top View) The following gives a brief description of the functionality of the NBC12349A Inputs and Outputs. Unless explicitly stated, all inputs are CMOS/TTL compatible with either pull−up or pulldown resistors. The PECL outputs are capable of driving two series terminated 50 W transmission lines on the incident edge. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 3. PIN FUNCTION DESCRIPTION Pin Name Function Description INPUTS Crystal Inputs These pins form an oscillator when connected to an external series−resonant crystal. S_LOAD* CMOS/TTL Serial Latch Input (Internal Pulldown Resistor) This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this signal is HIGH; thus, the data must be stable on the HIGH−to−LOW transition of S_LOAD for proper operation. S_DATA* CMOS/TTL Serial Data Input (Internal Pulldown Resistor) This pin acts as the data input to the serial configuration shift registers. S_CLOCK* CMOS/TTL Serial Clock Input (Internal Pulldown Resistor) This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge. P_LOAD** CMOS/TTL Parallel Latch Input (Internal Pullup Resistor) This pin loads the configuration latches with the contents of the parallel inputs. The latches will be transparent when this signal is LOW; therefore, the parallel data must be stable on the LOW−to−HIGH transition of P_LOAD for proper operation. M[6:0]** CMOS/TTL PLL Loop Divider Inputs (Internal Pullup Resistor) These pins are used to configure the PLL loop divider. They are sampled on the LOW−to−HIGH transition of P_LOAD. M[6] is the MSB, M[0] is the LSB. N[1:0]** CMOS/TTL Output Divider Inputs (Internal Pullup Resistor) These pins are used to configure the output divider modulus. They are sampled on the LOW−to−HIGH transition of P_LOAD. OE** CMOS/TTL Output Enable Input (Internal Pullup Resistor) Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the FOUT output. When Disabled, FOUT goes LOW and FOUT. FREF_EXT* CMOS/TTL Input (Internal Pulldown Resistor) This pin can be used as the PLL Reference XTAL_SEL** CMOS/TTL Input (Internal Pullup Resistor) This pin selects between the crystal and the FREF_EXT source for the PLL reference signal. A HIGH selects the crystal input. PWR_DOWN CMOS/TTL Input (Internal Pulldown Resistor) PWR_DOWN forces the FOUT outputs to synchronously reduce frequency by a factor of 16. XTAL1, XTAL2 www.onsemi.com 3 NBC12439A ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 3. PIN FUNCTION DESCRIPTION (continued) Pin Name Function Description OUTPUTS FOUT, FOUT TEST PECL Differential Outputs These differential, positive−referenced ECL signals (PECL) are the outputs of the synthesizer. CMOS/TTL Output The function of this output is determined by the serial configuration bits T[2:0]. Positive Supply for the Logic The positive supply for the internal logic and output buffer of the chip, and is connected to +3.3 V or +5.0 V. Positive Supply for the PLL This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V. Negative Power Supply These pins are the negative supply for the chip and are normally all connected to ground. Exposed Pad for QFN−32 only The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to GND. POWER VCC PLL_VCC GND − * When left Open, these inputs will default LOW. ** When left Open, these inputs will default HIGH. Table 4. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 37.5 kW ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 150 V > 1 kV Moisture Sensitivity (Note 1) Pb−Free Pkg QFN Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 2269 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 5. MAXIMUM RATINGS Symbol VCC Parameter Condition 1 Condition 2 Rating Unit 6 V 6 V 50 100 mA mA Positive Supply GND = 0 V VI Input Voltage GND = 0 V Iout Output Current Continuous Surge TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm QFN−32 QFN−32 31 27 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P QFN−32 12 °C/W Tsol Wave Solder (Pb−Free)