NBC12439AMNR4G

NBC12439, NBC12439A 3.3V/5V Programmable PLL Synthesized Clock Generator 50 MHz to 800 MHz Description http://onsemi.com MARKING DIAGRAMS 1 28 The NBC12439 and NBC12439A are general purpose, PLL based synthesized clock sources. The VCO will operate over a frequency range of 400 MHz to 800 MHz. The VCO frequency is sent to the N-output divider, where it can be configured to provide division ratios of 1, 2, 4 or 8. The VCO and output frequency can be programmed using the parallel or serial interfaces to the configuration logic. Output frequency steps of 16 MHz, 8 MHz, 4 MHz, or 2 MHz can be achieved using a 16 MHz crystal, depending on the output divider settings. The PLL loop filter is fully integrated and does not require any external components. Features NBC12439xG PLCC-28 FN SUFFIX CASE 776 AWLYYWW • • • • • • • • • Best- -Class Output Jitter Performance, ±20 ps Peak- -Peak -in-to50 MHz to 800 MHz Programmable Differential PECL Outputs Fully Integrated Phase-Lock-Loop with Internal Loop Filter LQFP-32 FA SUFFIX CASE 873A NBC12 439x AWLYYWWG Parallel Interface for Programming Counter and Output Dividers During Powerup • Minimal Frequency Overshoot Serial 3-Wire Programming Interface Crystal Oscillator Inputs 10 MHz to 20 MHz Operating Range: VCC = 3.135 V to 5.25 V CMOS and TTL Compatible Control Inputs 1 1 32 QFN32 MN SUFFIX CASE 488AM x A WL, L YY, Y WW, W G or G NBC12 439x AWLYYWWG G Pin and Function Compatible with Motorola MC12439 and MPC9239 • Powerdown of PECL Outputs (÷16) • 0°C to 70°C Ambient Operating Temperature (NBC12439) • --40°C to 85°C Ambient Operating Temperature (NBC12439A) • Pb--Free Packages are Available = Blank or A = Assembly Location = Wafer Lot = Year = Work Week = Pb--Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet. © Semiconductor Components Industries, LLC, 2007 February, 2007 - Rev. 10 - 1 Publication Order Number: NBC12439/D NBC12439, NBC12439A PWR_DOWN 2 FREF +3.3 or 5.0 V 1 PLL_VCC ÷2 XTAL_SEL FREF_EXT 15 3 4 10--20MHz 5 OE S_LOAD P_LOAD 6 28 7 PHASE DETECTOR VCO POWER DOWN VCC ÷N (1, 2, 4, 8) 21, 25 24 23 +3.3 or 5.0 V XTAL1 OSC XTAL2 7--BIT ÷ M COUNTER ÷2 FOUT FOUT 400--800 MHz 20 LATCH LATCH TEST LATCH 0 1 0 2--BIT SR 1 3--BIT SR S_DATA S_CLOCK 27 26 7--BIT SR 8 14 7 M[6:0] 17, 18 2 N[1:0] 22, 19 Figure 1. Block Diagram (28-Lead PLCC) Table 1. Output Division N [1:0] 00 01 10 11 Output Division 2 4 8 1 Table 2. XTAL_SEL And OE Input PWR_DOWN XTAL_SEL OE 0 FOUT FREF_EXT Outputs Disabled 1 FOUT ÷ 16 XTAL Outputs Enabled http://onsemi.com 2 NBC12439, NBC12439A FOUT FOUT TEST 20 GND 25 24 23 22 21 S_CLOCK S_DATA S_LOAD PLL_VCC PWR_DOWN FREF_EXT XTAL1 GND 19 18 17 16 15 14 13 12 VCC VCC 26 27 28 1 2 3 4 5 6 7 8 9 10 11 N[1] N[0] NC XTAL_SEL M[6] M[5] M[4] P_LOAD XTAL2 M[0] M[1] M[2] M[3] OE FOUT FOUT TEST 26 GND Figure 2. 28-Lead PLCC (Top View) 32 31 30 29 28 27 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 GND VCC VCC VCC S_CLOCK S_DATA S_LOAD PLL_VCC PLL_VCC PWR_DOWN FREF_EXT XTAL1 1 2 3 4 5 6 7 8 N/C N[1] N[0] NC XTAL_SEL M[6] M[5] M[4] FOUT FOUT XTAL2 M[0] M[1] M[2] TEST 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 S_CLOCK S_DATA S_LOAD PLL_VCC PLL_VCC PWR_DOWN FREF_EXT XTAL1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N/C N[1] N[0] NC XTAL_SEL M[6] M[5] M[4] Figure 3. 32-Lead LQFP (Top View) XTAL2 M[0] M[1] M[2] P_LOAD M[3] N/C OE Exposed Pad (EP) Figure 4. 32-Lead QFN (Top View) http://onsemi.com 3 P_LOAD GND GND VCC VCC VCC M[3] N/C OE NBC12439, NBC12439A The following gives a brief description of the functionality of the NBC12439 and NBC12349A Inputs and Outputs. Unless explicitly stated, all inputs are CMOS/TTL compatible with either pull- or pulldown resistors. The PECL outputs are capable -up of driving two series terminated 50 Ω transmission lines on the incident edge. Table 3. PIN FUNCTION DESCRIPTION Pin Name INPUTS XTAL1, XTAL2 S_LOAD* Crystal Inputs CMOS/TTL Serial Latch Input (Internal Pulldown Resistor) CMOS/TTL Serial Data Input (Internal Pulldown Resistor) CMOS/TTL Serial Clock Input (Internal Pulldown Resistor) CMOS/TTL Parallel Latch Input (Internal Pullup Resistor) These pins form an oscillator when connected to an external series--resonant crystal. This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this signal is HIGH; thus, the data must be stable on the HIGH--to--LOW transition of S_LOAD for proper operation. This pin acts as the data input to the serial configuration shift registers. This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge. This pin loads the configuration latches with the contents of the parallel inputs .The latches will be transparent when this signal is LOW; therefore, the parallel data must be stable on the LOW--to--HIGH transition of P_LOAD for proper operation. These pins are used to configure the PLL loop divider. They are sampled on the LOW--to--HIGH transition of P_LOAD. M[6] is the MSB, M[0] is the LSB. These pins are used to configure the output divider modulus. They are sampled on the LOW--to--HIGH transition of P_LOAD. Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the FOUT output. This pin can be used as the PLL Reference This pin selects between the crystal and the FREF_EXT source for the PLL reference signal. A HIGH selects the crystal input. PWR_DOWN forces the FOUT outputs to synchronously reduce frequency by a factor of 16. Function Description S_DATA* S_CLOCK* P_LOAD** M[6:0]** N[1:0]** OE** FREF_EXT* XTAL_SEL** PWR_DOWN OUTPUTS FOUT, FOUT TEST POWER VCC PLL_VCC GND -- CMOS/TTL PLL Loop Divider Inputs (Internal Pullup Resistor) CMOS/TTL Output Divider Inputs (Internal Pullup Resistor) CMOS/TTL Output Enable Input (Internal Pullup Resistor) CMOS/TTL Input (Internal Pulldown Resistor) CMOS/TTL Input (Internal Pullup Resistor) CMOS/TTL Input (Internal Pulldown Resistor) PECL Differential Outputs CMOS/TTL Output Positive Supply for the Logic Positive Supply for the PLL Negative Power Supply Exposed Pad for QFN--32 only These differential, positive--referenced ECL signals (PECL) are the outputs of the synthesizer. The function of this output is determined by the serial configuration bits T[2:0]. The positive supply for the internal logic and output buffer of the chip, and is connected to +3.3 V or +5.0 V. This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V. These pins are the negative supply for the chip and are normally all connected to ground. The Exposed Pad (EP) on the QFN--32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat--sinking conduit. The pad is electrically connected to GND. * When left Open, these inputs will default LOW. ** When left Open, these inputs will default HIGH. http://onsemi.com 4 NBC12439, NBC12439A Table 4. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg PLCC LQFP QFN Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 Level 1 Level 2 Level 1 Value 75 kΩ 37.5 kΩ > 2 kV > 150 V > 1 kV Pb--Free Pkg Level 1 Level 2 Level 1 Moisture Sensitivity (Note 1) UL 94 V--0 @ 0.125 in 2269 Table 5. MAXIMUM RATINGS Symbol VCC VI Iout TA Positive Supply Input Voltage Output Current Operating Temperature Range Parameter Condition 1 GND = 0 V GND = 0 V Continuous Surge NB12439 NB12439A VI ± VCC Condition 2 Rating 6 6 50 100 0 to 70 --40 to +85 --65 to +150 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm 2S2P