NBSG11BAEVB

NBSG11 2.5V/3.3V SiGe 1:2 Differential Clock Driver with RSECL* Outputs *Reduced Swing ECL http://onsemi.com Description MARKING DIAGRAMS* The NBSG11 is a 1−to−2 differential fanout buffer, optimized for low skew and Ultra−Low JITTER. Inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), CML, LVCMOS, LVTTL, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV. Features SG 11 ALYW FCBGA−16 BA SUFFIX CASE 489 16 1 QFN−16 MN SUFFIX CASE 485G • • • • • A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. © Semiconductor Components Industries, LLC, 2006 1 July, 2006 − Rev. 8 Publication Order Number: NBSG11/D ÇÇ ÇÇ • • • • • Maximum Input Clock Frequency up to 12 GHz Typical Maximum Input Data Rate up to 12 Gb/s Typical 30 ps Typical Rise and Fall Times 125 ps Typical Propagation Delay RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V RSECL Output Level (400 mV Peak−to−Peak Output), Differential Output Only 50 W Internal Input Termination Resistors Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices Pb−Free Packages are Available SG11 ALYWG G NBSG11 1 A VTCLK 2 NC 3 NC 4 Q1 VEE 16 VTCLK NC 15 NC 14 VCC 13 Exposed Pad (EP) 1 2 NBSG11 3 4 12 11 10 9 Q0 Q0 Q1 Q1 B CLK VEE VCC Q1 CLK Q0 C CLK VEE VCC CLK VTCLK D VTCLK NC NC Q0 5 VEE 6 NC 7 NC 8 VCC Figure 1. BGA−16 Pinout (Top View) Figure 2. QFN−16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin BGA D1 C1 QFN 1 2 Name VTCLK CLK I/O − ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input − − − − RSECL Output RSECL Output RSECL Output RSECL Output − Description Internal 50 W Termination Pin. See Table 2. Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to VCC. B1 3 CLK Noninverted Differential Input. Internal 75 kW to VEE. A1 B2,C2 A2,A3,D2, D3 B3,C3 A4 B4 C4 D4 N/A 4 5,16 6,7,14,15 8,13 9 10 11 12 − VTCLK VEE NC VCC Q1 Q1 Q0 Q0 EP Internal 50 W Termination Pin. See Table 2. Negative Supply Voltage No Connect Positive Supply Voltage Inverted Differential Output 1. Typically Terminated with 50 W to VTT = VCC − 2.0 V. Noninverted Differential Output 1. Typically Terminated with 50 W to VTT = VCC − 2.0 V. Inverted Differential output 0. Typically Terminated with 50 W to VTT = VCC − 2.0 V. Noninverted Differential Output 0. Typically Terminated with 50 W to VTT = VCC − 2 V. Exposed Pad (Note 2) 1. The NC pins are electrically connected to the die and must be left open. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat−sinking conduit. 3. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self−oscillation. http://onsemi.com 2 NBSG11 VCC VTCLK 50 W CLK CLK 50 W VTCLK VEE 75 KW 75 KW Q0 Q0 36.5 KW Q1 Q1 Figure 3. Logic Diagram Table 2. INTERFACING OPTIONS INTERFACING OPTIONS CML LVDS AC−COUPLED RSECL, PECL, NECL LVTTL, LVCMOS CONNECTIONS Connect VTCLK and VTCLK to VCC Connect VTCLK and VTCLK together Bias VTCLK and VTCLK Inputs within (VIHCMR) Common Mode Range Standard ECL Termination Techniques An external voltage should be be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL and VCC/2 for LVCMOS inputs. Table 3. ATTRIBUTES Characteristics Internal Input Pulldown Resistor (CLK, CLK) Internal Input Pullup Resistor (CLK) ESD Protection Moisture Sensitivity (Note 4) FCBGA−16 QFN−16 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 4. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 Human Body Model Machine Model Pb Pkg Level 3 Level 1 Value 75 kW 36.5 kW > 2 kV > 100 V Pb−Free Pkg N/A Level 1 UL 94 V−0 @ 0.125 in 125 http://onsemi.com 3 NBSG11 Table 4. MAXIMUM RATINGS Symbol VCC VEE VI VINPP Iout TA Tstg qJA Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 5) 0 lfpm 500 lfpm 0 lfpm 500 lfpm 1S2P (Note 5) 2S2P (Note 6) 16 FCBGA 16 FCBGA 16 QFN 16 QFN 16 FCBGA 16 QFN |D − D| Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VCC − VEE w VCC − VEE < Continuous Surge 16 FCBGA 16 QFN 2.8 V 2.8 V VI ≤ VCC VI ≥ VEE Condition 2 Rating 3.6 −3.6 3.6 −3.6 2.8 |VCC − VEE| 25 50 −40 to +70 −40 to +85 −65 to +150 108 86 41.6 35.2 5.0 4.0 225 225 Unit V V V V V V mA mA °C °C °C/W °C/W °C/W °C/W °C/W °C/W °C qJC Tsol Thermal Resistance (Junction−to−Case) Wave Solder Pb Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 5. JEDEC standard multilayer board − 1S2P (1 signal, 2 power). 6. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 4 NBSG11 Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 7) −40°C Symbol IEE VOH VOUTPP VIH Characteristic Negative Power Supply Current Output HIGH Voltage (Note 8) Output Amplitude Voltage Input HIGH Voltage (Single−Ended) (Note 10) Input LOW Voltage (Single−Ended) (Note 11) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) Internal Input Termination Resistor Input HIGH Current (@ VIH, VIHMAX) Input LOW Current (@ VIL, VILMIN) Min 45 1450 350 VCC− 1435 mV VIH− 2.5 V 1.2 Typ 60 1530 410 VCC− 1000 mV* VCC− 1400 mV* Max 75 1575 525 VCC Min 45 1525 350 VCC− 1435 mV VIH− 2.5 V 1.2 25°C Typ 60 1565 410 VCC− 1000 mV* VCC− 1400 mV* Max 75 1600 525 VCC 70°C(BGA)/85°C(QFN)** Min 45 1550 350 VCC− 1435 mV VIH− 2.5 V 1.2 Typ 60 1590 410 VCC− 1000 mV* VCC− 1400 mV* Max 75 1625 525 VCC Unit mA mV mV V VIL VIH− 150 mV 2.5 VIH− 150 mV 2.5 VIH− 150 mV 2.5 V VIHCMR V RTIN IIH IIL 45 50 80 25 55 150 100 45 50 80 25 55 150 100 45 50 80 25 55 150 100 W mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *Typicals used for testing purposes. **The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum temperature specification of 85°C. 7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.965 V. 8. All loading with 50 W to VCC − 2.0 V. VOH/VOL measured at VIH/VIL. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10. VIH cannot exceed VCC. 11. VIL always ≥ VEE. http://onsemi.com 5 NBSG11 Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 12) −40°C Symbol IEE VOH VOUTPP VIH Characteristic Negative Power Supply Current Output HIGH Voltage (Note 13) Output Amplitude Voltage Input HIGH Voltage (Single−Ended) (Note 15) Input LOW Voltage (Single−Ended) (Note 16) Input HIGH Voltage Common Mode Range (Note 14) (Differential Configuration) Internal Input Termination Resistor Input HIGH Current (@ VIH, VIHMAX) Input LOW Current (@ VIL, VILMIN) Min 45 2250 350 VCC− 1435 mV VIH− 2.5 V 1.2 Typ 60 2330 410 VCC− 1000 mV* VCC− 1400 mV* Max 75 2375 525 VCC Min 45 2325 350 VCC− 1435 mV VIH− 2.5 V 1.2 25°C Typ 60 2365 410 VCC− 1000 mV* VCC− 1400 mV* Max 75 2400 525 VCC 70°C(BGA)/85°C(QFN)** Min 45 2350 350 VCC− 1435 mV VIH− 2.5 V 1.2 Typ 60 2390 410 VCC− 1000 mV* VCC− 1400 mV* Max 75 2425 525 VCC Unit mA mV mV V VIL VIH− 150 mV 3.3 VIH− 150 mV 3.3 VIH− 150 mV 3.3 V VIHCMR V RTIN IIH IIL 45 50 80 25 55 150 100 45 50 80 25 55 150 100 45 50 80 25 55 150 100 W mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.165 V. 13. All loading with 50 W to VCC − 2.0 V. VOH/VOL measured at VIH/VIL. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 15. VIH cannot exceed VCC. 16. VIL always ≥ VEE. *Typicals used for testing purposes. **The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum temperature specification of 85°C. http://onsemi.com 6 NBSG11 Table 7. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT VCC = 0 V; VEE = −3.465 V to −2.375 V (Note 17) −40°C Symbol IEE VOH VOUTPP VIH Characteristic Negative Power Supply Current Output HIGH Voltage (Note 18) Output Amplitude Voltage Input HIGH Voltage (Single−Ended) (Note 20) Input LOW Voltage (Single−Ended) (Note 21) Min 45 −1050 350 VCC− 1435 mV VIH− 2.5 V Typ 60 −970 410 VCC− 1000 mV* VCC− 1400 mV* Max 75 −925 525 VCC Min 45 −975 350 VCC− 1435 mV VIH− 2.5 V 25°C Typ 60 −935 410 VCC− 1000 mV* VCC− 1400 mV* Max 75 −900 525 VCC 70°C(BGA)/85°C(QFN)** Min 45 −950 350 VCC− 1435 mV VIH− 2.5 V Typ 60 −910 410 VCC− 1000 mV* VCC− 1400 mV* Max 75 −875 525 VCC Unit mA mV mV V VIL VIH− 150 mV 0.0 55 150 100 VIH− 150 mV 0.0 55 150 100 VIH− 150 mV 0.0 55 150 100 V VIHCMR RTIN IIH IIL Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 19) Internal Input Termination Resistor Input HIGH Current (@ VIH, VIHMAX) Input LOW Current (@ VIL, VILMIN) VEE+1.2 45 50 80 25 VEE+1.2 45 50 80 25 VEE+1.2 45 50 80 25 V W mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17. Input and output parameters vary 1:1 with VCC. 18. All loading with 50 W to VCC − 2.0 V. VOH/VOL measured at VIH/VIL. 19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 20. VIH cannot exceed VCC. 21. VIL always ≥ VEE. *Typicals used for testing purposes. **The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum temperature specification of 85°C. http://onsemi.com 7 NBSG11 Table 8. AC CHARACTERISTICS for FCBGA−16 VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V −40°C Symbol fmax tPLH, tPHL tSKEW Characteristic Maximum Frequency (See Figure 4. Fmax/JITTER) (Note 22) Propagation Delay to Output Differential Duty Cycle Skew (Note 23) Within−Device Skew (Note 24) Device−to−Device Skew (Note 25) RMS Random Clock Jitter fin < 10 GHz Peak−to−Peak Data Dependent Jitter fin < 10 Gb/s VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 26) Output Rise/Fall Times (20% − 80%) @ 1 GHz Q, Q 75 20 30 0.2 TBD 2600 55 75 20 30 1 0.2 TBD 2600 55 75 20 30 1 0.2 TBD 2600 55 mV ps 1 Min 10.709 90 Typ 12 125 3 6 25 160 15 15 50 Max Min 10.709 90 25°C Typ 12 125 3 6 25 160 15 15 50 Max Min 10.709 90 70°C Typ 12 125 3 6 25 160 15 15 50 Max Unit GHz ps ps tJITTER ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 22. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. For minimum fmax value of 10.709 GHz, output amplitude is approximately 200 mV (as shown in Figure 4, where output P−P spec is shown as a minimum/guarantee of around 150 mV). Input edge rates 40 ps (20% − 80%). 23. See Figure 5. tSKEW = |tPLH − tPHL| for a nominal 50% Differential Clock Input Waveform. 24. Within−Device skew is defined as identical transitions on similar paths through a device. 25. Device−to−device skew for identical transitions at identical VCC levels. 26. VINPP (MAX) cannot exceed VCC − VEE. http://onsemi.com 8 NBSG11 Table 9. AC CHARACTERISTICS for QFN−16 VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V −40°C Symbol fmax tPLH, tPHL tSKEW Characteristic Maximum Frequency (See Figure 4. Fmax/JITTER) (Note 27) Propagation Delay to Output Differential Duty Cycle Skew (Note 28) Within−Device Skew (Note 29) Device−to−Device Skew (Note 30) RMS Random Clock Jitter fin < 10 GHz Peak−to−Peak Data Dependent Jitter fin < 10 Gb/s VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 31) Output Rise/Fall Times (20% − 80%) @ 1 GHz Q, Q 75 15 30 0.2 TBD 2600 55 75 20 30 1 0.2 TBD 2600 55 75 20 30 1 0.2 TBD 2600 55 mV ps 1 Min 10.5 90 Typ 12 125 3 6 25 160 15 15 50 Max Min 10.5 90 25°C Typ 12 125 3 6 25 160 15 15 50 Max Min 10.5 90 85°C Typ 12 125 3 6 25 160 15 15 50 Max Unit GHz ps ps tJITTER ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 27. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC−2.0 V. For minimum fmax value of 10.5 GHz, output amplitude is approximately 200 mV (as shown in Figure 4, where output P−P spec is shown as a minimum/guarantee of around 150 mV). Input edge rates 40 ps (20% − 80%). 28. See Figure 5. tSKEW = |tPLH − tPHL| for a nominal 50% Differential Clock Input Waveform. 29. Within−Device skew is defined as identical transitions on similar paths through a device. 30. Device−to−device skew for identical transitions at identical VCC levels. 31. VINPP (MAX) cannot exceed VCC − VEE. 600 9.5 OUTPUT VOLTAGE AMPLITUDE (mV) 500 OUTPUT AMP. 400 OUTPUT P−P SPEC 8.5 7.5 6.5 5.5 4.5 3.5 2.5 1.5 0.5 −0.5 JITTERout ps (RMS) 300 200 100 ÒÒÒ Ú Õ Ò ÚŠ ÒÒÒÚŠŠÕÒÔÔÓÑÖÖÔÓÓÑ Ú ŠŠŠ Õ Ô Ó Ñ Ö Ô Ó Ñ ÕÒ Ô ÚÚŠŠÕÒÔÔÓÑÖÖÔÓÓÑ Ñ ÓÑ Ö Ñ Š ÕÒÒÔÔÓÑÖÖÔÓÓÑ ÔÑÓÑÑ ÔÓ Ñ ŠŠŠ Õ Ò ÔÔ Ñ Ö Ô Ó Ñ ÕÒ Ô ÓÑ Ö ÒÒÔÔÓÑÖÖÔÓÓÑ Ô ÓÓ Ö Ô Ó Ñ Ñ ÔÔÔÓÑÖÖÔÓÓÑ Ó ÑÑ Ô Ó Ñ Ö ÔÓ Ñ ÓÓÑÖÖÔÓÓÑ ÑÖÑÔÓ Ñ ÑÑ ÑÑÖÖÔÑÓÑ ÖÖÖÔÑÑÑ ÑÑÔÑÓÓ ÑÑÓÑ ÓÑ RMS JITTER 0 1 2 3 4 5 6 7 8 9 INPUT FREQUENCY (GHz) 10 11 12 Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical) http://onsemi.com 9 NBSG11 CLK VINPP = VIH(CLK) − VIL(CLK) CLK Q VOUTPP = VOH(Q) − VOL(Q) Q tPLH tPHL Figure 5. AC Reference Measurement Q Driver Device Q Zo = 50 W D Receiver Device Zo = 50 W 50 W 50 W D VTT VTT = VCC − 2.0 V Figure 6. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device NBSG11BA NBSG11BAR2 NBSG11MN NBSG11MNG NBSG11MNR2 NBSG11MNR2G Package FCBGA−16 FCBGA−16 QFN−16 QFN−16 (Pb−Free) QFN−16 QFN−16 (Pb−Free) Shipping† 100 Units / Tray (Contact Sales Representative) 100 / Tape & Reel 123 Units / Rail 123 Units / Rail 3000 / Tape & Reel 3000 / Tape & Reel Board NBSG11BAEVB Description NBSG11BA Evaluation Board †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 10 NBSG11 PACKAGE DIMENSIONS LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA FCBGA−16 BA SUFFIX PLASTIC 4X4 (mm) BGA FLIP CHIP PACKAGE CASE 489−01 ISSUE O −X− D M NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. DIM A A1 A2 b D E e S MILLIMETERS MIN MAX 1.40 MAX 0.25 0.35 1.20 REF 0.30 0.50 4.00 BSC 4.00 BSC 1.00 BSC 0.50 BSC −Y− K E M 0.20 3X FEDUCIAL FOR PIN A1 IDENTIFICATION IN THIS AREA A B C D e 4 3 2 1 3 16 X b 0.15 0.08 M M S VIEW M−M ZXY Z 5 0.15 Z A A2 −Z− A1 16 X 4 DETAIL K 0.10 Z ROTATED 90 _ CLOCKWISE http://onsemi.com 11 NBSG11 PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 D A B PIN 1 LOCATION 0.15 C 0.15 C 0.10 C TOP VIEW 16 X 0.08 C SIDE VIEW A1 C 16X L 5 NOTE 5 4 16X K 1 12 16X b BOTTOM VIEW 0.50 0.02 0.30 0.012 SCALE 10:1 mm inches 0.10 C A B 0.05 C NOTE 3 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative ÇÇ ÇÇ (A3) D2 e 8 9 16 13 E A SEATING PLANE DIM A A1 A3 b D D2 E E2 e K L SOLDERING FOOTPRINT* 3.25 0.128 0.30 0.012 EXPOSED PAD 0.575 0.022 EXPOSED PAD E2 e 3.25 0.128 1.50 0.059 *For additional information on our Pb−Free strategy and solder details, please download the ON Semiconductor Soldering a Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 12 NBSG11/D