NBSG14
2.5V/3.3V SiGe Differential
1:4 Clock/Data Driver with
RSECL* Outputs
*Reduced Swing ECL
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Description
The NBSG14 is a 1−to−4 clock/data distribution chip, optimized for
ultra−low skew and jitter.
Inputs incorporate internal 50 termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS,
CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV.
All outputs loaded with 50 to VCC − 1.5 V for BGA package and
VCC − 2 V for QFN package.
MARKING DIAGRAMS*
FCBGA−16
BA SUFFIX
CASE 489
•
•
•
•
•
ÇÇ
ÇÇ
ÇÇ
16
Features
•
•
•
•
•
SG
14
ALYWG
G
Maximum Input Clock Frequency up to 12 GHz Typical
Maximum Input Data Rate up to 12 Gb/s Typical
30 ps Typical Rise and Fall Times
125 ps Typical Propagation Delay
RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V
with VEE = 0 V
RSNECL Output with RSNECL or NECL Inputs with
Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
RSECL Output Level (400 mV Peak−to−Peak Output),
Differential Output
50 Internal Input Termination Resistors
Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
Pb−Free Packages are Available
1
1
QFN−16
MN SUFFIX
CASE 485G
A
L
Y
W
G
SG
14
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
January, 2011 − Rev. 16
1
Publication Order Number:
NBSG14/D
NBSG14
1
A
2
VTCLK
B
CLK
Q3
VEE
3
4
Q3
VEE
Q0
Q0
VCC
16
15
14
13
Q2
VCC
Q2
VTCLK
1
CLK
2
12 Q1
11 Q1
NBSG14
C
CLK
D
VEE
Q0
VTCLK
Exposed Pad (EP)
VCC
Q1
Q0
CLK
3
10 Q2
VTCLK
4
9
Q1
Figure 1. BGA−16 Pinout (Top View)
5
6
7
8
VEE
Q3
Q3
VCC
Q2
Figure 2. QFN−16 Pinout (Top View)
Table 1. Pin Description
Pin
BGA
QFN
Name
I/O
D1
1
VTCLK
−
C1
2
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input. Internal 75 k to VEE and 36.5 k to VCC.
B1
3
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input. Internal 75 k to VEE.
A1
4
VTCLK
−
Internal 50 Termination Pin. See Table 2.
B2,C2
5,16
VEE
−
Negative Supply Voltage. All VEE Pins must be Externally Connected to Power
Supply to Guarantee Proper Operation.
A2*
6
Q3
RSECL Output
Inverted Differential Output 3. Typically Terminated with 50 to VTT = VCC − 2 V*
A3*
7
Q3
RSECL Output
Noninverted Differential Output 3. Typically Terminated with 50 to
VTT = VCC − 2 V*
B3,C3
8,13
VCC
−
A4*
9
Q2
RSECL Output
Inverted Differential Output 2. Typically Terminated with 50 to VTT = VCC − 2 V*
B4*
10
Q2
RSECL Output
Noninverted Differential Output 2. Typically Terminated with 50 to
VTT = VCC − 2 V*
C4*
11
Q1
RSECL Output
Inverted Differential Output 1. Typically Terminated with 50 to VTT = VCC − 2 V*
D4*
12
Q1
RSECL Output
Noninverted Differential Output 1. Typically Terminated with 50 to
VTT = VCC − 2 V*
D3*
14
Q0
RSECL Output
Inverted Differential Output 0. Typically Terminated with 50 to VTT = VCC − 2 V*
D2*
15
Q0
RSECL Output
Noninverted Differential Output 0. Typically Terminated with 50 to
VTT = VCC − 2 V*
N/A
−
EP
−
Description
Internal 50 Termination pin. See Table 2.
Positive Supply Voltage. All VCC Pins must be Externally Connected to Power
Supply to Guarantee Proper Operation.
The Exposed Pad (EP) and the QFN−16 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is not electrically connected to the die
but may be electrically and thermally connected to VEE on the PC board.
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, if no
signal is applied then the device will be susceptible to self−oscillation.
*Devices in BGA package typically terminated with 50 to VTT = VCC − 1.5 V.
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NBSG14
VCC
Q3
Q3
VTCLK
36.5 K
Q2
50
Q2
CLK
CLK
50
75 K
75 K
Q1
VTCLK
Q1
Q0
VEE
Q0
Figure 3. Logic Diagram
Table 2. INTERFACING OPTIONS
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTCLK and VTCLK to VCC
LVDS
Connect VTCLK and VTCLK Together
AC−COUPLED
Bias VTCLK and VTCLK Inputs within
Common Mode Range (VIHCMR)
RSECL, PECL, NECL
Standard ECL Termination Techniques
LVTTL, LVCMOS
An External Voltage (VTHR) should be Applied to
the Unused Differential Input. Nominal VTHR is
1.5 V for LVTTL and VCC/2 for LVCMOS Inputs.
This Voltage must be within the VTHR
Specification.
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor (CLK, CLK)
75 k
Internal Input Pullup Resistor (CLK)
ESD Protection
36.5 k
Human Body Model
Machine Model
Moisture Sensitivity (Note 1)
FCBGA−16
QFN−16
Flammability Rating
Value
Oxygen Index: 28 to 34
Transistor Count
> 2 kV
> 100 V
Pb Pkg
Pb−Free Pkg
Level 3
Level 1
Level 3
Level 1
UL 94 V−0 @ 0.125 in
158
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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NBSG14
Table 4. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
Positive Power Supply
Parameter
VEE = 0 V
Condition 1
3.6
V
VEE
Negative Power Supply
VCC = 0 V
−3.6
V
VI
Positive Input
Negative Input
VEE = 0 V
VCC = 0 V
3.6
−3.6
V
V
VINPP
Differential Input Voltage |CLK−CLK|
VCC − VEE w 2.8 V
VCC − VEE < 2.8 V
2.8
|VCC−VEE|
V
IIN
Input Current Through RT (50 Resistor)
Static
Surge
45
80
mA
mA
IOUT
Output Current
Continuous
Surge
25
50
mA
mA
TA
Operating Temperature Range
FCBGA−16
QFN−16
−40 to +70
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
JA
Thermal Resistance (Junction−to−Ambient)
(Note 2)
0 lfpm
500 lfpm
0 lfpm
500 lfpm
FCBGA−16
FCBGA−16
QFN−16
QFN−16
108
86
41.6
35.2
°C/W
°C/W
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case)
2S2P (Note 2)
2S2P (Note 3)
FCBGA−16
5
4.0
°C/W
°C/W
Tsol
Wave Solder
225
265
°C
Pb
Pb−Free
Condition 2
VI v VCC
VI w VEE
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power).
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NBSG14
Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 4)
−40°C
Symbol
Characteristic
25°C
70°C(BGA)/85°C(QFN)**
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
60
75
45
60
75
45
60
75
mA
IEE
Negative Power Supply Current
VOH
Output HIGH Voltage (Note 5)
1525
1575
1625
1550
1610
1650
1575
1635
1675
mV
VOUTPP
Output Amplitude Voltage
315
405
495
315
405
495
315
405
495
mV
VIH
Input HIGH Voltage (Single−Ended)
(Notes 7 and 9)
VCC−
1435
VCC−
1000*
VCC
VCC−
1435
VCC−
1000*
VCC
VCC−
1435
VCC−
1000*
VCC
mV
VIL
Input LOW Voltage (Single−Ended)
(Notes 8 and 9)
VIH−
2500
VCC−
1400*
VIH−
150
VIH−
2500
VCC−
1400*
VIH−
150
VIH−
2500
VCC−
1400*
VIH−
150
mV
VTHR
Input Threshold Voltage
(Single−Ended) (Note 9)
VEE +
1125
VCC−
75
VEE +
1125
VCC−
75
VEE +
1125
VCC−
75
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 6)
1.2
2.5
1.2
2.5
1.2
2.5
V
RTIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
IIH
Input HIGH Current (@ VIH)
80
150
80
150
80
150
A
IIL
Input LOW Current (@ VIL)
25
100
25
100
25
100
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
**The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum
temperature specification of 85°C.
4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.5 V.
5. All outputs loaded with 50 to VCC − 1.5 V for BGA package and VCC − 2 V for QFN package. VOH/VOL measured at VIH/VIL (Typical).
6. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
7. VIH cannot exceed VCC. |VIH − VTHR| < 2600 mV.
8. VIL always ≥ VEE. |VIL − VTHR| < 2600 mV.
9. VTHR is the voltage applied to one input when running in single−ended mode.
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NBSG14
Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 10)
−40°C
Symbol
Characteristic
25°C
70°C(BGA)/85°C(QFN)**
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
45
60
75
45
60
75
45
60
75
mA
VOH
Output HIGH Voltage (Note 11)
2325
2375
2425
2350
2410
2450
2375
2435
2475
mV
VOUTPP
Output Amplitude Voltage
350
440
530
350
440
530
350
440
530
mV
VIH
Input HIGH Voltage (Single−Ended)
(Notes 13 and 15)
VCC−
1435
VCC−
1000*
VCC
VCC−
1435
VCC−
1000*
VCC
VCC−
1435
VCC−
1000*
VCC
mV
VIL
Input LOW Voltage (Single−Ended)
(Notes 14 and 15)
VIH−
2500
VCC−
1400*
VIH−
150
VIH−
2500
VCC−
1400*
VIH−
150
VIH−
2500
VCC−
1400*
VIH−
150
mV
VTHR
Input Threshold Voltage
(Single−Ended) (Note 15)
VEE +
1125
VCC−
75
VEE +
1125
VCC−
75
VEE +
1125
VCC−
75
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 12)
1.2
3.3
1.2
3.3
1.2
3.3
V
RTIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
IIH
Input HIGH Current (@ VIH)
80
150
80
150
80
150
A
IIL
Input LOW Current (@ VIL)
25
100
25
100
25
100
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
**The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum
temperature specification of 85°C.
10. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −0.165 V.
11. All outputs loaded with 50 to VCC − 1.5 V for BGA package and VCC − 2 V for QFN package. VOH/VOL measured at VIH/VIL (Typical).
12. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
13. VIH cannot exceed VCC. |VIH − VTHR| < 2600 mV.
14. VIL always ≥ VEE. |VIL − VTHR| < 2600 mV.
15. VTHR is the voltage applied to one input when running in single−ended mode.
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NBSG14
Table 7. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT
VCC = 0 V; VEE = −3.465 V to −2.375 V (Note 16)
−40°C
Symbol
Characteristic
25°C
70°C(BGA)/85°C(QFN)**
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
45
60
75
45
60
75
45
60
75
mA
VOH
Output HIGH Voltage (Note 17)
−975
−925
−875
−950
−890
−850
−925
−865
−825
mV
VOUTPP
Output Amplitude Voltage
−3.465 V v VEE v −3.0 V
−3.0 V < VEE v −2.375 V
350
315
440
405
530
495
350
315
440
405
530
495
350
315
440
405
530
495
VIH
Input HIGH Voltage (Single−Ended)
(Notes 19 and 21)
VCC−
1435
VCC−
1000*
VCC
VCC−
1435
VCC−
1000*
VCC
VCC−
1435
VCC−
1000*
VCC
mV
VIL
Input LOW Voltage (Single−Ended)
(Notes 20 and 21)
VIH−
2500
VCC−
1400*
VIH−
150
VIH−
2500
VCC−
1400*
VIH−
150
VIH−
2500
VCC−
1400*
VIH−
150
mV
VTHR
Input Threshold Voltage
(Single−Ended) (Note 21)
VEE +
1125
VCC−
75
VEE +
1125
VCC−
75
VEE +
1125
VCC−
75
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 18)
VEE + 1.2
0.0
VEE + 1.2
0.0
0.0
V
RTIN
Internal Input Termination Resistor
45
50
55
45
50
55
50
55
IIH
Input HIGH Current (@ VIH)
80
150
80
150
80
150
A
IIL
Input LOW Current (@ VIL)
25
100
25
100
25
100
A
VEE + 1.2
45
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
**The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum
temperature specification of 85°C.
16. Input and output parameters vary 1:1 with VCC.
17. All outputs loaded with 50 to VCC −1.5 V for BGA package and VCC − 2 V for QFN package. VOH/VOL measured at VIH/VIL (Typical).
18. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
19. VIH cannot exceed VCC. |VIH − VTHR| < 2600 mV.
20. VIL always ≥ VEE. |VIL − VTHR| < 2600 mV.
21. VTHR is the voltage applied to one input when running in single−ended mode.
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NBSG14
Table 8. AC CHARACTERISTICS for FCBGA−16
VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
−40°C
Symbol
Characteristic
25°C
Min
Typ
Max
70°C
Min
Typ
Max
10.7
12
100
125
150
Min
Typ
Max
10.7
12
100
125
150
ps
ps
fmax
Maximum Frequency
(See Figure 4) (Note 22)
10.7
12
tPLH,
tPHL
Propagation Delay to
Output Differential
100
125
150
tSKEW
Duty Cycle Skew (Note 23)
Within−Device Skew (Note 24)
Device−to−Device Skew (Note 25)
2
6
25
10
15
50
2
6
25
10
15
50
2
6
25
10
15
50
tJITTER
RMS Random Clock Jitter
(Figure 4) (Note 27)
fin < 10 GHz
Peak−to−Peak Data Dependent Jitter
(Note 28)
fin < 10 Gb/s
0.2
1
0.2
1
0.2
1
10
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 26)
75
tr
tf
Output Rise/Fall Times
(20% − 80%) @ 1 GHz
20
Q, Q
10
30
2600
75
55
20
30
Unit
GHz
ps
10
2600
75
55
20
30
2600
mV
55
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
22. Measured using a 500 mV source, 50% duty cycle clock source. All outputs loaded with 50 to VCC − 1.5 V. Input edge rates 40 ps
(20% − 80%).
23. See Figure 6. tSKEW = |tPLH − tPHL| for a nominal 50% Differential Clock Input Waveform.
24. Within−Device skew is measured between outputs under identical transitions and conditions on any one device.
25. Device−to−device skew for identical transitions at identical VCC levels.
26. VINPP (MAX) cannot exceed VCC − VEE (applicable only when VCC−VEE < 2600 mV).
27. Additive RMS Jitter with 50% duty cycle clock signal at 10 GHz.
28. Additive Peak−to−Peak data dependent jitter with NRZ PRBS 231−1 data at 10 Gb/s.
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NBSG14
Table 9. AC CHARACTERISTICS for QFN−16
VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
−40°C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 4) (Note 29)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Duty Cycle Skew (Note 30)
Within−Device Skew (Note 31)
Device−to−Device Skew (Note 32)
tJITTER
RMS Random Clock Jitter
(Figure 4) (Note 34)
fin < 10 GHz
Peak−to−Peak Data Dependent Jitter
(Note 35)
fin < 10 Gb/s
Min
Typ
10.5
12
90
125
160
3
6
25
0.2
Max
85°C
Min
Typ
Max
Min
Typ
10.5
12
90
125
160
15
15
50
3
6
25
1
0.2
Max
10.5
12
90
125
160
ps
15
15
50
3
6
25
15
15
50
ps
1
0.2
1
Unit
GHz
ps
10
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 33)
75
tr
tf
Output Rise/Fall Times
(20% − 80%) @ 1 GHz
15
Q, Q
25°C
30
2600
75
55
20
30
2600
75
55
20
30
2600
mV
55
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
29. Measured using a 500 mV source, 50% duty cycle clock source. All outputs loaded with 50 to VCC − 2.0 V. Input edge rates 40 ps
(20% − 80%)
30. See Figure 6. tSKEW = |tPLH − tPHL| for a nominal 50% Differential Clock Input Waveform.
31. Within−Device skew is measured between outputs under identical transitions and conditions on any one device.
32. Device−to−device skew for identical transitions at identical VCC levels.
33. VINPP (MAX) cannot exceed VCC − VEE (applicable only when VCC−VEE < 2600 mV).
34. Additive RMS Jitter with 50% duty cycle clock signal at 10 GHz.
35. Additive Peak−to−Peak data dependent jitter with NRZ PRBS 231−1 data at 10 Gb/s.
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NBSG14
10
9
8
400
7
OUTPUT AMPLITUDE
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÑÑÑÑÑÑÑ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÑÑÑÑÑÑÑ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÑÑÑÑÑÑÑ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÑÑÑÑ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÑÑÑÑ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
6
300
5
200
4
OUTPUT P−P SPEC
(AMPLITUDE GUARANTEE)
3
2
100
RMS JITTER
0
1
2
3
4
5
6
7
1
8
9
10
11
12
0
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at Ambient Temperature (Typical)
X = 17 ps/DIV, Y = 53 mV/DIV
Figure 5. Eye Diagram at 10.8 Gbps
(VCC − VEE = 3.3 V @ 255C with Input Data Pattern of 2^31−1 PRBS.
Total Pk−Pk System Jitter Including Signal Generator is 18 ps.
This Data was taken by Acquiring 7000 Waveforms.)
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10
JITTERout ps (RMS)
OUTPUT VOLTAGE AMPLITUDE (mV)
500
NBSG14
D/CLK
VINPP = = VIH(CLK) − VIL(CLK)
D/CLK
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPLH
tPHL
Figure 6. AC Reference Measurement
Q
Zo = 50
D
Receiver
Device
Driver
Device
Q
D
Zo = 50
50
50
VTT
VTT = VCC − 1.5 V (BGA)
VTT = VCC − 2.0 V (QFN)
Figure 7. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping†
NBSG14BAHTBG
FCBGA−16
(Pb−Free)
100 / Tape & Reel
NBSG14BAR2
FCBGA−16
100 / Tape & Reel
(Contact Sales Representative)
QFN−16
123 Units / Rail
NBSG14MNG
QFN−16
(Pb−Free)
123 Units / Rail
NBSG14MNR2
QFN−16
3000 / Tape & Reel
NBSG14MNR2G
QFN−16
(Pb−Free)
3000 / Tape & Reel
NBSG14MNHTBG
QFN−16
(Pb−Free)
100 / Tape & Reel
Device
NBSG14MN
Board
Description
NBSG14BAEVB
NBSG14BA Evaluation Board
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
NBSG14
PACKAGE DIMENSIONS
FCBGA−16
BA SUFFIX
PLASTIC 4X4 (mm) BGA FLIP CHIP PACKAGE
CASE 489−01
ISSUE O
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
−X−
D
M
−Y−
K
E
M
0.20
3X
e
4
3
2
FEDUCIAL FOR PIN A1
IDENTIFICATION IN THIS AREA
1
A
B
3
C
16 X
b
D
S
VIEW M−M
0.15
M
Z X Y
0.08
M
Z
5
0.15 Z
A
A2
A1
16 X
4
−Z−
0.10 Z
DETAIL K
ROTATED 90 _ CLOCKWISE
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12
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO DATUM
PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
DIM
A
A1
A2
b
D
E
e
S
MILLIMETERS
MIN
MAX
1.40 MAX
0.25
0.35
1.20 REF
0.30
0.50
4.00 BSC
4.00 BSC
1.00 BSC
0.50 BSC
NBSG14
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G−01
ISSUE E
D
ÇÇÇ
ÇÇÇ
ÇÇÇ
PIN 1
LOCATION
2X
A
B
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
ÉÉ
ÉÉ
EXPOSED Cu
0.10 C
TOP VIEW
(A3)
DETAIL B
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
0.10 C
2X
L
L
A1
DETAIL B
A
0.05 C
ÉÉ
ÉÉ
ÇÇ
A3
MOLD CMPD
ALTERNATE
CONSTRUCTIONS
NOTE 4
A1
SIDE VIEW
C
SEATING
PLANE
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.18 TYP
0.30
0.50
0.00
0.15
RECOMMENDED
SOLDERING FOOTPRINT*
0.10 C A B
16X
L
DETAIL A
D2
8
4
16X
16X
0.58
PACKAGE
OUTLINE
1
9
2X
E2
K
2X
1.84 3.30
1
16X
16
e
e/2
BOTTOM VIEW
16X
0.30
b
0.50
PITCH
0.10 C A B
0.05 C
NOTE 3
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
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13
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
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