NBSG72A_06

NBSG72A 2.5V/3.3V SiGe Differential 2 x 2 Crosspoint Switch with Output Level Select The NBSG72A is a high−bandwidth fully differential 2 X 2 crosspoint switch with Output Level Select (OLS) capabilities. This is a part of the GigaComm™ family of high performance Silicon Germanium products. The device is housed in a low profile 3 X 3 mm 16−pin QFN package. Differential inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to program the peak−to−peak output amplitude between 0 mV and 800 mV in five discrete steps. The SELECT inputs are single−ended and can be driven with either LVECL or LVCMOS/LVTTL input levels. Features http://onsemi.com MARKING DIAGRAM* 1 1 QFN−16 MN SUFFIX CASE 485G • • • • • • • Maximum Input Clock Frequency > 7 GHz Typical Maximum Input Data Rate > 7 Gb/s Typical 200 ps Typical Propagation Delay (OLS = FLOAT) 55/45 ps Typical Rise/Fall Times (OLS = FLOAT) Selectable Swing PECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V Selectable Swing NECL Output with NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V Selectable Output Levels (0 mV, 200 mV, 400 mV, 600 mV or 800 mV Peak−to−Peak Output) 50 W Internal Input Termination Resistors (SELA, SELB) Pb−Free Packages are Available A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. • • Single−Ended LVECL or LVCMOS/LVTTL Select Inputs • © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 5 1 Publication Order Number: NBSG72A/D ÇÇ ÇÇ 16 SG 72A ALYWG G NBSG72A VCC 16 VTD0 D0 D0 SELA 1 2 NBSG72A 3 4 5 VEE 6 D1 7 D1 8 VTD1 Q0 15 Q0 14 OLS 13 12 VCC 11 Q1 10 Q1 9 SELB Exposed Pad (EP) Figure 1. QFN−16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin No. 1 2 Name VTD0 D0 I/O − LVDS, CML, ECL, LVTTL, LVCMOS Input LVDS, CML, ECL, LVTTL, LVCMOS Input LVECL, LVCMOS Input − LVDS, CML, ECL, LVTTL, LVCMOS Input LVDS, CML, ECL, LVTTL, LVCMOS Input − LVECL, LVCMOS Input RSECL Output RSECL Output − Input RSECL Output RSECL Output − − Inverted Differential Input 0. Description Common Internal 50 W Termination Pin for D0 and D0 Input. See Table 4. (Note 1) 3 D0 Noninverted Differential Input 0. 4 5 6 SELA VEE D1 Select Logic Input A. Internal 75 kW Pulldown to VEE. Negative Supply. All VEE Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. Inverted Differential Input 1. 7 D1 8 9 VTD1 SELB Q1 Q1 10 11 12 13 14 15 16 − VCC OLS (Note 2) Q0 Q0 VCC EP 1. In the differential configuration when the input termination pins (VTD0, VTD1) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self−oscillation. 2. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, 2 kW resistor should be connected from OLS pin to VEE. Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Noninverted Differential Input 1. Common Internal 50 W Termination Pin for D1 and D1 Input. See Table 4. (Note 1) Select Logic Input B. Internal 75 kW Pulldown to VEE. Noninverted Differential Output. Inverted Differential Output. Positive Supply. All VCC Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. Input Pin for Output Level Select (OLS) See Table 3. Noninverted Differential Output Typically Terminated with 50 W Resistor to VTT = VCC − 2.0 V. Inverted Differential Output Typically Terminated with 50 W Resistor to VTT = VCC − 2.0 V. Positive Supply. All VCC Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. Exposed Pad. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat−sinking conduit. ÁÁ Á ÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ http://onsemi.com 2 NBSG72A VTD0 D0 D0 D1 D1 50 W VTD1 SELA 75 kW 2 SELB 75 kW OLS 2 50 W 2 2 2 Q1 Q1 VCC VEE 2 2 50 W 50 W 2 2 2 Q0 Q0 + Table 2. TRUTH TABLE SELA LOW HIGH LOW HIGH SELB LOW LOW HIGH HIGH Q0 D0 D1 D0 D1 Q1 D0 D0 D1 D1 Figure 2. Logic/Block Diagram Table 3. OUTPUT LEVEL SELECT (OLS) OLS VCC VCC − 0.4 V VCC − 0.8 V VCC − 1.2 V VEE (Note 3) FLOAT Output Amplitude (VOUTPP) 800 mV 200 mV 600 mV 0 400 mV 600 mV OLS Sensitivity OLS − 75 mV OLS ± 150 mV OLS ± 100 mV OLS ± 75 mV OLS ± 100 mV N/A 3. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE. Table 4. INTERFACING OPTIONS Interfacing Options CML LVDS AC−COUPLED RSECL, PECL, NECL LVCMOS / LVTTL Connect VTD0 and VTD1 to VCC VTD0 and VTD1 Should Be Left Floating. Bias VTD0 and VTD1 Inputs within Common Mode Range (VIHCMR) Standard ECL Termination Techniques The external voltage should be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL and VCC/2 for LVCMOS Inputs. Connections http://onsemi.com 3 NBSG72A Table 5. ATTRIBUTES Characteristics Internal Input Pulldown Resistor (SELA, SELB) ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW > 2 kV > 50 V > 1 kV Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in 436 Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 6. MAXIMUM RATINGS Symbol VCC VEE VI VINPP Iout IIN TA Tstg qJA qJC Tsol Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage |DX − DX| Output Current Input Current Through RT (50 W Resistor) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 2) Thermal Resistance (Junction−to−Case) Wave Solder Pb Pb−Free 0 lfpm 500 lfpm (Note 2) < 3 sec @ 260°C < 3 sec @ 260°C QFN−16 QFN−16 QFN−16 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VEE − VCC w 2.8 V VEE − VCC t 2.8 V Continuous Surge Static Surge VI  VCC VI  VEE Condition 2 Rating 3.6 −3.6 3.6 −3.6 2.8 |VCC − VEE| 25 50 45 80 −40 to +85 −65 to +150 42 35 4 265 265 Units V V V V V mA mA mA mA °C °C °C/W °C/W °C/W °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. JEDEC standard multilayer board − 1S2P (1 signal, 2 power). http://onsemi.com 4 NBSG72A Table 7. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 3) −40°C Symbol IEE VOH VOL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) (OLS = VEE) Output Voltage Amplitude (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) (OLS = VEE) Input HIGH Voltage (Single−Ended) (Note 6) D0, D0, D1, D1 Input LOW Voltage (Single−Ended) (Note 7) D0, D0, D1, D1 Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 5) Internal Input Termination Resistor Input HIGH Current (@VIH) Input LOW Current (@VIL) 670 125 510 0 325 VEE + 1275 VEE 1.2 45 50 35 20 800 215 615 5 415 VCC − 1000* VCC− 1400* VCC VIH− 150 2.5 55 100 100 660 120 505 0 320 VEE + 1275 VEE 1.2 45 50 35 20 795 210 610 0 410 VCC − 1000* VCC− 1400* VCC VIH− 150 2.5 55 100 100 655 120 500 0 320 VEE + 1275 VEE 1.2 45 50 35 20 790 210 605 5 410 VCC− 1000* VCC− 1400* VCC VIH− 150 2.5 55 100 100 mV mV V W mA mA 555 1235 775 1455 1005 705 1295 895 1505 1095 855 1385 1015 1585 1215 595 1270 810 1490 1040 745 1330 930 1540 1130 895 1420 1050 1620 1250 625 1295 840 1510 1065 775 1355 960 1560 1155 925 1445 1080 1640 1275 mV Min 40 1460 Typ 55 1510 Max 65 1560 Min 40 1490 25°C Typ 55 1540 Max 65 1590 Min 40 1515 85°C Typ 55 1565 Max 65 1615 Unit mA mV mV VOUTPP VIH VIL VIHCMR RTIN IIH IIL NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *Typicals used for testing purposes. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.965 V. 4. All loading with 50 W to VCC − 2.0 V. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 6. VIH cannot exceed VCC. 7. VIL always w VEE. http://onsemi.com 5 NBSG72A Table 8. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 8) −40°C Symbol IEE VOH VOL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 9) Output LOW Voltage (Note 9) (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) **(OLS = VEE) Output Amplitude Voltage (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) **(OLS = VEE) Input HIGH Voltage (Single−Ended) (Note 11) D0, D0, D1, D1 Input LOW Voltage (Single−Ended) (Note 12) D0, D0, D1, D1 Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) Internal Input Termination Resistor Input HIGH Current (@VIH) Input LOW Current (@VIL) 705 130 535 0 345 VEE + 1275 VIH− 2600 1.2 815 220 640 0 435 VCC − 1000* VCC− 1400* VCC VIH− 150 3.3 695 125 530 0 340 VEE + 1275 VIH− 2600 1.2 805 215 635 0 430 VCC − 1000* VCC− 1400* VCC VIH− 150 3.3 690 125 525 0 335 VEE + 1275 VIH− 2600 1.2 800 215 630 0 425 VCC − 1000* VCC− 1400* VCC VIH− 150 3.3 mV mV V 1320 2030 1550 2260 1785 1470 2090 1670 2310 1875 1620 2180 1790 2390 1995 1360 2065 1585 2290 1820 1510 2125 1705 2340 1910 1660 2215 1825 2420 2030 1390 2090 1615 2315 1850 1540 2150 1735 2365 1940 1690 2240 1855 2445 2060 mV Min 40 2260 Typ 55 2310 Max 65 2360 Min 40 2290 25°C Typ 55 2340 Max 65 2390 Min 40 2315 85°C Typ 55 2365 Max 65 2415 Unit mA mV mV VOUTPP VIH VIL VIHCMR RTIN IIH IIL 45 50 35 20 55 100 100 45 50 35 20 55 100 100 45 50 35 20 55 100 100 W mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *Typicals used for testing purposes. **When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE. 8. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.165 V. 9. All loading with 50 W to VCC − 2.0 V. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 11. VIH cannot exceed VCC. 12. VIL always w VEE. http://onsemi.com 6 NBSG72A Table 9. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT VCC = 0 V; VEE = −3.465 V to −2.375 V (Note 13) −40°C Symbol IEE VOH VOL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 14) Output LOW Voltage (Note 14) −3.465 V v VEE v −3.0 V (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS =FLOAT) (OLS = VCC − 1.2 V) **(OLS = VEE) −3.0 V < VEE v −2.375 V (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS =FLOAT) (OLS = VCC − 1.2 V) (OLS = VEE) Output Voltage Amplitude −3.465 V v VEE v −3.0 V (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) **(OLS = VEE) −3.0 V < VEE v −2.375 V (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS =FLOAT) (OLS = VCC − 1.2 V) (OLS = VEE) Input HIGH Voltage (Single−Ended) (Note 16) D0, D0, D1, D1 Input LOW Voltage (Single−Ended) (Note 17) D0, D0, D1, D1 Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 15) Internal Input Termination Resistor Input HIGH Current (@VIH) Input LOW Current (@VIL) OLS Input Current (See Figure 9) (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) −3.0 V < VEE v −2.375 V (OLS = VEE) −3.465 V v VEE v −3.0 V *(OLS = VEE) Min 40 −1040 Typ 55 −990 Max 65 −940 Min 40 −1010 25°C Typ 55 −960 Max 65 −910 Min 40 −985 85°C Typ 55 −935 Max 65 −885 Unit mA mV mV −1980 −1270 −1750 −1040 −1515 −1945 −1265 −1725 −1045 −1495 −1830 −1210 −1630 −990 −1425 −1795 −1205 −1605 −995 −1405 −1680 −1120 −1510 −910 −1305 −1645 −1115 −1485 −915 −1285 −1940 −1235 −1715 −1010 −1480 −1905 −1230 −1690 −1010 −1460 −1790 −1175 −1595 −960 −1390 −1755 −1170 −1570 −960 −1370 −1640 −1085 −1475 −880 −1270 −1605 −1080 −1450 −880 −1250 −1910 −1210 −1685 −985 −1450 −1875 −1205 −1660 −990 −1435 −1760 −1150 −1565 −935 −1360 −1725 −1145 −1540 −940 −1345 −1610 −1060 −1445 −855 −1240 −1575 −1055 −1420 −860 −1225 mV 705 130 535 0 345 670 125 510 0 325 VEE + 1275 VIH− 2600 815 220 640 0 435 800 215 615 5 415 VCC − 1000* VCC− 1400* VCC VIH− 150 0.0 695 125 530 0 340 660 120 505 0 320 VEE + 1275 VIH− 2600 805 215 635 0 430 795 210 610 0 410 VCC − 1000* VCC− 1400* VCC VIH− 150 0.0 690 125 525 0 335 655 120 500 0 320 VEE + 1275 VIH− 2600 800 215 630 0 425 790 210 605 5 410 VCC − 1000* VCC− 1400* VCC VIH− 150 0.0 mV mV V VOUTPP VIH VIL VIHCMR VEE+1.2 VEE+1.2 VEE+1.2 RTIN IIH IIL IOLS 45 50 35 20 300 100 5 −100 −400 −600 55 100 100 900 300 100 45 50 35 20 300 100 5 −100 −400 −600 55 100 100 900 300 100 45 50 35 20 300 100 5 −100 −400 −600 55 100 100 900 300 100 W mA mA mA −300 −1000 −1500 −300 −1000 −1500 −300 −1000 −1500 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *Typicals used for testing purposes. **When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE. 13. Input and output parameters vary 1:1 with VCC. 14. All loading with 50 W to VCC − 2.0 V. 15. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 16. VIH cannot exceed VCC. 17. VIL always w VEE. http://onsemi.com 7 NBSG72A Table 10. AC CHARACTERISTICS VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V (Note 18) −40°C Symbol VOUTPP Characteristic Output Voltage Amplitude (Note 18) fin < 5 GHz fin v 7 GHz Min 400 200 170 190 170 150 Typ 590 250 205 265 205 215 5.0 5.0 15 0.16 0.14 0.21 0.23 0.18 0.2 0.17 0.14 0.2 0.18 0.16 0.18 12 75 255 350 255 270 25 25 50 0.3 0.4 0.5 0.4 0.5 0.5 0.3 0.4 0.5 0.3 0.6 0.5 18 2600 75 Max Min 450 180 170 190 170 150 25°C Typ 590 250 205 265 205 215 5.0 5.0 15 0.17 0.16 0.31 0.23 0.19 0.25 0.18 0.16 0.27 0.19 0.17 0.24 12 255 350 255 270 25 25 50 0.3 0.4 0.7 0.4 0.5 0.6 0.3 0.3 0.7 0.3 0.4 0.6 18 2600 75 Max Min 440 130 170 190 170 150 85°C Typ 590 250 210 265 210 215 5.0 5.0 15 0.18 0.19 0.44 0.25 0.23 0.32 0.19 0.2 0.38 0.2 0.2 0.34 12 260 350 260 270 25 25 50 0.4 0.4 0.9 0.4 0.5 0.7 0.3 0.3 0.9 0.3 0.4 0.8 18 2600 mV ps ps Max Unit mV tPLH Propagation Delay to Output Differential D0, D1 → Q0, Q1 SELA, SELB → Q0, Q1 Propagation Delay to Output Differential D0, D1 → Q0, Q1 SELA, SELB → Q0, Q1 Duty Cycle Skew (Note 19) Within−Device Skew Device−to−Device Skew RMS Random Clock Jitter (Note 20) v 1 GHz OLS = VCC v 5 GHz OLS = VCC v 6.5 GHz OLS = VCC v 1 GHz OLS = VCC − 400 mV v 5 GHz OLS = VCC − 400 mV v 6.5 GHz OLS = VCC − 400 mV v 1 GHz OLS = VCC − 800 mV v 5 GHz OLS = VCC − 800 mV v 6.5 GHz OLS = VCC − 800 mV v 1 GHz OLS = VEE v 5 GHz OLS = VEE v 6.5 GHz OLS = VEE Peak−to−Peak Data Dependent Jitter (Note 21) fin v 7 Gb/s Input Voltage Swing/Sensitivity (Differential Configuration) (Note 22) Output Rise/Fall Times (20% − 80%) @ 1 GHz (Q0, Q1) tr tf tPHL ps tSKEW ps tJITTER ps VINPP tr tf 40 30 55 45 70 55 40 30 55 45 70 55 40 30 55 45 70 55 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 18. Measured using a 75 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. OLS = FLOAT. Input edge rates 40 ps (20% − 80%). 19. tSKEW = |tPLH − tPHL| for a nominal 50% differential clock input waveform. 20. Additive RMS jitter with 50% Duty Cycle clock signal. 21. Additive Peak−to−Peak data dependent jitter with NRZ PRBS 231−1 data at 7 Gb/s. 22. Input Voltage Swing is a single−ended measurement operating in differential mode. VINPP (max) cannot exceed VCC − VEE. http://onsemi.com 8 NBSG72A 900 OUTPUT VOLTAGE AMPLITUDE (mV) 800 700 600 500 400 300 200 100 0 1 2 3 4 5 6 7 8 9 OLS = VCC − 0.8 V = FLOAT OLS = VCC *OLS = VEE OLS = VCC − 0.4 V INPUT FREQUENCY (GHz) Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input Clock Frequency (fin) @ Ambient Temperature (Typical) *When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE. D0 Input Signal D0 Signal Path NBSG72A Non−Driven Input D1 D1 SELA SELB Q0 Selected Q0 Output 20 0 Measured Q1 Non−Driven Output (VNA) Yscale = 10 dB/div Q1 0 dB Q Logic Low Logic High Q −80 1 Xscale = 1 GHz/div 8 Figure 4. Channel−to−Channel Crosstalk Isolation at Ambient Temperature (D0 to Q0 Signal Path Selected; SelA = Low, SelB = High) D0 Non−Driven Input D0 D1 D1 Input Signal SELA SELB NBSG72A Q0 Selected Q0 Output Q1 20 0 Measured Non−Driven Output Q1 (VNA) Yscale = 10 dB/div 0 dB Q Q Logic High Logic Low −80 1 Xscale = 1 GHz/div 8 Figure 5. Channel−to−Channel Crosstalk Isolation at Ambient Temperature (D1 to Q0 Signal Path Selected; SelA = High, SelB = Low) http://onsemi.com 9 NBSG72A D0 Non−Driven Input D0 D1 Input Signal D1 NBSG72A SELA SELB Signal Path Q0 Non−Driven Q0 Selected Output Q1 20 0 Yscale = 10 dB/div 0dB Measured Output Q1 (VNA) Q Q Logic Low Logic Low −80 1 Xscale = 1 GHz/div 8 Figure 6. Channel−to−Channel Crosstalk Isolation at Ambient Temperature (D0 to Q0 and Q1 Signal Path Selected; SelA = Low, SelB = Low) D0 Input Signal D0 D1 D1 NBSG72A Q0 Measured Output Q0 (VNA) Q1 20 0 Yscale = 10 dB/div 0dB Q Q Non−Driven Input Signal Path SELA SELB Non−Driven Q1 Selected Output Logic High Logic High −80 1 Xscale = 1 GHz/div 8 Figure 7. Channel−to−Channel Crosstalk Isolation at Ambient Temperature (D1 to Q0 and Q1 Signal Path Selected; SelA = High, SelB = High) http://onsemi.com 10 NBSG72A Y = 75 mv/div Total System Jitter = 17.2 ps Input Generator Jitter = 10 ps Device Jitter = 6.8 ps X = 60 ps/div Figure 8. Eye Diagram at 3.2 Gb/s (VCC − VEE = 3.3 V, OLS = FLOAT @ 255C with input pattern of 231−1 PRBS, 5000 Waveforms) Y = 80 mV/div Total System Jitter = 17.2 ps Input Generator Jitter = 10 ps Device Jitter = 7.2 ps X = 21 ps/div Figure 9. Eye Diagram at 7 Gb/s/s (VCC − VEE = 3.3 V, OLS = FLOAT @ 255C with input pattern of 231−1 PRBS, 5000 Waveforms) 300 200 100 0 IOLS (mA) −100 −200 −300 −400 −500 −600 −700 VCC VCC − 400 VCC − 800 VOLS (mV) VCC − 1200 VEE Figure 10. Typical OLS Input Current vs. OLS Input Voltage (VCC − VEE = 3.3 V @ 255C) http://onsemi.com 11 NBSG72A 1000 VCC − 75 800 VOUTPP (mV) VCC − 700 600 VCC − 900 VEE + 100 400 VCC − 250 VCC − 550 200 0 VCC − 1125 VCC VCC − 400 VCC − 800 OLS (mV) VCC − 1275 VEE VCC − 1200 Figure 11. OLS Operating Area D VINPP = VIH(D) − VIL(D) D Q Q tPLH VOUTPP = VOH(Q) − VOL(Q) tPHL Figure 12. AC Reference Measurement Q Driver Device Q Zo = 50 W D Receiver Device Zo = 50 W 50 W 50 W D VTT VTT = VCC − 2.0 V Figure 13. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) http://onsemi.com 12 NBSG72A ORDERING INFORMATION Device NBSG72AMN NBSG72AMNG NBSG72AMNR2 NBSG72AMNR2G Package QFN−16 QFN−16 (Pb−Free) QFN−16 QFN−16 (Pb−Free) Shipping † 123 Units / Rail 123 Units / Rail 3000 / Tape & Reel 3000 / Tape & Reel Board NBSG72AMNEVB Description NBSG72AMN Evaluation Board †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D − ECL Clock Distribution Techniques − Designing with PECL (ECL at +5.0 V) − ECLinPSt I/O SPiCE Modeling Kit − Metastability and the ECLinPS Family − Interfacing Between LVDS and ECL − The ECL Translator Guide − Odd Number Counters Design − Marking and Date Codes − Termination of ECL Logic Devices − Interfacing with ECLinPS − AC Characteristics of ECL Devices http://onsemi.com 13 NBSG72A PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE C D A B PIN 1 LOCATION E NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG DIM A A1 A3 b D D2 E E2 e K L SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 0.15 C 0.15 C 0.10 C 16 X 0.08 C 16X L NOTE 5 4 16X K 1 16 16X 13 b BOTTOM VIEW 0.10 C A B 0.05 C NOTE 3 GigaComm is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative ÇÇ ÇÇ ÇÇ TOP VIEW (A3) SIDE VIEW D2 5 A A1 C e 8 EXPOSED PAD 9 E2 12 e http://onsemi.com 14 NBSG72A/D