NBXDBA014LN1TAG

NBXDBA014 3.3 V, 62.5 MHz / 125 MHz LVPECL Clock Oscillator The NBXDBA014 dual frequency crystal oscillator (XO) is designed to meet today's requirements for 3.3 V LVPECL clock generation applications. The device uses a high Q fundamental crystal and Phase Lock Loop (PLL) multiplier to provide selectable 62.5 MHz or 125 MHz, ultra low jitter and phase noise LVPECL differential output. This device is a member of ON Semiconductor's PureEdget clock family that provides accurate and precision clock solutions. Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape and reel in quantities of 1,000. Features http://onsemi.com MARKING DIAGRAM • • • • • • • • • • • • • • • LVPECL Differential Output Uses High Q Fundamental Mode Crystal and PLL Multiplier Ultra Low Jitter and Phase Noise - 0.4 ps (12 kHz - 20 MHz) Selectable Output Frequency - 62.5 MHz / 125 MHz Frequency Stability - ±50 PPM Hermetically Sealed Ceramic SMD Package RoHS Compliant Operating Range 3.3 V ±10% This is a Pb-Free Device Fiber Distributed Data Interface Ethernet, Gigabit Ethernet Infiniband PCIe Host Bus Adapter RAID Controller VDD 6 CLK CLK 54 6 PIN CLCC LN SUFFIX CASE 848AB DBA014 62.5/125.0 AWLYYWW DBA014 = NBXDBA014 (±50 PPM) 62.5/125.0 = Output Frequency A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week ORDERING INFORMATION Device Package Shipping† Applications NBXDBA014LN1TAG CLCC-6 1000/Tape & Reel (Pb-Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Crystal PLL Clock Multiplier 1 OE 2 FSEL 3 GND Figure 1. Simplified Logic Diagram © Semiconductor Components Industries, LLC, 2007 1 August, 2007 - Rev. 1 Publication Order Number: NBXDBA014/D NBXDBA014 OE 1 6 VDD FSEL 2 5 CLK GND 3 4 CLK Figure 2. Pin Connections (Top View) Table 1. PIN DESCRIPTION Pin No. 1 2 3 4 5 6 Symbol OE I/O LVTTL/LVCMOS Control Input LVTTL/LVCMOS Control Input Power Supply Description Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. See OE pin description Table 2. Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ FSEL GND CLK CLK VDD Output Frequency Select Pin. Pin will default to logic HIGH when left open. See Output Frequency Select pin description Table 3. Ground 0 V LVPECL Output LVPECL Output Power Supply Non-Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to VTT = VDD - 2 V. Non-Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to VTT = VDD - 2 V. Positive power supply voltage. Voltage should not exceed 3.3 V ±10%. Table 2. OUTPUT ENABLE TRI-STATE FUNCTION OE Pin Open HIGH Level LOW Level Output Pin Active Active High Z Table 3. OUTPUT FREQUENCY SELECT FSEL Pin Open (pin will float high) HIGH Level LOW Level Output Frequency (MHz) 62.5 62.5 125 Table 4. ATTRIBUTES Characteristic ESD Protection Human Body Model Machine Model Value 2 kV 200 V Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. Table 5. MAXIMUM RATINGS Symbol VDD Iout TA Tstg Tsol Parameter Positive Power Supply LVPECL Output Current Operating Temperature Range Storage Temperature Range Wave Solder See Figure 6 Condition 1 GND = 0 V Continuous Surge Condition 2 Rating 4.6 25 50 -40 to +85 -55 to +120 260 Units V mA °C °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 NBXDBA014 Table 6. DC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = -40°C to +85°C) Symbol IDD VIH VIL IIH IIL VOH VOL VOUTPP Characteristic Power Supply Current (Note 2) OE and FSEL Input HIGH Voltage OE and FSEL Input LOW Voltage Input HIGH Current Input LOW Current OE FSEL OE FSEL VDD = 3.3 V Output LOW Voltage (Note 2) VDD = 3.3 V Output Voltage Amplitude (Note 2) 2000 GND - 300 -100 -100 -100 -100 VDD-1145 2155 VDD-1945 1355 780 Conditions Min. Typ. 50 Max. 65 VDD 800 +100 +100 +100 +100 VDD-895 2405 VDD-1600 1700 Units mA mV mV mA mA mV mV mV Output HIGH Voltage (Note 2) NOTE: NBX circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 2. Measurement taken with outputs terminated with 50 ohm to VDD-2 V. Table 7. AC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = -40°C to +85°C) Symbol fCLKOUT Characteristic Output Clock Frequency Conditions FSEL = HIGH FSEL = LOW Df FNOISE Frequency Stability NBXDBA014 Phase-Noise Performance fCLKout = 62.5 MHz/125 MHz 10 Years Aging 100 Hz of Carrier 1 kHz of Carrier 10 kHz of Carrier 100 kHz of Carrier 1 MHz of Carrier 10 MHz of Carrier tjit(F) tjitter RMS Phase Jitter Cycle to Cycle, RMS Cycle to Cycle, Peak-to-Peak Period, RMS Period, Peak-to-Peak tOE/OD tDUTY_CYCLE tR tF tstart Output Enable/Disable Time Output Clock Duty Cycle (Measured at Cross Point) Output Rise Time (20% and 80%) Output Fall Time (80% and 20%) Start-up Time Aging 1st Year 48 50 380 400 1 12 kHz to 20 MHz 1000 Cycles 1000 Cycles 10,000 Cycles 10,000 Cycles -111/104 -129/-123 -138/-132 -141/-135 -141/-135 -159/-156 0.4 3 15 2 10 0.9 10 35 5 25 200 52 620 620 5 3 1 Min. Typ. 62.5 125 ±50 ppm dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ps ps ps ps ps ns % ps ps ms ppm ppm Max. Units MHz Every Year After 1st NOTE: NBX circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. http://onsemi.com 3 NBXDBA014 Table 8. RELIABILITY COMPLIANCE Parameter Shock Mechanical Mechanical Mechanical Mechanical Mechanical Standard Method MIL-STD-833, Method 2002, Condition B MIL-STD-833, Method 2003 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Solderability Vibration MIL-STD-833, Method 2007, Condition A MIL-STD-202, Method 215 Solvent Resistance Resistance to Soldering Heat Thermal Shock MIL-STD-203, Method 210, Condition I or J MIL-STD-833, Method 1001, Condition A MIL-STD-833, Method 1004 Environment Environment Moisture Resistance Figure 3. Typical Phase Noise Plot of the NBXDBA014 Operating at 62.5 MHz Figure 4. Typical Phase Noise Plot of the NBXDBA014 Operating at 125 MHz http://onsemi.com 4 NBXDBA014 NBXDBA014 CLK Driver Device CLK Z o = 50 W 50 W 50 W D Z o = 50 W D Receiver Device VTT VTT = VDD - 2.0 V Figure 5. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.) Temperature (°C) 260 217 temp. 260°C 20 - 40 sec. max. peak 3°C/sec. max. 6°C/sec. max. ramp-up 175 150 cooling pre-heat reflow Time 60180 sec. 60150 sec. Figure 6. Recommended Reflow Soldering Profile http://onsemi.com 5 NBXDBA014 PACKAGE DIMENSIONS 6 PIN CLCC, 7x5, 2.54P CASE 848AB-01 ISSUE A D D1 A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. DIM A A1 A2 A3 b D D1 D2 D3 E E1 E2 E3 e L R MIN 1.70 MILLIMETERS NOM MAX 1.80 1.90 0.70 REF 0.36 REF 0.10 0.12 1.40 1.50 7.00 BSC 6.20 6.23 6.81 6.96 5.08 BSC 5.00 BSC 4.40 4.43 4.80 4.95 3.49 BSC 2.54 BSC 1.27 1.37 0.70 REF 4X 0.15 C TERMINAL 1 INDICATOR E2 E1 E 0.08 1.30 6.17 6.66 D2 TOP VIEW A3 0.10 C A A1 SIDE VIEW C D3 e 1 2 3 6X A2 4.37 4.65 1.17 SEATING PLANE SOLDERING FOOTPRINT* 1.50 R E3 0.10 C A B 0.05 C 6X 5.06 6 5 4 6X b BOTTOM VIEW L 2.54 PITCH 6X 1.50 DIMENSION: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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