NCD5700DR2G

NCD5700 High Current IGBT Gate Driver The NCD5700 is a high−current, high−performance stand−alone IGBT driver for high power applications that include solar inverters, motor control and uninterruptable power supplies. The device offers a cost−effective solution by eliminating many external components. Device protection features include Active Miller Clamp, accurate UVLO, EN input, DESAT protection and Active Low FAULT output. The driver also features an accurate 5.0 V output and separate high and low (VOH and VOL) driver outputs for system design convenience. The driver is designed to accommodate a wide voltage range of bias supplies including unipolar and bipolar voltages. It is available in a 16−pin SOIC package. www.onsemi.com MARKING DIAGRAM SOIC−16 D SUFFIX CASE 751B NCD5700DR2G AWLYWW Features • • • • • • • • • • High Current Output (+4/−6 A) at IGBT Miller Plateau Voltages Low Output Impedance of VOH & VOL for Enhanced IGBT Driving Short Propagation Delays with Accurate Matching Direct Interface to Digital Isolator/Opto−coupler/Pulse Transformer for Isolated Drive, Logic Compatibility for Non−isolated Drive Active Miller Clamp to Prevent Spurious Gate Turn−on DESAT Protection with Programmable Delay Enable Input for Independent Driver Control Tight UVLO Thresholds for Bias Flexibility Wide Bias Voltage Range including Negative VEE Capability This Device is Pb−Free, Halogen−Free and RoHS Compliant Typical Applications • • • • Solar Inverters Motor Control Uninterruptible Power Supplies (UPS) Rapid Shutdown for Photovoltaic Systems VREF EN VIN A WL Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS EN 1 16 CLAMP VIN 2 15 VEEA VREF 3 14 VEE FLT 4 13 GND GNDA 5 12 VOL NC 6 11 VOH RSVD 7 10 VCC NC 8 9 DESAT (Top View) DESAT VCC VCC VOH VOL CLAMP GND VEE VEE ORDERING INFORMATION See detailed ordering and shipping information on page 6 of this data sheet. FLT Figure 1. Simplified Application Schematic © Semiconductor Components Industries, LLC, 2017 June, 2017 − Rev. 4 1 Publication Order Number: NCD5700/D NCD5700 Q SET TSD S Q CLR R VREF FLT I DESAT-CHG + VDESAT-THR DESAT R EN-H DELAY - S SET R CLR Q EN Q VCC VREF RIN-H VOH VIN VREF VOL DELAY Bandgap VEE VUVLO + VCC S SET Q R CLR Q + VMC-THR VEE GND CLAMP VEEA Figure 2. Detailed Block Diagram VREF EN CLAMP VREF CLAMP VIN VEEA VCC LDO VEE Logic Unit VREF FLT GNDA GND VOL NC VOH TSD RSVD VCC VCC UVLO NC DESAT Figure 3. Simplified Block Diagram www.onsemi.com 2 DESAT NCD5700 Table 1. PIN FUNCTION DESCRIPTION Pin Name No. I/O/x Description EN 1 I Enable input allows additional gating of VOH and VOL, and can be used when the driver output needs to be turned off independent of the Microcontroller input. VIN 2 I Input signal to control the output. In applications which require galvanic isolation, VIN is generated at the opto output, the pulse transformer secondary or the digital isolator output. There is a signal inversion from VIN to VOH/VOL. VIN is internally clamped to 5.5 V and has a pull−up resistor of 1 MW to ensure that output is low in the absence of an input signal. A minimum pulse−width is required at VIN before VOH/VOL are activated. VREF 3 O 5 V Reference generated within the driver is brought out to this pin for external bypassing and for powering low bias circuits (such as digital isolators). FLT 4 O Fault output (active low) that allows communication to the main controller that the driver has encountered a fault condition and has deactivated the output. Truth Table is provided in the datasheet to indicate conditions under which this signal is asserted. Capable of driving optos or digital isolators when isolation is required. GNDA 5 x This pin provides a convenient connection point for bypass capacitors (e.g REF) on the left side of the package. NC 6,8 x Pins not internally connected. RSVD 7 x Reserved. No connection is allowed. DESAT 9 I Input for detecting the desaturation of IGBT due to a fault condition. A capacitor connected to this pin allows a programmable blanking delay every ON cycle before DESAT fault is processed, thus preventing false triggering. VCC 10 x Positive bias supply for the driver. The operating range for this pin is from UVLO to the maximum. A good quality bypassing capacitor is required from this pin to GND and should be placed close to the pins for best results. VOH 11 O Driver high output that provides the appropriate drive voltage and source current to the IGBT gate. VOL 12 O Driver low output that provides the appropriate drive voltage and sink current to the IGBT gate. VOL is actively pulled low during start−up and under Fault conditions. GND 13 x This pin should connect to the IGBT Emitter with a short trace. All power pin bypass capacitors should be referenced to this pin and kept at a short distance from the pin. VEE 14 x A negative voltage with respect to GND can be applied to this pin and that will allow VOL to go to a negative voltage during OFF state. A good quality bypassing capacitor is needed from VEE to GND. If a negative voltage is not applied or available, this pin must be connected to GND. VEEA 15 x Analog version of the VEE pin for any signal trace connection. VEE and VEEA are internally connected. CLAMP 16 I/O Provides clamping for the IGBT gate during the off period to protect it from parasitic turn−on. To be tied directly to IGBT gate with minimum trace length for best results. www.onsemi.com 3 NCD5700 Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1) Symbol Minimum Maximum Unit VCC−VEE (Vmax) 0 36 V Positive Power Supply VCC−GND −0.3 22 V Negative Power Supply VEE−GND −18 0.3 V Gate Output High VOH−GND VCC + 0.3 V Gate Output Low VOL−GND VEE − 0.3 Input Voltage VIN−GND −0.3 5.5 V Enable Voltage VEN−GND −0.3 5.5 V DESAT Voltage VDESAT−GND −0.3 VCC + 0.3 V Parameter Differential Power Supply FLT Current Sink Source V mA IFLT−SINK IFLT−SRC Power Dissipation SO−16 package 20 25 PD mW 900 Maximum Junction Temperature TJ(max) 150 °C Storage Temperature Range TSTG −65 to 150 °C ESD Capability, Human Body Model (Note 2) ESDHBM 4 kV ESD Capability, Machine Model (Note 2) ESDMM 200 V Moisture Sensitivity Level MSL 1 − Lead Temperature Soldering Reflow (SMD Styles Only), Pb−Free Versions (Note 3) TSLD 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) Latchup Current Maximum Rating: ≤ 100 mA per JEDEC standard: JESD78, 25°C 3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Table 3. THERMAL CHARACTERISTICS Parameter Symbol Value RθJA 145 Unit °C/W Thermal Characteristics, SOIC−16 (Note 4) Thermal Resistance, Junction−to−Air (Note 5) 4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 5. Values based on copper area of 100 mm2 (or 0.16 in2) of 1 oz copper thickness and FR4 PCB substrate. Table 4. OPERATING RANGES (Note 6) Parameter Differential Power Supply Symbol Min VCC−VEE (Vmax) Max Unit 30 V Positive Power Supply VCC UVLO 20 V Negative Power Supply VEE −15 0 V Input Voltage VIN 0 5 V Enable Voltage VEN 0 5 V Input Pulse Width ton 40 Ambient Temperature TA −40 ns 125 °C 6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 4 NCD5700 Table 5. ELECTRICAL CHARACTERISTICS VCC = 15 V, VEE = 0 V, Kelvin GND connected to VEE. For typical values TA = 25°C, for min/max values, TA is the operating ambient temperature range that applies, unless otherwise noted. Parameter Test Conditions Symbol Min Input Threshold Voltages High−state (Logic 1) Required Low−state (Logic 0) Required No state change Pulse−Width = 150 ns, VEN = 5 V Voltage applied to get output to go low Voltage applied to get output to go high Voltage applied without change in output state VIN−H1 VIN−L1 VIN−NC 4.3 Enable Threshold Voltages High−state Low−state VIN = 0 V Voltage applied to get output to go high Voltage applied to get output to go low VEN−H VEN−L 4.3 Typ Max Unit LOGIC INPUT and OUTPUT Input/Enable Internal Pull−Up Resistance to VREF Input/Enable Current High−state Low−state Input Pulse−Width No Response at the Output Guaranteed Response at the Output FLT Threshold Voltage Low State High State V 0.75 3.7 1.2 V 0.75 RIN−H/ REN−H 1 MW mA VIN−H/VEN−H = 4.5 V VIN−L/VEN−L = 0.5 V Voltage thresholds consistent with input specs IIN−H/IEN−H IIN−L/IEN−L 1 10 ton−min1 ton−min2 10 ns 30 V (IFLT−SINK = 15 mA) (IFLT−SRC = 20 mA) VFLT−L VFLT−H 12 0.5 13.9 1.0 0.1 0.2 0.8 0.2 0.5 1.2 DRIVE OUTPUT V Output Low State Isink = 200 mA, TA = 25°C Isink = 200 mA, TA = −40°C to 125°C Isink = 1.0 A, TA = 25°C VOL1 VOL2 VOL3 Isrc = 200 mA, TA = 25°C Isrc = 200 mA, TA = −40°C to 125°C Isrc = 1.0 A, TA = 25°C VOH1 VOH2 VOH3 Peak Driver Current, Sink (Note 7) RG = 0.1 W, VCC = 15 V, VEE = −8 V VO = 13 V VO = 9 V (near Miller Plateau) IPK−snk1 IPK−snk2 6.8 6.1 Peak Driver Current, Source (Note 7) RG = 0.1 W, VCC = 15 V, VEE = −8 V VO = −5 V VO = 9 V (near Miller Plateau) IPK−src1 IPK−src2 7.8 4.0 Output High State V 14.5 14.2 13.8 14.8 14.7 14.1 A A DYNAMIC CHARACTERISTICS Turn−on Delay (see timing diagram) Negative input pulse width = 10 ms tpd−on 45 56 75 ns Turn−off Delay (see timing diagram) Positive input pulse width = 10 ms tpd−off 45 63 75 ns Propagation Delay Distortion (=tpd−on− tpd−off) For input or output pulse width > 150 ns, TA = 25°C TA = −40°C to 125°C tdistort1 tdistort2 −15 −25 −7 5 25 tdistort −tot −30 0 30 Prop Delay Distortion between Parts (Note 7) ns ns Rise Time (Note 7) (see timing diagram) Cload = 1.0 nF trise 9.2 ns Fall Time (Note 7) (see timing diagram) Cload = 1.0 nF tfall 7.9 ns 7. Values based on design and/or characterization. www.onsemi.com 5 NCD5700 Table 5. ELECTRICAL CHARACTERISTICS VCC = 15 V, VEE = 0 V, Kelvin GND connected to VEE. For typical values TA = 25°C, for min/max values, TA is the operating ambient temperature range that applies, unless otherwise noted. Parameter Test Conditions Symbol Min Typ Max Unit Delay from FLT under UVLO/ TSD to VOL td1−OUT 10 12 15 ms Delay from DESAT to VOL (Note 7) td2−OUT 220 ns Delay from UVLO/TSD to FLT (Note 7) td3−FLT 7.3 ms Vclamp 1.2 1.4 2.2 V DYNAMIC CHARACTERISTICS MILLER CLAMP Isink = 500 mA, TA = 25°C Isink = 500 mA, TA = −40°C to 125°C Clamp Voltage Clamp Activation Threshold VMC−THR 1.8 2.0 2.2 V DESAT Threshold Voltage VDESAT−THR 6.0 6.35 7.0 V Blanking Charge Current IDESAT−CHG 0.20 0.24 0.28 mA Blanking Discharge Current IDESAT−DIS DESAT PROTECTION 30 mA UVLO UVLO Startup Voltage VUVLO−OUT−ON 13.2 13.5 13.8 V UVLO Disable Voltage VUVLO−OUT−OFF 12.2 12.5 12.8 V UVLO Hysteresis VUVLO−HYST 1.0 V VREF IREF = 10 mA Voltage Reference VREF Reference Output Current (Note 7) 4.85 5.00 5.15 V 20 mA IREF Recommended Capacitance CVREF 100 nF SUPPLY CURRENT Current Drawn from VCC VCC = 15 V Standby (No load on output, FLT, VREF) ICC−SB Current Drawn from VEE VEE = −10 V Standby (No load on output, FLT, VREF) IEE−SB 0.9 −0.2 1.5 mA −0.14 mA THERMAL SHUTDOWN Thermal Shutdown Temperature (Note 7) TSD 188 °C Thermal Shutdown Hysteresis (Note 7) TSH 33 °C 7. Values based on design and/or characterization. ORDERING INFORMATION Device NCD5700DR2G Package Shipping† SO−16 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 6 NCD5700 TYPICAL CHARACTERISTICS ENABLE TO OUTPUT LOW DELAY (ns) PROPAGATION DELAY (ns) 80 70 tpd−off 60 tpd−on 50 40 −40 −20 0 20 40 60 80 100 120 60 50 40 −40 −20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 4. Propagation Delay vs. Temperature Figure 5. Enable to Output Low Delay 120 20 RISE/FALL TIME (ns) 14 13 12 15 tfall 10 trise 5 11 10 −40 −20 0 20 40 60 80 100 0 −40 120 0 20 40 60 80 100 TEMPERATURE (°C) Figure 6. Fault to Output Low Delay Figure 7. Output Rise/Fall Time 8 8 7 7 6 6 5 5 4 3 2 2 1 1 0 5 10 0 −5 15 0 5 10 VO (V, VCC = 15 V, VEE = −8 V) VO (V, VCC = 15 V, VEE = −8 V) Figure 8. Output Source Current vs. Output Voltage Figure 9. Output Sink Current vs. Output Voltage www.onsemi.com 7 120 4 3 0 −5 −20 TEMPERATURE (°C) IO (A) FAULT TO OUTPUT DELAY (ms) 70 TEMPERATURE (°C) 15 IO (A) 80 15 NCD5700 5.05 5.05 5.04 5.04 5.03 5.03 5.02 5.02 5.01 5.01 VREF (V) VREF (V) TYPICAL CHARACTERISTICS 5.00 4.99 4.99 4.98 4.97 4.97 4.96 4.95 4.96 4.95 −40 2 4 6 8 10 VREF @ IREF = 10 mA −20 0 20 40 60 80 IREF (mA) TEMPERATURE (°C) Figure 10. VREF Voltage vs. Current Figure 11. VCLAMP at 0.5 A 100 120 100 120 6.5 VDESAT (V) 260 IDESET−CHG (mA) 5.00 4.98 0 250 6.4 6.3 240 −40 −20 0 20 40 60 80 100 6.2 −40 120 −20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) Figure 12. DESAT Charge Current vs. Temperature Figure 13. DESAT Threshold Voltage vs. Temperature 15 20 15 10 VO (V) VO, OUTPUT VOLTAGE (V) VREF @ IREF = 0 mA UVLO−OUT−OFF UVLO−OUT−ON 10 5 5 0 0 −5 10 11 12 13 14 15 0 1 2 3 VCC, SUPPLY VOLTAGE (V) VIN (V) Figure 14. UVLO Threshold Voltages Figure 15. VO vs. VIN at 255C (VCC = 15 V, VEE = 0 V) www.onsemi.com 8 4 5 NCD5700 TYPICAL CHARACTERISTICS 1.0 VFLT−L (V) VFLT−H (V) 15 14 13 −40 −20 0 20 40 60 80 100 0.5 0 −40 120 −20 0 20 80 100 TEMPERATURE (°C) Figure 16. Fault Output, Sourcing 20 mA Figure 17. Fault Output, Sinking 15 mA 120 1.4 SUPPLY CURRENT (mA) 1.2 2.0 VCLAMP (V) 60 TEMPERATURE (°C) 2.5 1.5 1.0 ICC 1.0 0.8 0.6 0.4 IEE 0.2 0.5 −40 40 0 −20 0 20 40 60 80 100 120 0 20 40 60 80 TEMPERATURE (°C) FREQUENCY (kHz) Figure 18. VCLAMP at 0.5 A Figure 19. Supply Current vs. Switching Frequency (VCC = 15 V, VEE = −10 V, 255C) www.onsemi.com 9 100 NCD5700 Applications and Operating Information This section lists the details about key features and operating guidelines for the NCD5700. High Drive Current Capability The NCD5700 driver family is equipped with many features which facilitate a superior performance IGBT driving circuit. Foremost amongst these features is the high drive current capability. The drive current of an IGBT driver is a function of the differential voltage on the output pin (VCC−VOH for source current, VOL−VEE for sink current) as shown in Figure 20. Figure 20 also indicates that for a given VOH/VOL value, the drive current can be increased by using higher VCC/VEE power supply). The drive current tends to drop off as the output voltage goes up (for turn−on event) or goes down (for turn−off event). As explained in many IGBT application notes, the most critical phase of IGBT switching event is the Miller plateau region where the gate voltage remains constant at a voltage (typically in 9−11 V range depending on IGBT design and the collector current), but the gate drive current is used to charge/discharge the Miller capacitance (CGC). By providing a high drive current in this region, a gate driver can significantly reduce the duration of the phase and help reducing the switching losses. The NCD5700 addresses this requirement by providing and specifying a high drive current in the Miller plateau region. Most other gate driver ICs merely specify peak current at the start of switching – which may be a high number, but not very relevant to the application requirement. It must be remembered that other considerations such as EMI, diode reverse recovery performance, etc., may lead to a system level decision to trade off the faster switching speed against low EMI and reverse recovery. However, the use of NCD5700 does not preclude this trade−off as the user can always tune the drive current by employing external series gate resistor. Important thing to remember is that by providing a high internal drive current capability, the NCD5700 facilitates a wide range of gate resistors. Another value of the high current at the Miller plateau is that the initial switching transition phase is shorter and more controlled. Finally, the high gate driver current (which is facilitated by low impedance internal FETs), ensures that even at high switching frequencies, the power dissipation from the drive circuit is primarily in the external series resistor and more easily manageable. Experimental results have shown that the high current drive results in reduced turn−on energy (EON) for the IGBT switching. Figure 20. Output Current vs. Output Voltage Drop When driving larger IGBTs for higher current applications, the drive current requirement is higher, hence lower RG is used. Larger IGBTs typically have high input capacitance. On the other hand, if the NCD5700 is used to drive smaller IGBT (lower input capacitance), the drive current requirement is lower and a higher RG is used. Thus, for most typical applications, the driver load RC time constant remains fairly constant. Caution must be exercised when using the NCD5700 with a very low load RC time constant. Such a load may trigger internal protection circuitry within the driver and disable the device. Figure 21 shows the recommended minimum gate resistance as a function of IGBT gate capacitance and gate drive trace inductance. Figure 21. Recommended Minimum Gate Resistance as a Function of IGBT Gate Capacitance www.onsemi.com 10 NCD5700 Gate Voltage Range controller to initiate a more orderly/sequenced shutdown. In case the controller fails to do so, the driver output shutdown ensures IGBT protection after td1−OUT. The negative drive voltage for gate (with respect to GND, or Emitter of the IGBT) is a robust way to ensure that the gate voltage does not rise above the threshold voltage due to the Miller effect. In systems where the negative power supply is available, the VEE option offered by NCD5700 allows not only a robust operation, but also a higher drive current for turn−off transition. Adequate bypassing between VEE pin and GND pin is essential if this option is used. The VCC range for the NCD5700 is quite wide and allows the user the flexibility to optimize the performance or use available power supplies for convenience. Under Voltage Lock Out (UVLO) This feature ensures reliable switching of the IGBT connected to the driver output. At the start of the driver’s operation when VCC is applied to the driver, the output remains turned−off. This is regardless of the signals on VIN until the VCC reaches the UVLO Output Enabled (VUVLO−OUT−ON) level. After the VCC rises above the VUVLO−OUT−ON level, the driver is in normal operation. The state of the output is controlled by signal at VIN. If the VCC falls below the UVLO Output Disabled (VUVLO−OUT−OFF) level during the normal operation of the driver, the Fault output is activated and the output is shut−down (after a delay) and remains in this state. The driver output does not start to react to the input signal on VIN until the VCC rises above the VUVLO−OUT−ON again. The waveform showing the UVLO behavior of the driver is in Figure 22. In an IGBT drive circuit, the drive voltage level is important for drive circuit optimization. If VUVLO−OUT−OFF is too low, it will lead to IGBT being driven with insufficient gate voltage. A quick review of IGBT characteristics can reveal that driving IGBT with low voltage (in 10−12 V range) can lead to a significant increase in conduction loss. So, it is prudent to guarantee VUVLO−OUT−OFF at a reasonable level (above 12 V), so that the IGBT is not forced to operate at a non−optimum gate voltage. On the other hand, having a very high drive voltage ends up increasing switching losses without much corresponding reduction in conduction loss. So, the VUVLO−OUT−ON value should not be too high (generally, well below 15 V). These conditions lead to a tight band for UVLO enable and disable voltages, while guaranteeing a minimum hysteresis between the two values to prevent hiccup mode operation. The NCD5700 meets these tight requirements and ensures smooth IGBT operation. It ensures that a 15 V supply with ±8% tolerance will work without degrading IGBT performance, and guarantees that a fault will be reported and the IGBT will be turned off when the supply voltage drops below 12.2 V. A UVLO event (VCC voltage going below VUVLO−OUT−OFF) also triggers activation of FLT output after a delay of td3−FLT. This indicates to the controller that the driver has encountered an issue and corrective action needs to be taken. However, a nominal delay td1−OUT = 12 ms is introduced between the initiation of the FLT output and actual turning off of the output. This delay provides adequate time for the Figure 22. UVLO Function and Limits Timing Delays and Impact on System Performance The gate driver is ideally required to transmit the input signal pulse to its output without any delay or distortion. In the context of a high−power system where IGBTs are typically used, relatively low switching frequency (in tens of kHz) means that the delay through the driver itself may not be as significant, but the matching of the delay between different drivers in the same system as well as between different edges has significant importance. With reference to Figure 23(a), two input waveforms are shown. They are typical complementary inputs for high−side (HS) and low−side (LS) of a half−bridge switching configuration. The dead−time between the two inputs ensures safe transition between the two switches. However, once these inputs are through the driver, there is potential for the actual gate voltages for HS and LS to be quite different from the intended input waveforms as shown in Figure 23(a). The end result could be a loss of the intended dead−time and/or pulse−width distortion. The pulse−width distortion can create an imbalance that needs to be corrected, while the loss of dead−time can eventually lead to cross−conduction of the switches and additional power losses or damage to the system. The NCD5700 driver is designed to address these timing challenges by providing a very low pulse−width distortion and excellent delay matching. As an example, the delay matching is guaranteed to tDISTORT2 = ±25 ns while many of competing driver solutions can be >250 ns. www.onsemi.com 11 NCD5700 Figure 23(a). Timing Waveforms (Other Drivers) Figure 23(b). NCD5700 Timing Waveforms Active Miller Clamp Protection An alternative way is to provide an additional path from gate to GND with very low impedance. This is exactly what Active Miller Clamp protection does. Additional trace from the gate of the IGBT to the Clamp pin of the gate driver is introduced. After the VO output has gone below the Active Miler Clamp threshold VMC−THR the Clamp pin is shorted to GND and thus prevents the voltage on the gate of the IGBT to rise above the threshold voltage as shown in Figure 25. The Clamp pin is disconnected from GND as soon as the signal to turn on the IGBT arrives to the gate driver input. The fact that the Clamp pin is engaged only after the gate voltage drops below the VMC−THR threshold ensures that the function of this pin does not interfere with the normal turn−off switching performance that is user controllable by choice of RG. This feature is a cost savvy alternative to a negative gate voltage. The main requirement is to hold the gate of the turned−off (for example low−side) IGBT below the threshold voltage during the turn−on of the opposite−side (in this example high−side) IGBT in the half bridge. The turn−on of the high−side IGBT causes high dv/dt transition on the collector of the turned−off low−side IGBT. This high dv/dt then induces current (Miller current) through the CGC capacitance (Miller capacitance) to the gate capacitance of the low−side IGBT as shown in Figure 24. If the path from gate to GND has critical impedance (caused by RG) the Miller current could rise the gate voltage above the threshold level. As a consequence the low−side IGBT could be turned on for a few tens or hundreds of nanoseconds. This causes higher switching losses. One way to avoid this situation is to use negative gate voltage, but this requires second DC source for the negative gate voltage. www.onsemi.com 12 NCD5700 Figure 24. Current Path without Miller Clamp Protection Figure 25. Current Path with Miller Clamp Protection Desaturation Protection (DESAT) At the turned−on output state of the driver, the current IDESAT−CHG from current source starts to flow to the blanking capacitor CBLANK, connected to DESAT pin. Appropriate value of this capacitor has to be selected to ensure that the DESAT pin voltage does not rise above the threshold level VDESAT−THR before the IGBT fully turns on. The blanking time is given by following expression. According to this expression, a 47 pF CBLANK will provide a blanking time of (47p *6.5/0.25m =) 1.22 ms. This feature monitors the collector−emitter voltage of the IGBT in the turned−on state. When the IGBT is fully turned on, it operates in a saturation region. Its collector−emitter voltage (called saturation voltage) is usually low, well below 3 V for most modern IGBTs. It could indicate an overcurrent or similar stress event on the IGBT if the collector−emitter voltage rises above the saturation voltage, after the IGBT is fully turned on. Therefore the DESAT protection circuit compares the collector−emitter voltage with a voltage level VDESAT−THR to check if the IGBT didn’t leave the saturation region. It will activate FLT output and shut down driver output (thus turn−off the IGBT), if the saturation voltage rises above the VDESAT−THR. This protection works on every turn−on phase of the IGBT switching period. At the beginning of turning−on of the IGBT, the collector−emitter voltage is much higher than the saturation voltage level which is present after the IGBT is fully turned on. It takes almost 1 ms between the start of the IGBT turn−on and the moment when the collector−emitter voltage falls to the saturation level. Therefore the comparison is delayed by a configurable time period (blanking time) to prevent false triggering of DESAT protection before the IGBT collector−emitter voltage falls below the saturation level. Blanking time is set by the value of the capacitor CBLANK. The exact principle of operation of DESAT protection is described with reference to Figure 26. At the turned−off output state of the driver, the DESAT pin is shorted to ground via the discharging transistor (QDIS). Therefore, the inverting input holds the comparator output at low level. t BLANK + C BLANK @ V DESAT−THR I DESAT−CHG After the IGBT is fully turned−on, the IDESAT−CHG flows through the DESAT pin to the series resistor RS−DESAT and through the high voltage diode and then through the collector and IGBT to the emitter. Care must be taken to select the resistor RS−DESAT value so that the sum of the saturation voltage, drop on the HV diode and drop on the RS−DESAT caused by current IDESAT−CHG flowing from DESAT source current is smaller than the DESAT threshold voltage. Following expression can be used: V DESAT−THR u R S−DESAT @ I DESAT−CHG ) V F_HV diode ) V CESAT_IGBT Important part for DESAT protection to work properly is the high voltage diode. It must be rated for at least same voltage as the low side IGBT. The safety margin is application dependent. The typical waveforms for IGBT overcurrent condition are outlined in Figure 27. www.onsemi.com 13 NCD5700 Figure 26. Desaturation Protection Schematic Figure 27. Desaturation Protection Waveforms www.onsemi.com 14 NCD5700 Input Signal The input signal controls the gate driver output. Figure 28 shows the typical connection diagrams for isolated applications where the input is coming through an opto−coupler or a pulse transformer. Figure 28. Opto−coupler or Pulse Transformer At Input The relationship between gate driver input signal from a pulse transformer (Figure 29) or opto−coupler (Figure 30) and the output is defined by many time and voltage values. The time values include output turn−on and turn−off delays (tpd−on and tpd−off), output rise and fall times (trise and tfall) and minimum input pulse−width (ton−min). Note that the delay times are defined from 50% of input transition to first 10% of the output transition to eliminate the load dependency. The input voltage parameters include input high (VIN−H1) and low (VIN−L1) thresholds as well as the input range for which no output change is initiated (VIN−NC). VIN−H1 VIN−NC VIN VIN−L1 tpd−off tfall trise ton−min tpd−on VOUT 90% 10% Figure 29. Input and Output Signal Parameters for Pulse Transformer www.onsemi.com 15 NCD5700 VIN−H1 VIN−NC VIN VIN−L1 tpd−off tfall ton−min trise tpd−on 90% VOUT 10% Figure 30. Input and Output Signal Parameters for Opto−coupler Use of VREF Pin highly stable over temperature and line/load variations (see characteristics curves for details) The NCD5700 provides an additional 5.0 V output (VREF) that can serve multiple functions. This output is capable of sourcing up to 10 mA current for functions such as opto−coupler interface or external comparator interface. The VREF pin should be bypassed with at least a 100 nF capacitor (higher the better) irrespective of whether it is being utilized for external functionality or not. VREF is Fault Output Pin This pin provides the feedback to the controller about the driver operation. The situations in which the FLT signal becomes active (low value) are summarized in the Table 6. Table 6. FLT LOGIC TRUTH TABLE VIN ENABLE UVLO DESAT Internal TSD VOUT FLT L H Inactive L L H H Normal operation − Output High Notes H H Inactive L L L H Normal operation − Output Low X L Inactive X L L H Disabled − Output Low, FLT High X X Active X L L L UVLO activated − FLT Low (td3-FLT), Output Low (td3-FLT + td1−OUT) L H Inactive H L L L DESAT activated (only when VIN is low) − Output Low (td2_OUT), FLT Low X X Inactive X H L L Internal Thermal Shutdown − FLT Low (td3-FLT ), Output Low (td3-FLT + td1−OUT) Thermal Shutdown Additional Use of Enable Pin The NCD5700 also offers thermal shutdown function that is primarily meant to self−protect the driver in the event that the internal temperature gets excessive. Once the temperature crosses the TSD threshold, the FLT output is activated after a delay of td3-FLT. After a delay of td1−OUT (12 ms), the output is pulled low and many of the internal circuits are turned off. The 12 ms delay is meant to allow the controller to perform an orderly shutdown sequence as appropriate. Once the temperature goes below the second threshold, the part becomes active again. For some applications, Enable is a useful feature as it provides the ability to shut down the power stage without involving the controls such as DSP. It can also be used along with the VREF pin and a comparator to provide local shutdown protection at fault conditions such as over temperature or over current, as illustrated in Figure 31. www.onsemi.com 16 NCD5700 +V VREF Vcc VIN + EN DESAT NCD5700 VOH VREF OT OC GND VOL VEE VEEA FLT GND CLAMP -V GND GND Figure 31. Additional Over Temperature and/or Over Current Shutdown Protection www.onsemi.com 17 CT MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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