NCL30059
High-Voltage Half-Bridge
Controller for LED Lighting
Applications
The NCL30059 is a self−oscillating high voltage MOSFET driver
primarily tailored for LED driver applications using half−bridge
topology. LLC and LCC configurations are supported with optimized
wide range control offered by the latter for Constant Current (CC)
applications. Due to its proprietary 600 V technology, the driver is
useful for bulk voltages utilized in 277 VAC lighting applications.
Operating frequency of the driver can be adjusted from 25 kHz to
250 kHz using a single resistor. Adjustable brown−out protection
assures correct bulk voltage operating range. An internal 100 ms PFC
delay timer ensures the converter is enabled after the bulk voltage is
fully stabilized. The device provides fixed dead−time which helps to
lower the shoot−through current.
Features
•
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•
•
•
•
•
•
•
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Wide Operating Frequency Range − from 25 kHz to 250 kHz
Minimum Frequency Adjust Accuracy $3%
Fixed Dead Time − 0.6 ms
Adjustable Brown−out Protection for a Simple PFC Association
100 ms PFC Delay Timer
Latched Input for Severe Fault Conditions, e.g. Overtemperature or
OVP
Internal 16 V VCC Clamp
Low Startup Current of 50 mA Maximum
1 A / 0.5 A Peak Current Sink / Source Drive Capability
Operation up to 600 V Bulk Voltage
Internal Temperature Shutdown
Supports Outdoor Use: −40°C to +125°C
PSR Current Regulation $2%
Efficiency up to 92%
SOIC−8 Package
These are Pb−Free Devices
Typical Applications
•
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•
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MARKING
DIAGRAM
8
8
30059B
ALYWW
G
1
SOIC−8
CASE 751
A
L
Y
WW
G
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PINOUT DIAGRAM
Vboot
VCC
Rt
Mupper
BO
HB
GND
Mlower
ORDERING INFORMATION
Device
Package
Shipping†
NCL30059BDR2G
SOIC−8
(Pb−Free)
2500 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Low Cost Resonant Converters
Low Parts Count
CV and CC LED Drivers
Wide Output Voltage Range LCC Drivers
Wallpack and Bollard LED Drivers
High Bay and Streetlight LED Drivers
© Semiconductor Components Industries, LLC, 2017
December, 2018 − Rev. 0
1
Publication Order Number:
NCL30059/D
NCL30059
+HV
Dboot
Rbo1
Cboot
U1
Vcc
Vboot
Mupper
Vcc
NCL30059
AC
Input
PFC
Front
End
BO
GND
LED1
M1
Lres
HB
Mlower
Rt
Rbias
Rfmax
LED2
Cres
Ccomp
Diso
U2
Rbo2
Chb
M2
Rfb1
Rfstart
CSS
Rfb2
Cave
Rsense
Return
Figure 1. Typical LCC Application Example
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2
NCL30059
VDD
Vboot
S
Q
Pulse
Trigger
D
+
−
Vref
Rt
Ct
+
−
Level
Shifter
S
Q
R
Q
Mupper
CLK
R
Q
Vref
Bridge
UV
Detect
IDT
PFC Delay
(100ms)
VCC
VDD
VCC
Vref
PON
RESET
VCC
Mlower
Delay
VCC
Management
VCC
Clamp
TSD
−
+
+
−
20ms
Filter
Q
S
R
Vreflatch
BO
+
−
+
−
VrefBO
Ihyster
SW
20ms
Filter
Switch SW Open for VBO > VrefBO
GND
Figure 2. Internal Circuit Architecture
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3
NCL30059
PIN FUNCTION DESCRIPTION
Pin #
Pin Name
Function
1
VCC
Supplies the Driver
Pin Description
2
Rt
Timing Resistor
3
BO
Brown−Out
Detects low input voltage conditions. When brought above Vlatch, it fully latches off
the driver.
4
GND
IC Ground
−
5
Mlower
Low−Side Driver Output
Drives the lower side MOSFET.
6
HB
Half−Bridge Connection
Connects to the half−bridge output.
7
Mupper
High−Side Driver Output
Drives the higher side MOSFET.
8
Vboot
Bootstrap Pin
The driver accepts up to 16 V (given by internal zener clamp).
Connecting a resistor between this pin and GND, sets the operating frequency
The floating supply terminal for the upper stage.
MAXIMUM RATINGS TABLE
Symbol
Rating
Vbridge
High Voltage Bridge Pin − Pin 6
Vboot −
Vbridge
Floating Supply Voltage
Value
Unit
−1 to +600
V
0 to 20
V
VDRV_HI
High−Side Output Voltage
Vbridge − 0.3 to
Vboot + 0.3
V
VDRV_LO
Low−Side Output Voltage
−0.3 to VCC +0.3
V
$50
V/ns
20
mA
−0.3 to 5
V
−0.3 to 10
V
178
°C/W
147
°C/W
−60 to +150
°C
2
kV
200
V
dVbridge/dt Allowable Output Slew Rate
ICC
V_Rt
Maximum Current that Can Flow into VCC Pin (Pin 1), (Note 1)
Rt Pin Voltage
Maximum Voltage, All Pins (Except Pins 4 and 5)
mm2
RqJA
Thermal Resistance Junction−to−Air, IC Soldered on 50
RqJA
Thermal Resistance Junction−to−Air, IC Soldered on 200 mm2 Cooper 35 mm
Cooper 35 mm
Storage Temperature Range
ESD Capability, Human Body Model (All Pins Except Pins 1 , 6, 7 and 8)
ESD Capability, Machine Model (All Pins Except Pins 1, 6, 7 and 8)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device contains internal zener clamp connected between VCC and GND terminals. Current flowing into the VCC pin has to be limited
by an external resistor when device is supplied from supply which voltage is higher than VCCclamp (16 V typically). The ICC parameter is
specified for VBO = 0 V.
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NCL30059
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C,
VCC = 12 V, unless otherwise noted)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
Turn−On Threshold Level, VCC Going Up
1
VCCON
10
11
12
V
Minimum Operating Voltage after Turn−On
1
VCCmin
8
9
10
V
Startup Voltage on the Floating Section
1
VbootON
7.8
8.8
9.8
V
Cutoff Voltage on the Floating Section
1
Vbootmin
7
8
9
V
VCC Level at which the Internal Logic gets Reset
1
VCCreset
−
6.5
−
V
Startup Current, VCC < VCCON, 0°C v Tamb v +125°C
1
ICC
−
−
50
mA
Startup Current, VCC < VCCON, −40°C v Tamb < 0°C
1
ICC
−
−
65
mA
Internal IC Consumption, No Output Load on Pins 8/7 − 5/4, Fsw = 100 kHz
1
ICC1
−
2.2
−
mA
Internal IC Consumption, 1 nF Output Load on Pins 8/7 − 5/4, Fsw = 100 kHz
1
ICC2
−
3.4
−
mA
Consumption in Fault Mode (Drivers Disabled, VCC > VCC(min), RT = 3.5 kW)
1
ICC3
−
2.56
−
mA
Consumption During PFC Delay Period, 0°C v Tamb v +125°C
ICC4
−
−
400
mA
Consumption During PFC Delay Period, −40°C v Tamb < 0°C
ICC4
−
−
470
mA
SUPPLY SECTION
Internal IC Consumption, No Output Load on Pin 8/7 FWS = 100 kHz
8
Iboot1
−
0.3
−
mA
Internal IC Consumption, 1 nF Output Load on Pin 8/7 FWS = 100 kHz
8
Iboot2
−
1.44
−
mA
Consumption in Fault Mode (Drivers Disabled, Vboot > Vbootmin)
8
Iboot3
−
0.1
−
mA
VCC Zener Clamp Voltage @ 20 mA
1
VCCclamp
15.4
16
17.5
V
Minimum Switching Frequency, Rt = 35 kW on Pin 2, DT = 600 ns
2
FSW min
24.25
25
25.75
kHz
Maximum Switching Frequency, Rt = 3.5 kW on Pin 2, DT = 600 ns
2
FSW max
208
245
282
kHz
Reference Voltage for all Current Generations
2
Vref RT
3.33
3.5
3.67
V
INTERNAL OSCILLATOR
Internal Resistance Discharging Csoft−start
2
Rtdischarge
−
500
−
W
5, 7
DC
48
50
52
%
Output Voltage Rise Time @ CL = 1 nF, 10−90% of Output Signal
5, 7
Tr
−
40
−
ns
Output Voltage Fall Time @ CL = 1 nF, 10−90% of Output Signal
5, 7
Tf
−
20
−
ns
Source Resistance
5, 7
ROH
−
12
−
W
Sink Resistance
5, 7
ROL
−
5
−
W
Dead−Time (Measured Between 50% of Rise and Fall Edge)
5,7
T_dead
540
610
720
ns
6,7,8
IHV_Leak
−
−
5
mA
Brown−Out Input Bias Current
3
IBObias
−
0.01
−
mA
Brown−Out Level
3
VBO
0.95
1
1.05
V
Hysteresis Current, Vpin3 < VBO
3
IBO
15.6
18.2
20.7
mA
Latching Voltage on BO Pin
3
Vlatch
1.9
2
2.1
V
Propagation Delay Before Drivers are Stopped
3
EN Delay
−
20
−
ms
Delay Before Any Driver Restart
−
PFC Delay
−
100
−
ms
Temperature Shutdown (Guaranteed by design)
−
TSD
140
−
−
°C
Hysteresis
−
TSDhyste
−
30
−
°C
Operating Duty Cycle Symmetry
NOTE:
Maximum capacitance directly connected to Pin 2 must be under 100 pF.
DRIVE OUTPUT
Leakage Current on High Voltage Pins to GND (600 Vdc)
PROTECTION
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NCL30059
11.01
8.98
11.00
8.97
8.96
10.98
VOLTAGE (V)
VOLTAGE (V)
10.99
10.97
10.96
10.95
10.94
−20
0
20
40
60
80
100
8.90
−40
120
20
40
60
Figure 3. VCCon
Figure 4. VCCmin
8.10
8.80
8.05
8.75
8.70
8.65
80
100
120
8.00
7.95
7.90
7.85
8.60
7.80
−20
0
20
40
60
80
100
7.75
−40
120
−20
0
20
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. VBOOTon
Figure 6. VBOOTmin
20
80
100
120
80
100
120
8
18
7
16
6
RESISTANCE (W)
14
12
10
8
6
4
5
4
3
2
1
2
0
−40
0
TEMPERATURE (°C)
8.85
8.55
−40
−20
TEMPERATURE (°C)
VOLTAGE (V)
VOLTAGE (V)
8.93
8.91
10.92
RESISTANCE (W)
8.94
8.92
10.93
10.91
−40
8.95
−20
0
20
40
60
80
100
0
−40
120
−20
0
20
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. ROH
Figure 8. ROL
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NCL30059
25.05
243.4
25.00
243.0
FREQUENCY (kHz)
FREQUENCY (kHz)
243.2
242.8
242.6
242.4
242.2
24.85
−20
0
20
40
60
80
100
24.75
−40
120
40
60
Figure 10. FSWmin
40.0
400
35.0
350
30.0
300
25.0
20.0
15.0
50
60
80
100
0
−40
120
−20
0
20
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. ICC_startup
Figure 12. ICC4
580
120
80
100
120
80
100
120
150
5.0
40
100
200
100
20
80
250
10.0
0
20
Figure 9. FSWmax
450
−20
0
TEMPERATURE (°C)
45.0
0.0
−40
−20
TEMPERATURE (°C)
CURRENT (mA)
CURRENT (mA)
24.90
24.80
242.0
241.8
−40
24.95
645
560
640
635
520
TIME (ns)
RESISTANCE (W)
540
500
480
460
630
625
620
440
615
420
400
−40
−20
0
20
40
60
80
100
610
−40
120
−20
0
20
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Rt_discharge
Figure 14. Tdead
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NCL30059
109
2.008
108
2.006
107
2.004
VOLTAGE (V)
TIME (ms)
106
105
104
103
102
1.998
1.996
1.992
100
−20
0
20
40
60
80
100
1.990
−40
120
0
20
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. VLATCH
1.015
19.4
1.014
19.2
80
100
120
80
100
120
19.0
CURRENT (mA)
1.012
1.011
1.010
1.009
18.8
18.6
18.4
18.2
18.0
17.8
1.008
1.007
−40
−20
Figure 15. PFCdelay
1.013
VOLTAGE (V)
2.000
1.994
101
90
−40
2.002
17.6
−20
0
20
40
60
80
100
17.4
−40
120
−20
0
20
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. VBO
Figure 18. IBO
17.0
290
16.8
FREQUENCY (kHz)
VOLTAGE (V)
240
16.6
16.4
16.2
140
90
16.0
15.8
−40
190
−20
0
20
40
60
80
100
40
0.2
120
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
TEMPERATURE (°C)
Irt (mA)
Figure 19. VCC_clamp
Figure 20. Irt and Appropriate Frequency
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1
NCL30059
APPLICATION INFORMATION
• Latched Input: The latched comparator input is
The NCL30059 is primarily intended to drive low cost
half−bridge applications. It supports LLC and optimized
LCC topologies offering wide output voltage range in
constant current (CC) mode making it ideal for LED drivers.
The IC includes several features that help the designer to
cope with resonant SPMS design. All features are described
thereafter:
• Wide Operating Frequency Range: The internal
current controlled oscillator is capable to operate over
wide frequency range up to 250 kHz. Minimum
frequency accuracy is $3%.
• Fixed Dead−Time: Internal dead−time control is
optimized to avoid cross conduction or shoot−through
during transitions between low and high side
conduction.
• 100 ms PFC Timer: Fixed delay is placed to IC
operation whenever the driver restarts (VCCON or
BO_OK detect events). This delay assures that the bulk
voltage will be stabilized prior to switching operation.
Another benefit of this delay is that the soft start
capacitor will be fully discharged before any restart.
• Brown−Out Detection: The BO input monitors bulk
voltage level via resistor divider and thus assures that
the application is working only for wanted bulk voltage
band. The BO input sinks current of 18.2 mA until the
VrefBO threshold is reached. Designer can thus adjust
the bulk voltage hysteresis according to the application
needs.
•
•
connected in parallel to the BO terminal to allow the
designer latch the IC if necessary − overvoltage or
overtemperature shutdown can be implemented using
this latch. The supply voltage has to be cycled down
below VCCreset threshold, or VBO diminished under
VBO level to reset the latch and enable restart.
Internal VCC Clamp: The internal zener clamp offers
a way to prepare passive voltage regulator to maintain
VCC voltage at 16 V in case the controller is supplied
from unregulated power supply or from bulk capacitor.
Low Startup Current: This device features maximum
startup current of 50 mA which allows the designer to
use high value startup resistor for applications when
driver is supplied from the auxiliary winding. Power
dissipation of startup resistor is thus significantly
reduced.
Current Controlled Oscillator
The current controlled oscillator features a high−speed
circuitry allowing operation from 50 kHz up to 500 kHz.
However, as a division by two internally creates the two Q
and Q outputs, the final effective signal on output Mlower
and Mupper switches between 25 kHz and 250 kHz. The
VCO is configured in such a way that if the current that flows
out from the Rt pin increases, the switching frequency also
goes up. Figure 21 shows the architecture of this oscillator.
V DD
S
Q
A
Q
B
D
+
−
+
−
Rsoft−start
Csoft−start
Rt
Rt
+
−
CLK
R
IDT
Ct
+
−
Vref Rt
Dead
Time
Vref
Delay
PON Reset
From PFC Delay
Figure 21. The Internal Current Controlled Oscillator Architecture
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NCL30059
This is valuable for applications that are supplied from
auxiliary winding and VCC capacitor is supposed to provide
energy during PFC delay period.
For resonant LED driver applications it is necessary to
adjust minimum operating frequency with high accuracy.
The designer also needs to limit maximum operating and
startup frequency. All these parameters can be adjusted
using few external components connected to the Rt pin as
depicted in Figure 22.
The internal timing capacitor Ct is charged by current
which is proportional to the current flowing out from the
Rt pin. The discharging current IDT is applied when voltage
on this capacitor reaches 2.5 V. The output drivers are
disabled during discharge period so the dead time length is
given by the discharge current sink capability. Discharge
sink is disabled when voltage on the timing capacitor
reaches zero and charging cycle starts again. The charging
current and thus also whole oscillator is disabled during the
PFC delay period to keep the IC consumption below 400 mA.
NCL30059
Rt
V CC
Rfmax
Rfmax−CC
Rbias
Rfstart
D1
Rt
Rcomp
(to secondary
voltage regulator)
Ccomp
CSS
TLV431
Voltage Feedback
(to primary
current sensor)
Current Feedback
Figure 22. Typical Rt Pin Connection
regulator. This voltage difference is applied across
Rfmax−CC.
The TLV431 shunt regulator is used in Figure 22 as the
constant current control regulator. Diode D1 is used to
establish minimum regulator bias current via resistor Rbias.
Total saturation voltage of this solution is 1.25 + 0.6 = 1.85
V for room temperature. Shottky diode will further decrease
saturation voltage. The Rfmax−CC resistor limits the
maximum frequency delivered by this regulation loop. This
parameter is affected by D1 temperature drift.
The minimum switching frequency is given by the Rt
resistor value. This frequency is reached if there is no
optocoupler or current feedback action and soft start period
has been already finished. The maximum switching
frequency excursion is limited by the Rfmax selection. Note
that the Fmax value is influenced by the optocoupler
saturation voltage value. Resistor Rfstart together with
capacitor CSS prepares the soft start period after PFC timer
elapses. The Rt pin is grounded via an internal switch during
the PFC delay period to assure that the soft start capacitor
will be fully discharged via Rfstart resistor.
Constant LED current is achieved using a feedback loop
monitoring the primary current. The sensing voltage must be
scaled by the turns ratio of the transformer. The Rt pin
reference voltage is VrefRt = 3.5 V. The control regulator
operates on the difference between the Rt pin reference
voltage and the minimum voltage compliance of the
Brown−Out Protection
The Brown−Out circuitry (BO) offers a way to protect the
application from low DC input voltages. Operation is
blocked below a set threshold. Hysteresis is provided by the
switched current source providing stable operation. The
internal circuitry, depicted by Figure 23, offers a way to
monitor the high−voltage (HV) rail.
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NCL30059
Vbulk
Rupper
BO
+
−
+
−
Rlower
20ms
Filter
to BO_OK and gates
VrefBO
SW
To PFC Delay
IBO
High Level for 50 ms after VCC On
Figure 23. The internal Brown−Out Configuration with an Offset Current Sink
internal BO_OK signal is high (PFC timer runs or Mlower
and Mupper pulse), the IBO sink is deactivated. As a result,
it becomes possible to select the turn−on and turn−off levels
via a few lines of algebra:
A resistive divider made of Rupper and Rlower, brings a
portion of the HV rail on Pin 3. Below the turn−on level,
the 18.2 mA current sink (IBO) is on. Therefore, the turn−on
level is higher than the level given by the division ratio
brought by the resistive divider. To the contrary, when the
IBO is ON
Vref BO + V bulk1 @
R lower
R lower ) R upper
* I BO @
ǒ
R lower @ R upper
Ǔ
R lower ) R upper
(eq. 1)
IBO is OFF
R lower
Vref BO + V bulk2 @
R lower ) R upper
(eq. 2)
We can extract Rlower from Equation 2 and plug it into Equation 1, then solve for Rupper:
R lower + Vref BO @
V bulk1 * V bulk2
I BO @ ǒV bulk2 * Vref BOǓ
R upper + R lower @
V bulk2 * Vref BO
Vref BO
(eq. 3)
(eq. 4)
If we decide to turn−on our converter for Vbulk1 equals 350 V and turn it off for Vbulk2 equals 250 V, then for IBO = 18.2 mA
and VrefBO = 1.0 V we obtain:
Rupper = 5.494 MW
Rlower = 22.066 V
The bridge power dissipation is 4002 / 5.517 MW = 29 mW when front−end PFC stage delivers 400 V. Figure 24 simulation
result confirms our calculations.
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NCL30059
Figure 24. Simulation Results for 350/250 ON/OFF Brown−Out Levels
Figure 25. BO Input Functionality − Vbulk2 < Vbulk < Vbulk1
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NCL30059
Figure 26. BO Input Functionality −Vbulk2 < Vbulk < Vbulk1, PFC Start Follows
Figure 27. BO Input Functionality − Vbulk > Vbulk1
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NCL30059
Figure 28. BO Input Functionality − Vbulk < Vbulk2, PFC Start Follows
Latched−Off Protection
The IBO current sink is turned ON for 50 ms after any
controller restart to let the BO input voltage stabilize (there
can be connected big capacitor to the BO input and the IBO
is only 18.2 mA so it will take some time to discharge). Once
the 50 ms one shoot pulse ends the BO comparator is
supposed to either hold the IBO sink turned ON (if the bulk
voltage level is not sufficient) or let it turned OFF (if the bulk
voltage is higher than Vbulk1). See Figures 25 through 28 for
better understanding on how the BO input works.
VCC
There are some situations where the converter shall be
fully turned−off and stay latched. This can happen in
presence of an overvoltage (the feedback loop is drifting) or
when an overtemperature is detected. Due to the addition of
a comparator on the BO Pin, a simple external circuit can lift
up this pin above Vlatch (2 V typical) and permanently
disable pulses. The VCC needs to be cycled down below
6.5 V typically to reset the controller.
Vbulk
Vout
+
−
Q1
+
−
20ms
Filter
Vreflatch
Rupper
BO
NTC
to Permanent Latch
Rlower
SW
IBO
+
−
+
−
20ms
Filter
BO_OK
VrefBO
To PFC Delay
High Level for 50 ms After VCC On
Figure 29. Adding a Comparator on the BO Pin Offers a Way to Latch−Off the Controller
On Figure 29, Q1 is biased off and does not affect the BO
measurement as long as the NTC and the optocoupler are not
activated. As soon as the secondary optocoupler senses an
OVP condition, or the NTC reacts to a high ambient
temperature, Q1 base is biased on and the BO Pin goes up,
permanently latching off the controller.
The High−Voltage Driver
Figure 30 shows the internal architecture of the
high−voltage section. The device incorporates an upper
UVLO circuitry that makes sure enough Vgs is available for
the upper side MOSFET. The VCC for floating driver section
is provided by Cboot capacitor that is refilled by external
bootstrap diode.
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NCL30059
Vboot
Pulse
Trigger
Level
Shifter
S
Q
R
Q
Cboot
Mupper
HB
UV
Detect
DEAD TIME
Vbulk
Dboot
from PFC
Delay
B
VCC
Vaux
+
B
A
A
Delay
Mlower
GND
from latch
high if OK
Figure 30. The Internal High−Voltage Section of the NCL30059
The A and B outputs are delivered by the internal logic, as
depicted in block diagram. This logic is constructed in such
a way that the Mlower driver starts to pulse firs after any
driver restart. The bootstrap capacitor is thus charged during
first pulse. A delay is inserted in the lower rail to ensure good
matching between these propagating signals. As stated in the
maximum rating section, the floating portion can go up to
600 Vdc and makes the IC perfectly suitable for offline
applications featuring a 400 V PFC front−end stage.
www.onsemi.com
15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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