NCN6024DWR2G

NCN6024 Compact and Low Cost Smart Card Interface IC The NCN6024 is a compact and low cost single smart card interface IC. It is dedicated for 3.0 V/5.0 V smart card reader/writer applications. The device is fully compatible with the ISO 7816−3 and EMV standards as well as with standards specifying conditional access in Set−Top−Box (STB). Features http://onsemi.com MARKING DIAGRAMS 28 NCN6024 AWLYYWWG SOIC−28* CASE 751F 1 • Single IC Card Interface • Fully Compatible with ISO 7816−3, EMV and Related Standards • • • • • • • • • • • • Including STB Standards Three Protected Bidirectional Buffered I/O Lines (C4, C7 and C8 Card Pins) 3.0 V or 5.0 V ± 5% Regulated Card Power Supply such as ICC ≤ 65 mA at VDDP = 4.5 V to 5.5 V Independent Power Supply on Controller Interface (2.7 V < VDD < 5.5 V) Thermal and Short Circuit Protection on all Card Pins Support up to 20 MHz Clock with Internal Division Ratio 1/1, 1/2, 1/4 and 1/8 through CLKDIV1 and CLKDIV2 ESD Protection on Card Pins up to 8 kV+ (Human Body Model) Activation/Deactivation Sequences Fault Protection Mechanisms Enabling Automatic Device Deactivation in Case of Overload, Overheating, Card Take−off or Power Supply Drop−out Interrupt Signal INT for Card Presence and Faults External Undervoltage Lockout Threshold Adjustment on VDD (PORADJ Pin) Available in 2 Package Formats: SOIC−28 and TSSOP−28 These are Pb−Free Devices *Consult Sales Office NCN 6024G ALYW TSSOP−28 CASE 948AA NCN6024 = Specific Device Code A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb−Free Package Typical Application ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. • Pay TV, Set Top Box Decoder with Conditional Access and • • • • Pay−per−View Conditional Access Module (CAM) Portable Systems Point Of Sales and Transaction Terminals Electronic Payment and Identification © Semiconductor Components Industries, LLC, 2009 July, 2009 − Rev. 1 1 Publication Order Number: NCN6024/D NCN6024 VDDP 10 uF VDD 100 nF Microcontroller VDD R1 R2 NCN6024 CMDVCC 5V/3V CLKDIV1 CLKDIV2 CLK_IN VDD INT PORADJ 100 nF VDDP C1 C2 VUP CRD_PRES CRD_PRES CRD_VCC CRD_RST CRD_CLK CRD_AUX1 CRD_AUX2 CRD_IO CRD_GND GNDP GND GND GND 100 nF GND 220 nF 1 2 3 4 100 nF 100 nF SMART CARD DET Vcc RST CLK C4 DET GND Vpp I/O C8 CONTROL 5 GND 6 7 8 DATAPORT RSTIN I/Ouc AUX1uc AUX2uc Figure 1. Typical Smart Card Interface Application CLKDIV1 CLKDIV2 5V/3V GNDP C2 VDDP C1 VUP CRD_PRES CRD_PRES CRD_I/O CRD_AUX2 CRD_AUX1 CRD_GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AUX2uc AUX1uc I/Ouc NC CLKIN INT GND VDD RSTIN CMDVCC PORADJ CRD_VCC CRD_RST CRD_CLK Figure 2. SOIC−28 and TSS0P−28 Pinout (Top View) http://onsemi.com 2 NCN6024 VDD 21 VDDP 6 9 CRD_PRES INT 23 Interrupt Block Card Detection 10 CRD_PRES 5V/3V CMDVCC PORADJ CLKDIV1 CLKDIV2 3 19 18 1 2 Thermal Control Clock Dividers Supply Voltage Monitoring DC/DC Converter Internal Oscillator 2.5 MHz 17 CRD_VCC 4 8 GNDP VUP 5 7 C2 C1 CLKIN NC RSTIN I/Ouc AUX2uc 24 25 20 26 27 28 22 15 CRD_CLK Control Logic and Sequencer Card Pin Drivers 16 CRD_RST 11 CRD_I/O 13 CRD_AUX2 12 CRD_AUX1 14 CRD_GND AUX1uc GND Figure 3. NCN6024 Block Diagram PIN FUNCTION AND DESCRIPTION Pin # 1 2 3 4 5 6 7 8 9 10 Name CLKDIV1 CLKDIV2 5V/3V GNDP C2 VDDP C1 VUP CRD_PRES CRD_PRES Type Input Input Input GND Power Power Power Power Input Input Description This pin coupled with CLKDIV2 is used to program the clock frequency division ratio (Table 1). This pin coupled with CLKDIV1 is used to program the clock frequency division ratio (Table 1). Allows selecting card VCC power supply voltage. CRD_VCC = 5 V when 5V/3V = HIGH or 3 V when 5V/3V = LOW DC/DC Converter Power Supply Ground DC/DC Converter Capacitor pin number 2 − A 100 nF capacitor is connected between this pin and pin C1. The capacitor has to feature an ESR lower than 100 mW DC/DC Converter Power Supply Voltage DC/DC Converter Capacitor pin number 1 − A 100 nF capacitor is connected between this pin and pin C2. The capacitor has to feature an ESR lower than 100 mW Charge−pump output tank capacitor − a very low ESR 100 nF capacitor (ESR< 100 mW) is connected between this pin and GNDP Card presence pin active (card present) when CRD_PRES = Low. A built−in debounce timer of about 8 ms is activated when a card is inserted. Card presence pin active (card present) when CRD_PRES = High. A built−in debounce timer of about 8 ms is activated when a card is inserted. http://onsemi.com 3 NCN6024 PIN FUNCTION AND DESCRIPTION Pin # 11 Name CRD_I/O Type Input/ Output Input/ Output Input/ Output GND Output Output Power Description This pin handles the connection to the serial I/O (C7) of the card connector. A bi−directional level translator adapts the serial I/O signal between the card and the micro controller. A 13 kW (typical) pullup resistor to CRD_VCC provides a High impedance state for the smart card I/O link. This pin handles the connection to the chip card’s serial auxiliary AUX2 I/O pin (C8). A bi−directional level translator adapts the serial I/O signal between the card and the micro controller. A 13 kW (typical) pullup resistor to CRD_VCC provides a High impedance state for the smart card C8 pin. This pin handles the connection to the chip card’s serial auxiliary AUX1 I/O pin (C4). A bi−directional level translator adapts the serial I/O signal between the card and the micro controller. An 13 kW (typical) pullup resistor to CRD_VCC provides a High impedance state for the smart card C4 pin. Card Ground This pin is connected to the CLOCK card connector’s pin (Chip card’s pin C3). The Clock signal comes from the CLKIN input through clock dividers and level shifter. This pin is connected to the chip card’s RESET pin (C2) through the card connector. A level translator adapts the external Reset (RSTIN) signal to the smart card. This pin is connected to the smart card power supply pin. An internal DC/DC converter is programmable using the pin 5V/3V to supply either 5 V or 3 V output voltage. An external distributed ceramic capacitor ranging from 320 nF to 500 nF recommended must be connected across CRD_VCC and CRD_GND. This set of capacitor (if distributed) must be low ESR (< 100 mW). Power−on reset threshold adjustment input pin for changing the reset threshold due to an external resistor power divider. Needs to be connected to ground when unused. Command VCC pin. Activation sequence Enable/Disable pin (active Low). The activation sequence is enabled by toggling CMDVCC High to Low and when a card is present. This Reset input connected to the host and referred to VDD (microcontroller side), is connected to the smart card Reset pin through the internal level shifter which translates the level according to the CRD_VCC programmed value. This pin is connected to the system controller power supply. It configures the level shifter input stage to accept the signals coming from the controller. A 0.1 mF capacitor shall be used to bypass the power supply voltage. When VDD is below 2.35 V typical the card pins are disabled. Ground The interrupt request is activated LOW on this pin. This is enabled when a card is present and the card presence is detected by CRD_PRES or CRD_PRES pins. Similarly an interrupt is generated when CRD_VCC is overloaded. 20 kW typical integrated pullup resistor to VDD. Clock Input for External Clock Unconnected Input/ Output Input/ Output Input/ Output This pin is connected to an external micro−controller. A bi−directional level translator adapts the serial I/O signal between the smart card and the external controller. A built−in constant 13 kW (typical) resistor provides a high impedance state. This pin is connected to an external micro−controller. A bi−directional level translator adapts the serial C4 signal between the smart card and the external controller. A built−in constant 13 kW (typical) resistor provides a high impedance state. This pin is connected to an external micro−controller. A bi−directional level translator adapts the serial C8 signal between the smart card and the external controller. A built−in constant 13 kW (typical) resistor provides a high impedance state. 12 CRD_AUX2 13 CRD_AUX1 14 15 16 17 CRD_GND CRD_CLK CRD_RST CRD_VCC 18 19 20 PORADJ CMDVCC RSTIN Input Input Input 21 VDD Power 22 23 GND INT GND Output 24 25 26 CLKIN NC I/Ouc Input 27 AUX1uc 28 AUX2uc http://onsemi.com 4 NCN6024 ATTRIBUTES Characteristics ESD protection Human Body Model (HBM) (Note 1) Card Pins (Card Interface Pins 9 − 17) All Other Pins Machine Model (MM) Card Pins (Card Interface Pins 9 − 17) All Other Pins Moisture sensitivity (Note 2) SOIC−28 and TSSOP−28 Flammability Rating Oxygen Index: 28 to 34 Values 8 kV 2 kV 400 V 150 V Level 1 UL 94 V−0 @ 0.125 in Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch−up Test 1. Human Body Model (HBM), R = 1500 W, C = 100 pF. 2. For additional information, see Application Note AND8003/D. MAXIMUM RATINGS (Note 3) Rating DC/DC Converter Power Supply Voltage Power Supply from Microcontroller Side External Card Power Supply Charge Pump Output Digital Input Pins Digital Output Pins (I/Ouc, AUX1uc, AUX2uc, INT) Smart Card Output Pins Thermal Resistance Junction−to−Air Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range SOIC−28 TSSOP−28 Symbol VDDP VDD CRD_VCC VUP Vin Vout Vout RqJA TA TJ TJmax Tstg Value −0.3 v VDDP v 5.5 −0.3 v VDD v 5.5 −0.3 v CRD_VCC v 5.5 −0.3 v VUP v 5.5 −0.3 v Vin v VDD −0.3 v Vout v VDD −0.3 v Vout v CRD_VCC 75 76 −40 to +85 −40 to +125 +125 −65 to + 150 V V V °C/W °C °C °C °C Unit V V V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25°C http://onsemi.com 5 NCN6024 POWER SUPPLY SECTION (VDD = 3.3 V; VDDP = 5 V; Tamb = 25°C; FCLKIN = 10 MHz) Pin 6 Symbol VDDP Rating DC/DC Converter Power Supply, CRD_VCC = 3V and 5V, |ICC| v 65 mA |ICC| v 15 mA (Note 4) Inactive Mode DC Operating Supply Current, FCLKIN = 10 MHz, CoutCRD_CLK = 33 pF, ⎢ICRD_VCC⎢ = 0 DC Operating Supply Current, CRD_VCC = 5 V, ICRD_VCC = 65 mA CRD_VCC = 3 V, ICRD_VCC = 65 mA Operating Voltage Inactive Mode 0 Standby Current Operating Current − FCLK_IN = 10 MHz, CoutCRD_CLK = 33 pF, ⎢ICRD_VCC⎢ = 0 Undervoltage Lockout (UVLO), No External Resistor at Pin PORADJ (Connected to GND), Falling VDD Level UVLO Hysteresis, No External Resistor at Pin PORADJ (Connected to GND) Min 4.5 3.0 − − Typ 5.0 − − Max 5.5 5.5 0.3 5.0 Unit V 6 6 6 IDDP IDDP IDDP mA mA mA − 2.7 − − 2.25 50 − − − − 2.35 100 200 200 5.5 0.6 1 2.45 150 21 21 21 21 21 VDD IVDD IVDD UVLOVDD UVLOHys V mA mA V mV PORADJ PIN 18 18 18 18 VPORth+ VPORth− VPORHys tPOR External Rising Threshold Voltage on VDD for Power On Reset − Pin PORADJ External Falling Threshold voltage on VDD for Power On Reset − Pin PORADJ Hysteresis on VPORth (pin PORADJ) Width of Power−On Reset Pulse (Note 5) No External Resistor on PORADJ External Resistor on PORADJ Low Level Input Leakage Current, VIL CRD_IO and CRD_IO −> IOuc (Falling Edge) (Note 5) Active pull−up pulse width buffers I/O, AUX1 & AUX2 (Note 5) CRD_PRES, CRD_PRES Card Detection Digital Filter Delay: (Note 5) Card Insertion Card Extraction CRD_PRES, CRD_PRES Card Presence Voltage High Level Card Presence Voltage Low Level 2.15 0.30 − − 0.75 x CRD_VCC 0 − − 8.0 − − − − − − − − − − 11 − − CRD_VCC+0.3 0.80 600 10 CRD_VCC+0.1 0.30 1.2 0.1 16 200 200 V V mA mA V V ms ms kW ns ns ms 25 25 0.7 x VDD −0.3 50 50 150 150 VDD + 0.3 0.3 x VDD V − 0.9 x CRD_VCC 0 0 CRD_VCC −0.4 45 − − 0.2 − − − − − − − − − 20 CRD_VCC +0.2 0.4 CRD_VCC 55 16 16 − MHz V V V V % ns ns V/ns Min 0.9 x CRD_VCC − 0 CRD_VCC − 0.4 − − − Typ − − − − − − − Max CRD_VCC 0.20 0.4 CRD_VCC 100 100 2 Unit V V V V ns ns ms http://onsemi.com 8 NCN6024 SMART CARD INTERFACE SECTION, CRD_IO, CRD_AUX1, CRD_AUX2, CRD_CLK, CRD_RST, CRD_PRES, CRD_PRES (VDD = 3.3 V; VDDP = 5 V; Tamb = 25°C; FCLKIN = 10 MHz) Pin 9, 10 Symbol |IIH| |IIL| Rating CRD_PRES, CRD_PRES Low level input leakage current, VIH = VDD CRD_PRES CRD_PRES High level input leakage current, VIL = 0 V CRD_PRES CRD_PRES 5 − − − 30 30 − Min Typ Max Unit mA 5 10 1 1 10 11 15 70 20 220 100 − ms mA mA mA ms ms °C 5 8 − − − − − 150 9, 10 11, 12, 13, 16 15 16 Tdebounce Debounce Time CRD_PRES and CRD_PRES (Note 5) ICRD_IO CRD_IO, CRD_AUX1, CRD_AUX2 Current Limitation ICRD_CLK CRD_CLK Current Limitation ICRD_RST CRD_RST Current Limitation tact tdeact Temp SD Activation Time (Note 5) Deactivation Time (Note 5) Shutdown Temperature NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. POWER SUPPLY The NCN6024 smart card interface has two power supplies: VDD and VDDP. VDD is usually common to the system controller and the interface. The applied VDD range can go from 2.7 V up to 5.5 V. If VDD goes below 2.35 V typical (UVLOVDD) a power-down sequence is automatically performed. In that case the interrupt (INT) pin is set Low. A built−in charge−pump−based DC/DC converter followed by a Low Drop−Out (LDO) regulator is used to provide the 3 V or 5 V power supply voltage (CRD_VCC) to the card. VDDP is the converter’s input voltage for which 2 voltage ranges can be considered: 3.0 V v VDDP v 5.5 V with ICC v 15 mA and 4.5 V v VDDP v 5.5 V with ICC v 65 mA. VUP is the charge−pump converter’s output. It is connected to the LDO input. A reservoir capacitor of 100 nF is connected to VUP. CRD_VCC is the LDO output. Even if the converter can operate with a single output reservoir capacitor as low as 100 nF at CRD_VCC, it is recommended to use a capacitor of at least 320 nF in order to satisfy optimally the datasheet specifications (100 nF + 220 nF or 330 nF or 100 nF + 330 nF or 470 nF). To minimize dI/dt effects, the fly capacitor (100 nF) and the reservoir capacitors VUP and CRD_VCC have to be connected as close as possible to the corresponding device’s pin and feature very low ESR values (lower than 50 mW). The fly capacitor is connected between C1 and C2. The decoupling capacitors on VDD and VDDP respectively 100 nF and 10 mF have also to be connected close to the respective IC pins. The CRD_VCC pin can source up to 65 mA continuously over the VDDP range (5 V ± 10%), the absolute maximum current being internally limited below 150 mA (Typical at 110 mA). CRD_VCC can stay in the range 4.6 V – 5.30 V during current transient up to 200 mA (peak current) over less than 400 ns of current pulse duration such as the charge transient is lower than 40 nAs. There’s no specific sequence for applying VDD or VDDP. They can be applied to the interface in any sequence. After powering the device INT remains Low until a card is inserted. SUPPLY VOLTAGE MONITORING The supply voltage monitoring block includes the Power On Reset (POR) circuitry and the under voltage lockout (UVLO) detection (VDD voltage dropout detection). PORADJ pin allows the user, according to the considered application, to adjust the VDD UVLO threshold. If not used PORADJ pin is connected to Ground. The input supply voltage is continuously monitored to prevent under voltage operation. At power up, the system initializes the internal logic during POR timing and no further signal can be provided or supported during this period. Such initialization takes place when the input voltage rises between 2 V to 2.6 V about typical. The system is ready to operate when the input voltage has reached the minimum 2.7 V. Considering this, the NCN6024 will detect an Under-Voltage situation when the input supply voltage will drop below 2.35 V typical. When VDD goes down below the UVLO falling threshold a deactivation sequence is performed. The device is inactive during power-on and power-off of the VDD supply (8 ms reset pulse). PORADJ pin is used to modify the UVLO threshold according to the below relationship considering an external http://onsemi.com 9 NCN6024 resistor divider R1 / R2 (see block diagram Figure 1) and the PORADJ internal 5 mA pull−down current source Ipd : UVLO + R1 ) R2 V POR ) R1 Ipd R2 If PORADJ is connected to Ground the VDD UVLO threshold (VDD falling) is typically 2.35 V. In some cases it can be interesting to adjust this threshold at a higher value and by the way increase the VDD supply dropout detection level which enables a deactivation sequence if the VDD voltage is too low. For example, there’re microcontrollers for which the minimum supply voltage insuring a correct operating is higher than 2.55 V, increasing UVLOVDD (VDD falling) is consequently necessary. Considering for instance a resistor bridge with R1 = 56 kW, R2 = 42 kW and VPOR- = 1.18 V typical the VDD dropout detection level can be increased up to: UVLO + 59k ) 42k V POR− ) 56k 42k 5 mA + 3.03 V channels are identical. The first side of the bidirectional level shifter dropping Low (falling edge) becomes the driver side until the level shifter enters again in the idle state pulling High CRD_IO and I/Ouc. Passive 11 kW pull-up resistors have been internally integrated on each terminal of the bidirectional channel. In addition with these pull-up resistors, an active pull-up circuit provides a fast charge of the stray capacitance. The current to and from the card I/O lines is limited internally to 15 mA and the maximum frequency on these lines is 1 MHz. STANDBY MODE The minimum dropout detection voltage should be higher than 2 V. The maximum detection level may be up to VDD. CLOCK DIVIDER: After a Power-on reset, the circuit enters the standby mode. A minimum number of circuits are active while waiting for the microcontroller to start a session: • All card contacts are inactive • Pins I/Ouc, AUX1uc and AUX2uc are in the high-impedance state (11 kW pull−up resistor to VDD) • Card pins are inactive and pulled Low • Supply Voltage monitoring is active • The internal DC/DC converter oscillator is running. POWER-UP The input clock can be divided by 1/1, 1/2, 1/4, or 1/8, depending upon the specific application, prior to be applied to the smart card driver. These division ratios are programmed using pins CLKDIV1 and CLKDIV2 (see Table 1). The input clock is provided externally to pin CLKIN. Table 1. Clock Frequency Programming CLKDIV1 0 0 1 1 CLKDIV2 0 1 0 1 FCRD_CLK CLKIN/8 CKLKIN / 4 CLKIN CLKIN / 2 In the standby mode the microcontroller can check the presence of a card using the signals INT and CMDVCC as shown in Table 2: Table 2. Card Presence State INT HIGH LOW CMDVCC HIGH HIGH State Card present Card not present The clock input stage (CLKIN) can handle a 27 MHz maximum frequency signal (considering a division ratio w 2). Of course, the ratio must be defined by the user to cope with Smart Card considered in a given application In order to avoid any duty cycle out of the 45% / 55% range specification, the divider is synchronized by the last flip flop, thus yielding a constant 50% duty cycle, whatever be the divider ratio 1/2, 1/4 or 1/8. On the other hand, the output signal Duty Cycle cannot be guaranteed 50% if the division ratio is 1 and if the input Duty Cycle signal is not within the 46 − 56% range at the CLKIN input. When the signal applied to CLKIN is coming from the external controller, the clock will be applied to the card under the control of the microcontroller or similar device after the activation sequence has been completed. DATA I/O, AUX1 and AUX2 LEVEL SHIFTERS The three bidirectional level shifters I/O, AUX1 and AUX2 adapt the voltage difference that might exist between the micro-controller and the smart card. These three If a card is detected present (CRD_PRES or CRD_PRES active) the controller can start a card session by pulling CMDVCC Low. Card activation is run (t0, Figure 5). This Power−Up Sequence makes sure all the card related signals are LOW during the CRD_VCC positive going slope. These lines are validated when CRD_VCC is stable and above the minimum voltage specified. When the CRD_VCC voltage reaches the programmed value (3.0 V or 5.0 V), the circuit activates the card signals according to the following sequence: • CRD_VCC is powered-up at its nominal value (t1) • I/O, AUX1 and AUX2 lines are activated (t2) • Then Clock channel is activated and the clock signal is applied to the card (t3) • Finally the Reset level shifter is enabled (t4) The clock can also be applied to the card using a RSTIN mode allowing controlling the clock starting by setting RSTIN Low (Figure 4). Before running the activation sequence, that is before setting Low CMDVCC RSTIN is set High. In these initial conditions CRD_CLK starts when RSTIN is pulled Low. This allows a precise count of clock pulses before toggling CRD_RST High for ATR (Answer To Reset) request. http://onsemi.com 10 NCN6024 The internal activation sequence activates the different channels according to a specific hardware built-it sequencing internally defined but at the end the actual activation sequencing is the responsibility of the application software and can be redefined by the micro-controller to comply with the different standards and the different ways the standards manage this activation (for example light differences exist between the EMV and the ISO7816 standards). Figure 4. Activation Sequence − RSTIN mode (RSTIN Starting High) Figure 5. Activation Sequence − Normal Mode http://onsemi.com 11 NCN6024 POWER-DOWN When the communication session is completed the NCN6024 runs a deactivation sequence by setting High CMDVCC. The below power down sequence is executed: • CRD_RST is forced to Low CMDVCC CRD_RST CRD_CLK CRD_IO CRD_VCC • CRD_CLK is set Low 12 ms after CRD_RST. • CRD_IO, CRD_AUX1 and CRD_AUX2 are pulled Low • Finally CRD_VCC supply can be shut-off. tdeact Figure 6. Deactivation Sequence FAULT DETECTION In order to protect both the interface and the external smart card, the NCN6024 provides security features to prevent failures or damages as depicted here after. • Card extraction detection • VDD under voltage detection • Short-circuit or overload on CRD_VCC CRD_PRES INT • Card pin current limitation: in the case of a short circuit • DC/DC operation: the internal circuit continuously • • to ground. No feedback is provided to the external MPU. senses the CRD_VCC voltage (in the case of either over or under voltage situation). DC/DC operation: under-voltage detection on VDDP or overload on VUP Overheating CMDVCC CRD_VCC Debounce Debounce Powerdown Resulting of Card Extraction Powerdown Caused by Short−Circuit Figure 7. Fault Detection and Interrupt Management Interrupt Pin Management: A card session is opened by toggling CMDVCC High to Low. Before a card session, CMDVCC is supposed to be in a High position. INT is Low if no card is present in the card connector (Normally open or normally closed type). INT is High if a card is present. If a card is inserted (INT = High) and if VDD drops below the UVLO threshold then INT pin drops Low immediately. It turns back High when VDD increases again over the UVLO limit (including hysteresis), a card being still present. During a card session, CMDVCC is Low and INT pin goes Low when a fault is detected. In that case a deactivation is immediately and automatically performed (see Figure 6). When the microcontroller resets CMDVCC to High it can sense the INT level again after having got completed the deactivation. As illustrated by Figure 7 the device has a debounce timer of 8 ms typical duration. When a card is inserted, output INT goes High only at the end of the debounce time. When the card is removed a deactivation sequence is automatically and immediately performed and INT goes Low. ESD PROTECTION The NCN6024 includes devices to protect the pins against the ESD spikes voltages. To cope with the different ESD http://onsemi.com 12 NCN6024 voltages developed across these pins, the built in structures have been designed to handle either 2 kV, when related to the micro controller side, or 8 kV when connected with the external contacts (HBM model). Practically, the CRD_RST, CRD_CLK, CRD_IO, CRD_AUX1, CRD_AUX2, CRD_PRES and CRD_PRES pins can sustain 8 kV. The CRD_VCC pin has the same ESD protection and can source up to 65 mA continuously, the absolute maximum current being internally limited with a max at 150 mA. The CRD_VCC current limit depends on VDDP and CRD_VCC. VDD +3.3V XTAL1 XTAL2 CLKDIV1 CLKDIV2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NCN6024 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AUX2uc AUX1uc I/Ouc NC CLKIN INT GND VDD RSTIN CMDVCC PORADJ CRD_VCC CRD_RST CRD_CLK R1 R2 100 nF 3.3 V Microcontroller + 100 nF VDDP +5V or +3.3V 100 nF 5V/3V 10 mF GNDP C2 VDDP 100 nF C1 VUP CRD_PRES CRD_PRES CRD_I/O CRD_AUX2 100 kW VDD +3.3V CRD_AUX1 CRD_GND Optional R1/R2 resistor divider − if not used PORADJ has to be connected to Ground 330 nF 100 nF 1 2 3 4 Vcc RST CLK C4 GND Vpp I/O C8 5 6 7 8 DET Normally Open SMART CARD Figure 8. Application Schematic ORDERING INFORMATION Device NCN6024DWR2G* NCN6024DTBR2G Package SOIC−28 (Pb−Free) TSSOP−28 (Pb−Free) Shipping† 1000 / Tape & Reel 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *Consult Sales Office http://onsemi.com 13 NCN6024 PACKAGE DIMENSIONS SOIC−28 WB CASE 751F−05 ISSUE H −X− 28 D 15 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBER PR5OTRUSION SHALL NOT BE 0.13 TOTATL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E G H L M MILLIMETERS MIN MAX 2.35 2.65 0.13 0.29 0.35 0.49 0.23 0.32 17.80 18.05 7.40 7.60 1.27 BSC 10.05 10.55 0.41 0.90 0_ 8_ E −Y− 1 PIN 1 IDENT 14 H 0.25 M Y M A 0.10 G B 0.025 M L C M A1 Y S −T− SEATING PLANE TX S SOLDERING FOOTPRINT* 11.00 28X 8X 1.30 1 28 0.52 28X 1.27 PITCH 14 15 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 14 NCN6024 PACKAGE DIMENSIONS 28 LEAD TSSOP CASE 948AA−01 ISSUE O 28 e 15 B PIN ONE LOCATION 2X E1 E DETAIL A NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 MM TOTAL IN EXCESS OF THE “b” DIMENSION AT MAXIMUM MATERIAL CONDITION. 4. DATUMS A AND B TO BE DETERMINED AT DATUM PLANE H. DIM A A1 A2 b b1 c c1 D E E1 e L L1 R R1 S 01 02 03 MILLIMETERS MIN MAX −−− 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.19 0.25 0.09 0.20 0.09 0.16 9.60 9.80 6.40 BSC 4.30 4.50 0.65 BSC 0.45 0.75 1.00 REF 0.09 −−− 0.09 −−− 0.20 −−− 0_ 8_ 12 _REF 12 _REF 0.20 C B A 0.05 0.10 C SEATING PLANE C c SECTION A−A ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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