NCN8026A
Compact Low Power Smart
Card Interface IC
The NCN8026A is a compact and cost−effective single SIM &
smart card interface IC. It can be used with 1.8 V, 3 V and 5 V IC
cards. The card VCC supply is provided by a built−in very low drop
out and low noise Regulator. The NCN8026A offers enhanced
performances with low VCC output ripple under load−transient
conditions, very low shutdown current and 1.8 V−to−5 V logic
compatibility.
This device is fully compatible with the ISO 7816−3, EMV 4.2,
UICC and related standards including NDS and other STB standards
(Nagravision, Irdeto, Conax ..). It satisfies the requirements specifying
conditional access into Set−Top−Boxes (STB) or Conditional Access
Modules (CAM).
This smart card interface IC is available in a QFN−24 package
providing all the industry−standard features usually required for STB
smart card interface.
Features
• Single IC Card Interface
• Fully Compatible with ISO 7816−3, EMV4.2, UICC and Related
•
•
•
•
•
•
•
•
•
•
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MARKING
DIAGRAMS
QFN24
MN SUFFIX
CASE 485L
NCN
8026A
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
Standards Including NDS and Other STB Standards (Nagravision,
ORDERING INFORMATION
Irdeto, Conax...)
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
Three Bidirectional Buffered I/O Level Shifters (C4, C7 and C8)
1.8 V, 3.0 V or 5.0 V $ 5 % Regulated Card Power Supply Such as
ICC ≤ 70 mA with Low VCC Ripple
Regulator Power Supply: VDDP = 2.7 V to 5.5 V (@ 1.8 V),
3.0 V to 5.5 V (@ 3.0 V) and 4.85 V to 5.5 V (@ 5.0 V)
Independent Power Supply range on Controller
• Interrupt Signal INT for Card Presence and Faults
Interface such as VDD = 1.6 V to 5.5 V
• Chip Select Pin (CS) for Dual Card Operating
Handles Class A, B and C Smart Cards
• External Under−Voltage Lockout Threshold
Short Circuit Protection on all Card Pins
Adjustment on VDD (PORADJ Pin)
Support up to 27 MHz input Clock with Internal
• Available in One Package Formats: QFN−24
Division Ratio 1/1, 1/2, 1/4 and 1/8 through CLKDIV1
• These are Pb−Free Devices
and CLKDIV2
Typical Application
HBM ESD Protection on Card Pins up to +8 kV
• Pay TV, Set Top Box Decoder with Conditional Access
(Human Body Model)
and Pay−per−View
Activation / Deactivation Sequences (ISO7816
•
Conditional Access Module (CAM / CAS)
Sequencer)
• SIM card interface applications (UICC / USIM)
Fault Protection Mechanisms Enabling Automatic
• Point Of Sales and Transaction Terminals
Device Deactivation in Case of Overload, Overheating,
Card Take−off or Power Supply Drop−out (OCP, OTP,
• Electronic Payment and Identification
UVP)
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 7
1
Publication Order Number:
NCN8026A/D
NCN8026A
VDDP
10 uF
VDD
100 nF
VDDP
100 nF
VDD
INT
VDD
R1
SMART CARD
PRES
PORADJ
R2
DET
PRES
NCN8026A
CONTROL
VSEL0
CS
100 nF
220 nF
CVCC
CCLK
CLKDIV1
CAUX1
CLKDIV2
CAUX2
5 GND
1
2
3
CRST
4
Vcc
GND
RST
Vpp
CLK
C4
I/O
C8
CI/O
CLKIN
RSTIN
R3
I/Ouc
GND
AUX1uc
AUX2uc
GND
GND
GND
VSEL1
CLKDIV2
CLKDIV1
AUX2uc
AUX1uc
I/Ouc
Figure 1. Typical Smart Card Interface Application
24
23
22
21
20
19
18 CLKIN
VSEL0
1
CS
2
NCN8026A
VDDP
3
25
16 GND
PRES
4
Exposed Pad
15 VDD
PRES
5
GND
CI/O
6
17 INT
14 RSTIN
10
11
12
CVCC
PORADJ
9
CRST
8
CCLK
7
CAUX1
13 CMDVCC
CAUX2
DATA PORT
Host Controller
CMDVCC
VSEL1
Figure 2. NCN8026A − QFN−24 Pinout
(Top View)
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2
DET
GND
GND
6
7
8
NCN8026A
VDD
15
16
GND
Supply Voltage
Monitoring
VDDP
3
PORADJ
12
VSEL0
1
VSEL1
24
1.8 V / 3 V / 5 V LDO
13
INT
17
CS
2
CLKDIV1
22
CLKDIV2
23
CLKIN
18
RSTIN
14
I/Ouc
19
AUX1uc
20
AUX2uc
21
Control Logic
and
Fault Detection
Clock Divider
ISO7816
Sequencer
Card
Detection
Card Pin Level Shifters & Drivers
CMDVCC
11 CVCC
4
PRES
5
PRES
9
CCLK
10 CRST
6
CIO
8
CAUX1
7
CAUX2
25 GND
Figure 3. NCN8026A Block Diagram (QFN−24 Pin Numbering)
PIN FUNCTION AND DESCRIPTION
Pin
(QFN24)
Name
Type
1
VSEL0
Input
Allows selecting card VCC power supply voltage mode (5V/3V or 1.8V/3V)
VSEL0 = Low; CVCC = 5 V when VSEL1 = High or 3 V when VSEL1 = Low
VSEL0 = High; CVCC = 1.8 V when VSEL1 = High or 3 V when VSEL1 = Low
2
CS
Input
When CS is Low, the corresponding chip is selected and the control and signal pins are configured
normally.
When CS is set High, CMDVCC, VSEL0, VSEL1, CLKDIV1, CLKDIV2 and RSTIN are latched. IOuc,
AUX1uc, and AUX2uc are set to high−impedance pull−up mode and data transmission to or from the
smart card is no longer allowed. VCC card power supply and card clock are maintained active if the
part is active.
3
VDDP
Power
4
PRES
Input
Card presence pin active (card present) when PRES = Low. A built−in debounce timer of about 8 ms
is activated when a card is inserted. Convenient for Normally Open (NO) Smart card connector. This
pin can be left open when not in use.
5
PRES
Input
Card presence pin active (card present) when PRES = High. A built−in debounce timer of about 8 ms
is activated when a card is inserted. Convenient for Normally Closed (NC) smart card connector. This
pin can be left open when not in use.
Description
Regulator power supply. When VDDP is below 2.5 V typical the card pins are disabled.
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3
NCN8026A
PIN FUNCTION AND DESCRIPTION
Pin
(QFN24)
Name
Type
Description
6
CI/O
Input/
Output
This pin handles the connection to the serial I/O (C7) of the card connector. A bi−directional level
translator adapts the serial I/O signal between the card and the micro controller. A 11 kW (typical) pull
up resistor to CVCC provides a High impedance state for the smart card I/O link.
7
CAUX2
Input/
Output
This pin handles the connection to the chip card’s serial auxiliary AUX2 I/O pin (C8). A bi−directional
level translator adapts the serial I/O signal between the card and the micro controller. A 11 kW
(typical) pull up resistor to CVCC provides a High impedance state for the smart card C8 pin.
8
CAUX1
Input/
Output
This pin handles the connection to the chip card’s serial auxiliary AUX1 I/O pin (C4). A bi−directional
level translator adapts the serial I/O signal between the card and the micro controller. A 11 kW
(typical) pull up resistor to CVCC provides a High impedance state for the smart card C4 pin.
9
CCLK
Output
This pin is connected to the CLOCK card connector’s pin (Chip card’s pin C3). The Clock signal
comes from the CLKIN input through clock dividers and level shifter.
10
CRST
Output
This pin is connected to the chip card’s RESET pin (C2) through the card connector. A level
translator adapts the external Reset (RSTIN) signal to the smart card.
11
CVCC
Power
Output
This pin is connected to the smart card power supply pin (C1). An internal low dropout regulator is
programmable using the pins VSEL0 and VSEL1 to supply either 5 V or 3 V or 1.8 V output voltage.
An external distributed ceramic capacitor ranging from 80 nF to 1.2 mF recommended must be
connected across CVCC and CGND. This set of capacitor (if distributed) must be low ESR (<
100 mW).
12
PORADJ
Input
Power−on reset threshold adjustment input pin for changing the reset threshold (VDD UVLO
threshold) thanks to an external resistor power divider. Needs to be connected to ground when
unused.
13
CMDVCC
Input
Command VCC pin. Activation sequence Enable/Disable pin (active Low). The activation sequence is
enabled by toggling CMDVCC High to Low and when a card is present. When CMDVCC = High, the
CVCC output is pulled low and the internal LDO is disabled unless the device has been latched by
the CS pin.
14
RSTIN
Input
This Reset input connected to the host and referred to VDD (microcontroller side), is connected to
the smart card Reset pin through the internal level shifter which translates the level according to the
CVCC programmed value.
15
VDD
Power
input
This pin is connected to the system controller power supply. It configures the level shifter input stage
to accept the signals coming from the controller. A 0.1 mF decoupling capacitor shall be used. When
VDD is below 1.45 V typical the card pins are disabled.
16
GND
Ground
Ground
17
INT
Output
The interrupt request is activated LOW on this pin. This is enabled when a card is present and the
card presence is detected by PRES or PRES pins. Similarly an interrupt is generated when CVCC is
overloaded. Inverter output (An open−drain output configuration with 50 kW pull−up resistor is
available under request (metal change)).
18
CLKIN
Input
19
I/Ouc
Input /
Output
This pin is connected to an external micro−controller. A bi−directional level translator adapts the
serial I/O signal between the smart card and the external controller. A built−in constant 11 kW
(typical) resistor provides a high impedance state.
20
AUX1uc
Input /
Output
This pin is connected to an external micro−controller. A bi−directional level translator adapts the
serial C4 signal between the smart card and the external controller. A built−in constant 11 kW (typical)
resistor provides a high impedance state.
21
AUX2uc
Input /
Output
This pin is connected to an external micro−controller. A bi−directional level translator adapts the
serial C8 signal between the smart card and the external controller. A built−in constant 11 kW (typical)
resistor provides a high impedance state.
22
CLKDIV1
Input
This pin coupled with CLKDIV2 is used to program the clock frequency division ratio (Table 2).
23
CLKDIV2
Input
This pin coupled with CLKDIV1 is used to program the clock frequency division ratio (Table 2).
24
VSEL1
Input
Allows selecting card VCC power supply voltage.
VSEL0 = Low: CVCC = 5 V when VSEL1 = High or 3 V when VSEL1 = Low.
VSEL0 = High: CVCC = 1.8 V when VSEL1 = High or 3 V when VSEL1 = Low.
25
GND
Ground
Clock Input for External Clock
Regulator Power Supply Ground
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4
NCN8026A
ATTRIBUTES
Characteristics
Values
ESD protection
Human Body Model (HBM) (Note 1)
Card Pins (card interface pins 4−11)
All Other Pins
Machine Model (MM)
Card Pins (card interface pins 4−11)
All Other Pins
8 kV
2 kV
400 V
150 V
Moisture sensitivity (Note 2) QFN−24
Level 1
Flammability Rating Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch−up Test
1. Human Body Model (HBM), R = 1500 W, C = 100 pF.
2. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 3)
Rating
Symbol
Value
Unit
Regulator Power Supply Voltage
VDDP
−0.3 ≤ VDDP ≤ 5.5
V
Power Supply from Microcontroller Side
VDD
−0.3 ≤ VDD ≤ 5.5
V
CVCC
−0.3 ≤ CVCC ≤ 5.5
V
External Card Power Supply
Digital Input Pins
Vin
−0.3 ≤ Vin ≤ VDD
V
Digital Output Pins (I/Ouc, AUX1uc, AUX2uc, INT)
Vout
−0.3 ≤ Vout ≤ VDD
V
Smart card Output Pins
Vout
−0.3 ≤ Vout ≤ CVCC
V
RqJA
90
°C/W
Operating Ambient Temperature Range
TA
−40 to +85
°C
Operating Junction Temperature Range
TJ
−40 to +125
°C
TJmax
+125
°C
Tstg
−65 to + 150
°C
Thermal Resistance Junction−to−Air
QFN−24
Maximum Junction Temperature
Storage Temperature Range
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25°C.
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5
NCN8026A
POWER SUPPLY SECTION (VDD = 3.3 V; VDDP = 5 V; Tamb = 25°C; FCLKIN = 5 MHz)
Symbol
VDDP
Rating
Regulator Power Supply,
5.0 V Mode,
|ICC| ≤ 70 mA
3.0 V Mode,
|ICC| ≤ 70 mA
1.8 V Mode,
|ICC| ≤ 70 mA
Min
Typ
Max
4.75
3.0
2.7
5.0
3.3/5.0
3.3/5.0
5.5
5.5
5.5
Unit
V
IDDP
Inactive mode (CMDVCC = High, CS = Low)
−
2.0
3.0
mA
IDDP
Active Mode, FCLKIN = 0 MHz, CoutCCLK = 33 pF, |ICVCC| = 0
(CMDVCC = Low, CS = Low)
−
−
4.0
mA
IDDP
DC Operating supply current, FCLKIN = 5 MHz,
CoutCCLK = 33 pF, |ICVCC| = 0 (CMDVCC = Low, CS = Low)
−
−
5.0
mA
IDDP
DC Operating supply current with FCLKIN = 5 MHz,
ICVCC = 70 mA
−
−
76
mA
VDD
Operating Voltage
1.6
−
5.5
V
IVDD
Inactive mode − standby current (CMDVCC = High)
−
−
1.0
mA
IVDD
Operating Current − FCLKIN = 0 MHz , CoutCCLK = 33 pF |ICVCC| = 0
(CMDVCC = Low)
−
−
1.0
mA
IVDD
Operating Current − FCLKIN = 5 MHz , CoutCCLK = 33 pF |ICVCC| = 0
(CMDVCC = Low)
−
−
100
mA
1.35
1.45
1.55
V
UVLOVDD
Under Voltage Lock−Out (UVLO), no external resistor at pin PORADJ
(connected to GND), falling VDD level
UVLOHys
UVLO Hysteresis, no external resistor at pin PORADJ (Connected to GND) (Note 4)
50
100
150
mV
Under Voltage LockOut (UVLO) falling VDDP level
2.4
2.5
2.6
V
VDDP UVLO Hysteresis (Note 4)
50
100
150
mV
UVLOVDDP
UVLOHys
PORADJ pin
VPORth+
External Rising threshold voltage on VDD for Power On Reset − pin PORADJ
1.19
1.24
1.26
V
VPORth−
External Falling threshold voltage on VDD for Power On Reset − pin PORADJ
1.17
1.19
1.22
V
VPORHys
Hysteresis on VPORth (pin PORADJ) (Note 4)
30
80
100
mV
Width of Power−On Reset pulse (Note 4)
No external resistor on PORADJ
External resistor on PORADJ
4.0
4.0
8.0
8.0
12
12
ms
ms
tPOR
IIL
Low level input leakage current, VIL < 0.5 V (Pull−down source current)
mA
0.2
Low Dropout Regulator
CCVCC
Output Capacitance on card power supply CVCC (Note 5)
0.08
0.32
1.2
mF
CVCC
Output Card Supply Voltage (including ripple)
1.8 V CVCC mode @ ICC ≤ 70 mA
3.0 V CVCC mode @ ICC ≤ 70 mA
5.0 V CVCC mode @ ICC ≤ 70 mA with 4.75 V ≤ VDDP ≤ 5.5 V
1.68
2.85
4.65
1.80
3.00
5.00
1.90
3.15
5.25
V
V
V
1.66
1.80
1.90
V
2.70
3.00
3.30
V
4.60
5.00
5.30
V
CVCC
ICVCC
Current pulses 7 nAs (t < 400 ns & |ICC| < 40 mA peak) (Note 4)
1.8 V mode / Ripple ≤ 150 mV (2.7 V ≤ VDDP ≤ 5.5 V)
Current pulses 40 nAs (t < 400 ns & |ICC| < 200 mA peak) (Note 4)
3.0 V mode / Ripple ≤ 150 mV (2.9 V ≤ VDDP ≤ 5.5 V)
Current pulses 40 nAs (t < 400 ns & |ICC| < 200 mA peak) (Note 4)
5.0 V mode / Ripple ≤ 150 mV (4.85 V ≤ VDDP ≤ 5.5 V)
Card Supply Current
@ 1.8 V Mode
@ 3.0 V Mode
@ 5.0 V Mode
mA
70
70
70
ICVCC_SC
Short −Circuit Current − CVCC shorted to ground
−
120
150
mA
DVCVCC
Output Card Supply Voltage Ripple peak−to−peak − fripple = 100 Hz to 200 MHz (load
transient frequency with 65 mA peak current and 50% Duty Cycle) (Note 4)
−
−
150
mV
CVCCSR
Slew Rate on CVCC turn−on / turn−off (Note 4)
−
−
0.22
V/ms
4. Guaranteed by design and characterization.
5. These values take into account the tolerance of the cms capacitor used. CMS capacitor very low ESR (< 100 mW, X5R / X7R).
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6
NCN8026A
HOST INTERFACE SECTION CLKIN, RSTIN, I/Ouc, AUX1uc, AUX2uc, CLKDIV1, CLKDIV2, CMDVCC, VSEL0, VSEL1, CS
(VDD = 3.3 V; VDDP = 5 V; Tamb = 25°C; FCLKIN = 5 MHz)
Symbol
FCLKIN
Rating
Clock frequency on pin CLKIN (Note 6)
Min
Typ
Max
Unit
−
−
27
MHz
VIL
Input Voltage level Low: CLKIN, RSTIN, CLKDIV1, CLKDIV2, CMDVCC, VSEL0,
VSEL1, CS
−0.3
−
0.3 x VDD
V
VIH
Input Voltage level High: CLKIN, RSTIN, CLKDIV1, CLKDIV2, CMDVCC, VSEL0,
VSEL1, CS
0.7 x VDD
−
VDD + 0.3
V
|IIL|
CLKDIV1, CLKDIV2, CMDVCC, RSTIN, CLKIN, VSEL0, VSEL1, CS Low Level
Input Leakage Current, VIL = 0 V
−
−
1.0
mA
|IIH|
CLKDIV1, CLKDIV2, CMDVCC, RSTIN, CLKIN, VSEL0, VSEL1, CS Low Level
Input Leakage Current, VIH = VDD
−
−
1.0
mA
VIL
Input Voltage level Low: I/Ouc, AUX1uc, AUX2uc
−0.3
−
0.5
V
VIH
Input Voltage level High: I/Ouc, AUX1uc, AUX2uc
0.7 x VDD
−
VDD + 0.3
V
|IIL |
I/Ouc, AUX1uc, AUX2uc Low level input leakage current, VIL = 0 V
−
−
600
mA
|IIH|
I/Ouc, AUX1uc, AUX2uc High level input leakage current, VIH = VDD
−
−
10
mA
VOH
I/Ouc, AUX1uc, AUX2uc data channels, @ Cs v 30 pF
High Level Output Voltage (CRD_I/O = CAUX1 = CAUX2 = CVCC)
IOH = 0
IOH = −40 mA for VDD > 2 V (IOH = −20 mA for VDD v 2 V)
0.9 x VDD
0.75 x VDD
−
VDD + 0.1
VDD + 0.1
V
V
0.3
V
1.2
ms
0.1
ms
kW
VOL
tRi/Fi
−
Low Level Output Voltage (CRD_I/O = CAUX1 = CAUX2 = 0 V)
IOL= + 1 mA
0
Input Rising/Falling times (Note 6)
−
−
−
tRo/Fo
−
Output Rising/Falling times (Note 6)
Rpu
I/0uc, AUX1uc, AUX2uc Pull Up Resistor
VOH
Output High Voltage
INT @ IOH = −15 mA (source)
VOL
RINT
8.0
11
16
0.75 x VDD
−
−
Output Low Voltage
INT @ IOL = 2 mA (sink)
0
−
0.30
INT Pull Up Resistor
−
20
−
V
V
6. Guaranteed by design and characterization.
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7
kW
NCN8026A
SMART CARD INTERFACE SECTION CI/O, CAUX1, CAUX2, CCLK, CRST, PRES, PRES (VDD = 3.3 V; VDDP = 5 V; Tamb = 25°C;
FCLKIN = 5 MHz)
Symbol
VOH
VOL
tR
tF
tR/F
td
Rating
Min
Typ
Max
Unit
CRST @ CVCC = 1.8 V, 3.0 V, 5.0 V
Output RESET VOH @ Irst = −200 mA
Output RESET VOL @ Irst = 200 mA
0.9 x CVCC
0
−
−
CVCC
0.20
V
V
Output RESET VOH @ Irst = −20 mA
Output RESET VOL @ Irst = 20 mA
0
CVCC − 0.4
0.4
CVCC
V
V
Output RESET Rise time @ Cout = 100 pF (Note 7)
Output RESET Fall time @ Cout = 100 pF (Note 7)
Output Rise/Fall times @ CVCC = 1.8 V & Cout = 100 pF (Note 7)
RSTIN to CRST delay − Reset enabled (Note 7)
−
−
−
−
−
−
100
100
200
ns
ns
ns
−
−
2
ms
−
−
27
MHz
−
−
CVCC
+0.2
V
V
0.4
CVCC
V
V
CCLK @ CVCC = 1.8 V, 3.0 V or 5.0 V
FCRDCLK
Output Frequency (Note 7)
VOH
VOL
Output CCLK VOH @ Iclk = −200 mA
Output CCLK VOL @ Iclk = 200 mA
0.9 x CVCC
0
FDC
Output CCLK VOH @ Iclk = −70 mA
Output CCLK VOL @ Iclk = 70 mA
0
CVCC − 0.4
Output Duty Cycle (Note 7)
trills
tulsa
SR
Rise & Fall time
Output CCLK Rise time @ Cout = 33 pF (Note 7)
Output CCLK Fall time @ Cout = 33 pF (Note 7)
Slew Rate @ Cout = 33 pF (CVCC = 3.0 V or 5.0 V) (Note 7)
45
−
55
%
−
−
−
−
16
16
ns
ns
0.2
−
−
V/ns
0.7xVCC
1.6
1.8
−
−
−
CVCC + 0.3
CVCC+ 0.3
CVCC + 0.3
V
V
V
−0.30
−0.30
−
−
0.50
0.80
V
V
600
10
mA
mA
CVCC + 0.1
CVCC + 0.1
CVCC + 0.1
0.4
V
V
CAUX1, CAUX2, CI/O @ CVCC = 1.8 V, 3.0 V, 5.0 V
VIH
VIL
Input Voltage High Level
1.8 V Mode
3.0 V Mode
5.0 V Mode
Input Voltage Low Level
1.8 V mode
3.0 V and 5.0 V modes
|IIL|
|IIH|
Low Level Input current VIL = 0 V
High Level Input current VIH = CVCC
VOH
Output VOH
@ IOH = no DC load
@ IOH = −40 mA for CVCC = 3.0 V and 5.0 V
@ IOH = −20 mA for CVCC = 1.8 V
@ IOH ≥ −15 mA
VOL
−
−
0.9xCVCC
0.75xCVCC
0.75xCVCC
0
−
−
−
V
tRi / Fi
tRo / Fo
Output VOL
@ IOL = 1 mA, VIL = 0 V
@ IOL ≥ +15 mA
0
VCC − 0.4
−
−
0.30
VCC
Input Rising/Falling times (Note 7)
−
−
1.2
Output Rising/Falling times / Cout = 80 pF (Note 7)
−
−
0.1
ms
ms
Fbidi
Maximum data rate through bidirectional I/O, AUX1 & AUX2 channels (Note 7)
−
−
1
MHz
RPU
CAUX1, CAUX2, CI/O Pull− Up Resistor
8
11
16
kW
tIO
Propagation delay IOuc −> CI/O and CI/O −> IOuc (falling edge) (Note 7)
−
−
200
ns
tpu
Active pull−up pulse width buffers I/O, AUX1 and AUX2 (Note 7)
−
−
200
ns
Cin
Input Capacitance on data channels (Note 7)
−
−
10
pF
VIH
VIL
PRES, PRES
Card Presence Voltage High Level
Card Presence Voltage Low Level
0.7 x VDD
−0.3
−
−
VDD + 0.3
0.3 x VDD
V
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8
NCN8026A
SMART CARD INTERFACE SECTION CI/O, CAUX1, CAUX2, CCLK, CRST, PRES, PRES (VDD = 3.3 V; VDDP = 5 V; Tamb = 25°C;
FCLKIN = 5 MHz)
Symbol
|IIH|
|IIL|
Tdebounce
Rating
Min
Typ
Max
Unit
mA
PRES, PRES
Low level input leakage current, VIH = VDD
PRES
PRES
High level input leakage current, VIL = 0 V
PRES
PRES
0.2
2.0
1.0
0.2
1.0
2.0
Debounce time PRES and PRES (Note 7)
5
8
12
ms
ICI/O
CI/O, CAUX1, CAUX2 current limitation, CVCC enabled
−
−
15
mA
ICCLK
CCLK current limitation
−
−
70
mA
ICRST
CRST current limitation
−
−
20
mA
Tact
Activation Time (Note 7)
30
−
100
ms
T5
RSTIN time control (Figure 5) (Note 7)
200
240
280
ms
Deactivation Time (Note 7)
30
−
250
ms
Tdeact
7. Guaranteed by design and characterization.
POWER SUPPLY
VSEL1 are usually programmed before activating the smart
card interface that is when CMDVCC is High.
There’s no specific sequence for applying VDD or VDDP.
They can be applied to the interface in any sequence. After
powering the device INT pin remains Low until a card is
inserted.
The NCN8026A smart card interface has two power
supplies: VDD and VDDP.
VDD is common to the system controller and the interface.
The applied VDD range can go from 1.6 V up to 5.5 V. If VDD
goes below 1.45 V typical (UVLOVDD) a power−down
sequence is automatically performed. In that case the
interrupt (INT) pin is set Low.
A Low Drop−Out (LDO) and low noise regulator is used
to provide the 1.8 V, 3 V or 5 V power supply voltage
(CVCC) to the card. VDDP is the LDO’s input voltage.
CVCC is the LDO output. The typical distributed reservoir
output capacitor connected to CVCC is 100 nF + 220 nF. The
capacitor of 100 nF is connected as close as possible to the
CVCC’s pin and the 220 nF one as close as possible to the
card connector C1 pin. Both feature very low ESR values
(lower than 50 mW). The decoupling capacitors on VDD and
VDDP respectively 100 nF and 10 mF + 100 nF have also to
be connected close to the respective IC pins.
The CVCC pin can source up to 70 mA at 1.8 V, 3 V and
5 V continuously over the VDDP range (see corresponding
specification table), the absolute maximum current being
internally limited below 150 mA (Typical at 120 mA).
The card VCC voltage (CVCC) can be programmed with
the pins VSEL0 and VSEL1 and according to the below table:
SUPPLY VOLTAGE MONITORING
The supply voltage monitoring block includes the
Power−On Reset (POR) circuitry and the under−voltage
lockout (UVLO) detection (VDD voltage dropout
detection). PORADJ pin allows the user, according to the
considered application, to adjust the VDD UVLO threshold.
If not used PORADJ pin is connected to Ground
(recommended even if it may be left unconnected).
The input supply voltage is continuously monitored to
prevent under voltage operation. At power up, the system
initializes the internal logic during POR timing and no further
signal can be provided or supported during this period.
The system is ready to operate when the input voltage has
reached the minimum VDD. Considering this, the
NCN8026A will detect an Under−Voltage situation when
the input supply voltage will drop below 1.45 V typical.
When VDD goes down below the UVLO falling threshold a
deactivation sequence is performed.
The device is inactive during power−on and power−off of
the VDD supply (8 ms reset pulse).
PORADJ pin is used to modify the UVLO threshold
according to the below relationship considering an external
resistor divider R1 / R2 (see block diagram Figure 1):
Table 1. CVCC PROGRAMMING
VSEL0
VSEL1
CVCC
0
0
3.0 V
0
1
5.0 V
1
0
3.0 V
1
1
1.8 V
UVLO +
R1 ) R2
V POR
R2
(eq. 1)
If PORADJ is connected to Ground the VDD UVLO
threshold (VDD falling) is typically 1.45 V. In some cases it
can be interesting to adjust this threshold at a higher value
and by the way increase the VDD supply dropout detection
VSEL0 can be used to select the CVCC programming
mode which can be 5V/3V (VSEL0 connected to Ground)
or 1.8V/3V (VSEL0 connected to VDD). VSEL0 and
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9
NCN8026A
While CVCC is enabled, the current to and from the card
I/O lines is limited internally to 15 mA and the maximum
guaranteed frequency on these lines is 1 MHz. If required,
an external series resistor up to 350 W can be added to limit
the CI/O pin current when CVCC is off, as shown by resistor
R3 in the application block diagram in Figure 1.
level which enables a deactivation sequence if the VDD
voltage is too low.
For example, there are microcontrollers for which the
minimum supply voltage insuring a correct operating is
higher than 1.45 V; increasing UVLOVDD (VDD falling) is
consequently necessary. Considering for instance a resistor
bridge with R1 = 56 kW, R2 = 42 kW and VPOR− = 1.22 V
typical the VDD dropout detection level can be increased up
to:
UVLO +
56k ) 42k
42k
V POR− + 2.85 V
POWER−UP AND STANDBY MODE
After a Power−on reset, the circuit enters the standby mode.
A minimum number of circuits are active while waiting for
the microcontroller to start a session:
− All card contacts are inactive
− Pins I/Ouc, AUX1uc and AUX2uc are pulled−up to
VDD with an active pull−up circuit
− Card pins are inactive and pulled Low
− Supply Voltage monitoring is active
(eq. 2)
CLOCK DIVIDER:
The input clock can be divided by 1/1, 1/2, 1/4, or 1/8,
depending upon the specific application, prior to be applied
to the smart card driver. These division ratios are
programmed using pins CLKDIV1 and CLKDIV2 (see
Table 2). The input clock is provided externally to pin
CLKIN.
INITIALIZATION SEQUENCE
If the CVCC output is not enabled following the
NCN8026A power up, a CVCC initialization is
recommended. For this initialization process, the PRES or
PRES pin can be activated by a card or the microcontroller.
Toggle CMDVCC from high to low to then enable CVCC.
After 10 ms, the CMDVCC pin can be set to high to return
to the standby mode. If using a microcontroller to activate
PRES or PRES pin, the microcontroller output can be set to
high impedance. This initialization process is only needed
upon NCN8026A power up.
Table 2. CLOCK FREQUENCY PROGRAMMING
CLKDIV1
CLKDIV2
FCCLK
0
0
CLKIN / 8
0
1
CKLKIN / 4
1
0
CLKIN
1
1
CLKIN / 2
SMART CARD POWER−UP
The clock input stage (CLKIN) can handle a 27 MHz
maximum frequency signal. Of course, the ratio must be
defined by the user to cope with Smart Card considered in
a given application
In order to avoid any duty cycle out of the 45% / 55%
range specification, the divider is synchronized by the last
flip flop, thus yielding a constant 50% duty cycle, whatever
be the divider ratio 1/2, 1/4 or 1/8. On the other hand, the
output signal Duty Cycle cannot be guaranteed 50% if the
division ratio is 1 and if the input Duty Cycle signal is not
within the 46% − 56% range at the CLKIN input.
When the signal applied to CLKIN is coming from the
external controller, the clock will be applied to the card
under the control of the microcontroller or similar device
after the activation sequence has been completed.
In the standby mode the microcontroller can check the
presence of a card using the signals INT and CMDVCC as
shown in Table 3:
Table 3. CARD PRESENCE STATE
INT
CMDVCC
State
HIGH
HIGH
Card present
LOW
HIGH
Card not present
If a card is detected present (PRES or PRES active) the
controller can start a card session by pulling CMDVCC
Low. Card activation is run (t0, Figure 5). This Power−Up
Sequence makes sure all the card related signals are LOW
during the CVCC positive going slope. These lines are
validated when CVCC is stable and above the minimum
voltage specified. When the CVCC voltage reaches the
programmed value (1.8 V, 3.0 V or 5.0 V), the circuit
activates the card signals according to the following
sequence (Figure 5):
− CVCC is powered−up at its nominal value (t1)
− I/O, AUX1 and AUX2 lines are activated (t2 ~ 10 ms)
− Then Clock is activated and the clock signal is applied
to the card (typically 2 ms after I/Os lines) (t3)
− Finally the Reset level shifter is enabled (typically 2 ms
after clock channel) (t4)
DATA I/O, AUX1 and AUX2 LEVEL SHIFTERS
The three bidirectional level shifters I/O, AUX1 and
AUX2 adapt the voltage difference that might exist between
the micro−controller and the smart card. These three
channels are identical. The first side of the bidirectional
level shifter dropping Low (falling edge) becomes the driver
side until the level shifter enters again in the idle state pulling
High CI/O and I/Ouc.
Passive 11 kW pull−up resistors have been internally
integrated on each terminal of the bidirectional channel. In
addition with these pull−up resistors, an active pull−up
circuit provides a fast charge of the stray capacitance.
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10
NCN8026A
The clock can also be applied to the card using a RSTIN
mode allowing controlling the clock starting by setting
RSTIN Low (Figure 4). Before running the activation
sequence, that is before setting Low CMDVCC RSTIN is set
High. The following sequence is applied:
− The Smart Card Interface is enable by setting
CMDVCC LOW (RSTIN is High).
− Between t2 (Figure 4) and t5 = 240 ms, RSTIN is reset
to LOW and CCLK will start precisely at this moment
allowing a precise count of clock cycles before toggling
CRST Low to High for ATR (Answer To Reset)
request.
− CRST remains LOW until 240 ms; after t5 = 240 ms
CRST is enabled and is the copy of RSTIN which has
no more control on the clock.
If controlling the clock with RSTIN is not necessary
(Normal Mode), then CMDVCC can be set LOW with
RSTIN LOW. In that case, CLK will start minimum 2 ms
after the transition on I/O (Figure 5), and to obtain an ATR,
CRST can be set High by RSTIN also about 2 ms after the
clock channel activation (Tact).
The internal activation sequence activates the different
channels according to a specific hardware built−in
sequencing internally defined but at the end the actual
activation sequencing is the responsibility of the application
software and can be redefined by the micro−controller to
comply with the different standards and the different ways
the standards manage this activation (for example light
differences exist between the EMV and the ISO7816
standards).
CMDVCC
CVCC
ATR
CIO
CCLK
RSTIN
CRST
t0
t1 t2
t4
t5
~240 ms
Figure 4. Activation Sequence − RSTIN Mode (RSTIN Starting High)
CMDVCC
CVCC
CIO
ATR
CCLK
RSTIN
CRST
t0
t1 t2 t3
t4
Tact
Figure 5. Activation Sequence − Normal Mode
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11
NCN8026A
SMART CARD POWER−DOWN
−
−
−
−
When the communication session is completed the
NCN8026A runs a deactivation sequence by setting High
CMDVCC. The below power down sequence is executed:
CRST is forced to Low
CCLK is set Low 12 ms after CRST.
CI/O, CAUX1 and CAUX2 are pulled Low
Finally CVCC supply can be shut−off.
CMDVCC
CRST
CCLK
CIO
CVCC
Tdeact
Figure 6. Deactivation Sequence
FAULT DETECTION
− DC/DC operation: the internal circuit continuously
senses the CVCC voltage (in the case of either over or
under voltage situation).
− DC/DC operation: under−voltage detection on VDDP
− Overheating
− Card pin current limitation: in the case of a short circuit
to ground. No feedback is provided to the external
MPU.
In order to protect both the interface and the external smart
card, the NCN8026A provides security features to prevent
failures or damages as depicted here after.
− Card extraction detection
− VDD under voltage detection
− Short−circuit or overload on CVCC
PRES
/INT
CMDVCC
debounce
debounce
CVCC
Powerdown resulting
of card extraction
Powerdown caused
by short−circuit
Figure 7. Fault Detection and Interrupt Management
Interrupt Pin Management:
During a card session, CMDVCC is Low and INT pin
goes Low when a fault is detected. In that case a deactivation
is immediately and automatically performed (see Figure 6).
When the microcontroller resets CMDVCC to High it can
sense the INT level again after having got completed the
deactivation.
As illustrated by Figure 7 the device has a debounce timer
of 8 ms typical duration. When a card is inserted, output INT
goes High only at the end of the debounce time. When the
card is removed a deactivation sequence is automatically
and immediately performed and INT goes Low.
A card session is opened by toggling CMDVCC High to
Low.
Before a card session, CMDVCC is supposed to be in a
High position. INT is Low if no card is present in the card
connector (Normally open or normally closed type). INT is
High if a card is present. If a card is inserted (INT = High)
and if VDD drops below the UVLO threshold then INT pin
drops Low immediately. It switches High when VDD
increases again over the UVLO limit (including hysteresis),
a card being still present.
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12
NCN8026A
MULTIPLE CARD OPERATION
WHEN CARD IS NOT IN USE
The chip select (CS) feature of the NCN8026A allows the
microcontroller to communicate with multiple smart cards,
reducing the number of pins used on the microcontroller. For
this feature to work, all cards in the system must be present
and active at all times (CVCC enabled). When CVCC is
deactivated, low impedance active pull−up circuits are
enabled on I/Ouc, AUX1uc, and AUX2uc. If any of these
pins are shared in a multiple card system, the active pull up
circuit can prevent the pin from reaching low logic voltage
levels.
Enable CVCC on all cards by toggling CMDVCC from
high to low on all devices. The CS pin is used to enable and
disable communication with the smart card without
disabling CVCC. When the CS pin is logic high, CMDVCC,
VSEL0, VSEL1, CLKDIV1, CLKDIV2, and RSTIN
become latched internally in the NCN8026A device. Use the
CS pin to control communication between specific smart
cards.
If I/Ouc and AUXuc pins of multiple NCN8026A devices
are connected commonly to the microcontroller, each
NCN8026A’s CMDVCC should be set low to avoid bus
collision on I/Ouc, AUX1uc, and AUX2uc. If disabling
CVCC on any cards not in use, add a disconnecting function
such as an analog switch on the I/Ouc, AUX1uc, and
AUX2uc pins on that device.
When the NCN8026A is powered on, CVCC is off. Upon
power on, I/Ouc, AUX1uc, and AUX2uc pins are driven
high with a low impedance active pull−up circuit sourcing
about 25 mA. The microcontroller’s I/O pins should be set
to a high impedance or input state during this time.
When CMDVCC is switched from high to low, CVCC
turns on. I/Ouc, AUX1uc, and AUX2uc are not driven by the
active pull−up circuit when CVCC is enabled and the
high−impedance pull−up resistor dominates.
When CMDVCC is switched from low to high, CVCC
turns off. The I/Ouc, AUX1uc, and AUX2uc pins are driven
high again with a low impedance active pull−up circuit
sourcing about 25 mA. The microcontroller’s I/O pins
should be set to a high impedance or input state during this
time.
ESD PROTECTION
The NCN8026A includes devices to protect the pins
against the ESD spike voltages. To cope with the different
ESD voltages developed across these pins, the built in
structures have been designed to handle either 2 kV, when
related to the micro controller side, or 8 kV when connected
with the external contacts (HBM model). Practically, the
CRST, CCLK, CI/O, CAUX1, CAUX2, PRES and PRES
pins can sustain 8 kV. The CVCC pin has the same ESD
protection and can source up to 70 mA continuously, the
absolute maximum current being internally limited with a
max at 150 mA. The CVCC current limit depends on VDDP
and CVCC.
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13
NCN8026A
APPLICATION SCHEMATIC
VDD
+ 3.3V
100 nF
23
22
21
20
19
VSEL0
1
CS
3
16
25
PRES
4
PRES
5
14
6
13
15
GND
CAUX2
R3
8
9
10
GND
VDD
100 nF
RSTIN
CMDVCC
Optional R1/R2 resistor
divider – if not used it is
recommended to connect
PORADJ to Ground
11 12
CVCC
7
100kΩ
PORADJ
CI/O
VDD
+ 3.3V
Exposed Pad
CRST
+ 10 μF
3.3 V Microcontroller
CLKIN
17 INT
2
CCLK
100 nF
VDDP
18
CAUX1
VDDP
+5 V
XTAL2
I/Ouc
AUX1uc
AUX2uc
CLKDIV1
VSEL1
24
CLKDIV2
XTAL1
R1
220 nF
R2
1
2
3
4
100 nF
Vcc GND
RST Vpp
CLK
I/O
C4
C8
5
6
7
8
DET
Normally Open
SMART CARD
Figure 8. Application Schematic
ORDERING INFORMATION
Device
NCN8026AMNTXG
Package
Shipping†
QFN24
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN24, 4x4, 0.5P
CASE 485L
ISSUE B
1 24
SCALE 2:1
D
PIN 1
REFEENCE
2X
0.15 C
2X
ÉÉÉ
ÉÉÉ
ÉÉÉ
0.15 C
DETAIL A
E
ALTERNATE
CONSTRUCTIONS
ÉÉÉ
ÉÉÉ
ÇÇÇ
EXPOSED Cu
DETAIL B
0.10 C
SEATING
PLANE
L
24X
7
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
4.00 BSC
2.70
2.90
4.00 BSC
2.70
2.90
0.50 BSC
0.30
0.50
0.05
0.15
XXXXX
XXXXX
ALYWG
G
13
E2
1
24
A1
A3
GENERIC
MARKING DIAGRAM*
D2
DETAIL A
ÉÉ
ÉÉ
ÇÇ
ALTERNATE TERMINAL
CONSTRUCTIONS
C
A1
SIDE VIEW
MOLD CMPD
DETAIL B
A
A3
NOTE 4
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
L1
TOP VIEW
0.08 C
L
L
A
B
DATE 05 JUN 2012
19
e
e/2
24X
b
0.10 C A B
0.05 C
BOTTOM VIEW
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT
4.30
24X
0.55
2.90
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
1
4.30
2.90
0.50
PITCH
24X
0.32
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98AON11783D
QFN24, 4X4, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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