NCP1234
Fixed Frequency Current
Mode Controller for Flyback
Converters
The NCP1234 is a new fixed−frequency current−mode controller
featuring Dynamic Self−Supply (DSS). This device is pin−to−pin
compatible with the previous NCP12xx families.
The DSS function greatly simplifies the design of the auxiliary
supply and the VCC capacitor by activating the internal startup current
source to supply the controller during transients.
Due to frequency foldback, the controller exhibits excellent
efficiency in light load condition while still achieving very low
standby power consumption. Internal frequency jittering, ramp
compensation, and a versatile latch input make this controller an
excellent candidate for converters where components cost is the key
constraints.
It features a timer−based fault detection that ensures the detection of
overload independently of an auxiliary winding, and an adjustable
compensation to help keep the maximum power independent of the
input voltage.
Finally, due to a careful design, the precision of critical parameters
is well controlled over the entire temperature range (−40°C to
+125°C).
Features
• Fixed−Frequency Current−Mode Operation with Built−In Ramp
Compensation
• 65 kHz or 100 kHz Oscillator Frequency version
• Frequency Foldback then Skip Mode for Maximized Performance in
Light Load and Standby Conditions
•
•
•
•
•
•
•
•
•
SOIC−7
CASE 751U
MARKING DIAGRAM
8
34Xff
ALYWX
G
1
34Xff = Specific Device Code
X = A or B
ff = 65 or 100
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
Latch 1
8
HV
6
VCC
FB 2
• Timer−Based Overload Protection with Latched (option A) or
•
www.onsemi.com
CS 3
Auto−Recovery (option B) Operation
GND 4
5 DRV
High−voltage Current Source with Dynamic Self−Supply,
(Top View)
Simplifying the Design of the VCC Capacitor
Frequency Modulation for Softened EMI Signature, including during
ORDERING INFORMATION
Frequency Foldback mode
See detailed ordering and shipping information in the package
dimensions section on page 32 of this data sheet.
Adjustable Overpower Compensation
Latch−off Input for Severe Fault Conditions, Allowing Direct
Connection of an NTC for Overtemperature Protection (OTP)
VCC Operation up to 28 V, with Overvoltage Detection
±500 mA Peak Source/Sink Current Drive Capability
4.0 ms Soft−Start
Typical Applications
Internal Thermal Shutdown
• AC−DC Adapters for Notebooks, LCD, and Printers
Pin−to−Pin Compatible with the Existing NCP12xx
• Offline Battery Chargers
Series
• Consumer Electronic Power Supplies
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
• Auxiliary/Housekeeping Power Supplies
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 2
1
Publication Order Number:
NCP1234/D
NCP1234
TYPICAL APPLICATION EXAMPLE
VOUT
VIN
(dc)
LATCH
FB
HV
NCP1234
CS
VCC
GND
DRV
Figure 1. Flyback Converter Application Using the NCP1234
PIN FUNCTION DESCRIPTION
Pin No
Pin Name
Function
1
LATCH
Latch−Off Input
2
FB
Feedback
3
CS
Current Sense
4
GND
5
DRV
Drive output
6
VCC
VCC input
8
HV
High−voltage pin
Pin Description
Pull the pin up or down to latch−off the controller. An internal current source
allows the direct connection of an NTC for over temperature detection
An optocoupler collector to ground controls the output regulation.
This Input senses the Primary Current for current−mode operation, and Offers
an overpower compensation adjustment.
IC Ground
Drives external MOSFET
This supply pin accepts up to 28 Vdc, with overvoltage detection
Connects to the bulk capacitor or the rectified AC line to perform the functions
of Start−up Current Source and Dynamic Self−Supply
www.onsemi.com
2
NCP1234
SIMPLIFIED INTERNAL BLOCK SCHEMATIC
VDD
+
−
+
INTC
HV
blanking
tLatch(OVP)
VOVP
INTC
Latch
+
HV
−
+
TSD
TSD
blanking
Dual HV
start−up
current source
tLatch(OTP)
1 kW
S
VOTP
Q
Latch
R
Vclamp
Soft−start
end
TSD HV current
Reset
UVLO
VCC
VDD
Start management
UVLO
VDD
IC Start
Reset
VCC
VFB(ref)
−
+
+
Vskip
20 kW
/5
slope
comp.
FB
HV sample
PWM
+
−
V to I
IOPC = 0.5m x
(VHV − 125)
Jitter
Sawtooth
Soft−start
+
−
Stop
Foldback
−
+
Oscillator
+
Soft−start ramp Start
t
End SSTART Reset
VFB(OPC)
IC Start
Clamp
IC Stop
S
Soft−start end
blanking
tLEB
Q
R
CS
+
blanking
tBCS
DRV
+
−
ILIMIT
VILIM
IC stop
GND
ILIMIT
S
Q
R
+
Fault Flag
Protection
Mode
release
+
−
Latch
For
Autorecovery
protection
mode only
VCS(stop)
timer
PWM
tfault
timer
tautorec
Fault
Reset
Figure 2. Simplified Internal Block Schematic
www.onsemi.com
3
TSD
UVLO
NCP1234
MAXIMUM RATINGS
Symbol
Value
Unit
Supply Pin (pin 6) (Note 2)
Voltage range
Current range
Rating
VCCMAX
ICCMAX
–0.3 to 28
±30
V
mA
High Voltage Pin (pin 8) (Note 2)
Voltage range
Current range
VHVMAX
IHVMAX
–0.3 to 500
±20
V
mA
Driver Pin (pin 5) (Note 2)
Voltage range
Current range
VDRVMAX
IDRVMAX
–0.3 to 20
±1000
V
mA
VMAX
IMAX
–0.3 to 10
±10
V
mA
All other pins (Note 2)
Voltage range
Current range
Thermal Resistance SOIC−7
Junction−to−Air, low conductivity PCB (Note 3)
Junction−to−Air, medium conductivity PCB (Note 4)
Junction−to−Air, high conductivity PCB (Note 5)
RθJ−A
°C/W
162
147
115
°C
Temperature Range
Operating Junction Temperature
Storage Temperature Range
TJMAX
TSTRGMAX
ESD Capability (Note 1)
Human Body Model (All pins except HV)
Machine Model
−40 to +150
−60 to +150
V
2000
200
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC standard JESD22, Method A114E
Machine Model Method 200 V per JEDEC standard JESD22, Method A115A
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78
3. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51−1 conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51−2 conductivity test PCB. Test conditions were under natural convection or zero air flow.
5. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51−3 conductivity test PCB. Test conditions were under natural convection or zero air flow.
www.onsemi.com
4
NCP1234
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,
VCC = 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
VHV(min)
−
30
40
V
Istart1
Istart2
0.2
3
0.5
6
0.8
9
mA
Istart(off)
−
25
50
mA
Turn−on threshold level, VCC
going up
HV current source stop threshold
VCC(on)
11.0
12.0
13.0
V
HV current source restart
threshold
VCC(min)
9.5
10.5
11.5
V
Turn−off threshold
VCC(off)
8.5
9.5
10.5
V
Overvoltage threshold
VCC(ovp)
25
26.5
28
V
Blanking duration on VCC(off) and
VCC(ovp) detection
tVCC(blank)
7
10
13
ms
VCC decreasing level at which
the internal logic resets
VCC(reset)
3.6
5.0
6.0
V
VCC level for ISTART1 to ISTART2
transition
VCC(inhibit)
0.4
1.0
1.6
V
ICC1
ICC1
ICC2
ICC2
ICC3
ICC4
1.2
1.3
1.9
2.2
0.67
0.4
1.8
1.9
2.5
2.9
0.9
0.7
2.2
2.3
3.2
3.6
1.13
1.0
mA
Oscillator frequency
fOSC
60
92
65
100
70
108
kHz
Maximum duty cycle
DMAX
75
80
85
%
Frequency jittering amplitude, in
percentage of FOSC
Ajitter
±4
±6
±8
%
Frequency jittering modulation
frequency
Fjitter
85
125
165
Hz
HIGH VOLTAGE CURRENT SOURCE
Minimum voltage for current
source operation
Current flowing out of VCC pin
VCC = 0 V
VCC = VCC(on) − 0.5 V
Off−state leakage current
VHV = 500 V
SUPPLY
Internal current consumption
(Note 6)
DRV open, VFB = 3 V, 65 kHz
DRV open, VFB = 3 V, 100 kHz
Cdrv = 1 nF, VFB = 3 V, 65 kHz
Cdrv = 1 nF, VFB = 3 V, 100 kHz
Off mode (skip or before start−up)
Fault mode (fault or latch)
OSCILLATOR
OUTPUT DRIVER
Rise time, 10% to 90 % of VCC
VCC = VCC(min) + 0.2 V, CDRV = 1 nF
trise
−
40
70
ns
Fall time, 90% to 10 % of VCC
VCC = VCC(min) + 0.2 V, CDRV = 1 nF
tfall
−
40
70
ns
Current capability
VCC = VCC(min) + 0.2 V, CDRV = 1 nF
DRV high, VDRV = 0 V
DRV low, VDRV = VCC
IDRV(source)
IDRV(sink)
−
−
500
500
−
−
mA
Clamping voltage (maximum
gate voltage)
VCC = VCCmax – 0.2 V, DRV high,
RDRV = 33 kW, Cload = 220 pF
VDRV(clamp)
11
13.5
16
V
High−state voltage drop
VCC = VCC(min) + 0.2 V, RDRV = 33 kW,
DRV high
VDRV(drop)
−
−
1
V
6. internal supply current only, current in FB pin not included (current flowing in GND pin only).
www.onsemi.com
5
NCP1234
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,
VCC = 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
RFB(up)
15
20
25
kW
VFB to internal current setpoint
division ratio
KFB
4.7
5
5.3
−
Internal pull−up voltage on the
FB pin
VFB(ref)
4.3
5
5.7
V
FEEDBACK
Internal pull−up resistor
TJ = 25°C
CURRENT SENSE
Input Bias Current
VCS = 0.7 V
Ibias
−
0.02
−
mA
Maximum internal current
setpoint
VFB > 3.5 V
VILIM
0.66
0.7
0.74
V
Propagation delay from VIlimit
detection to DRV off
VCS = VILIM
tdelay
−
80
110
ns
tLEB
190
250
310
ns
VCS(stop)
0.95
1.05
1.15
V
Leading Edge Blanking Duration
for VCS(stop)
tBCS
90
120
150
ns
Slope of the compensation ramp
Scomp(65kHz)
Scomp(100kHz)
−
−
−32.5
−50
−
−
mV /
ms
From 1st pulse to VCS = VILIM
tSSTART
2.8
4.0
5.2
ms
KOPC
−
0.54
−
mA / V
Current flowing out of CS pin
VHV = 125 V
VHV = 162 V
VHV = 325 V
VHV = 365 V
IOPC(125)
IOPC(162)
IOPC(325)
IOPC(365)
−
−
−
105
0
20
110
130
−
−
−
150
mA
FB voltage above which IOPC is
applied
VHV = 365 V
VFB(OPCF)
2.12
2.35
2.58
V
FB voltage below which is no
IOPC applied
VHV = 365 V
VFB(OPCE)
−
2.15
−
V
Watchdog timer for dc operation
tWD(OPC)
−
32
−
ms
HV sampling level
VHVsample
−
92
−
V
tfault
98
128
168
ms
tautorec
0.85
1.00
1.35
s
Feedback voltage threshold
below which frequency foldback
starts
VFB(foldS)
1.8
2.0
2.2
V
Feedback voltage threshold
below which frequency foldback
is complete
VFB(foldE)
1.22
1.35
1.48
V
VFB = Vskip(in) + 0.2
fOSC(min)
22
27
32
kHz
VFB going down
VFB going up
Vskip(in)
Vskip(out)
0.63
0.72
0.7
0.80
0.77
0.88
V
Leading Edge Blanking Duration
for VILIM
Threshold for immediate fault
protection activation
Soft−start duration
OVERPOWER COMPENSATION
VHV to IOPC conversion ratio
OVERCURRENT PROTECTION
Fault timer duration
From CS reaching VILIMIT to DRV stop
Autorecovery mode latch−off
time duration
FREQUENCY FOLDBACK
Minimum switching frequency
SKIP−CYCLE MODE
Feedback voltage thresholds for
skip mode
www.onsemi.com
6
NCP1234
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,
VCC = 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
LATCH−OFF INPUT
High threshold
VLatch going up
VOVP
2.35
2.5
2.65
V
Low threshold
VLatch going down
VOTP
0.76
0.8
0.84
V
Current source for direct NTC
connection
During normal operation
During soft−start
VLatch = 0 V
Blanking duration on high latch
detection
65 kHz version
100 kHz version
mA
Blanking duration on low latch
detection
Clamping voltage
ILatch = 0 mA
ILatch = 1 mA
INTC
INTC(SSTART)
65
130
95
190
105
210
tLatch(OVP)
35
25
50
35
70
45
ms
tLatch(OTP)
−
350
−
ms
Vclamp0(Latch)
Vclamp1(Latch)
1.0
2.0
1.2
2.4
1.4
3.0
V
TTSD
135
150
165
°C
TTSD(HYS)
20
30
40
°C
TEMPERATURE SHUTDOWN
Temperature shutdown
TJ going up
Temperature shutdown
hysteresis
TJ going down
www.onsemi.com
7
NCP1234
TYPICAL PERFORMANCE CHARACTERISTICS
40.00
35
38.00
30
36.00
25
Istart(off) (V)
VHV(min) (V)
34.00
32.00
30.00
28.00
26.00
20
15
10
24.00
5
22.00
20.00
−50
−25
0
25
50
75
TEMPERATURE (°C)
100
125
0
−50
0.75
1.15
0.74
1.13
0.73
1.11
0.72
1.09
0.71
0.70
0.69
0.99
0.66
0.97
25
50
75
100
125
1.03
1.01
0
100
1.05
0.67
−25
25
50
75
TEMPERATURE (°C)
1.07
0.68
0.65
−50
0
Figure 4. Off−State Leakage Current Istart(off)
VCS(stop) (V)
VILIM (V)
Figure 3. Minimum Current Source Operation
VHV(min)
−25
125
0.95
−50
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. Maximum Internal Current Setpoint
VILIM
Figure 6. Threshold for Immediate Fault
Protection Activation VCS(stop)
125
300
110
290
100
280
270
tLEB (ns)
tdelay (ns)
90
80
70
260
250
240
230
60
220
50
210
40
−50
−25
0
25
50
75
100
200
−50
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Propagation Delay tdelay
Figure 8. Leading Edge Blanking Duration tLEB
www.onsemi.com
8
NCP1234
TYPICAL PERFORMANCE CHARACTERISTICS
24
5.30
23
5.20
5.10
21
VFB(ref) (V)
RFB(up) (kW)
22
20
19
18
5.00
4.90
4.80
17
4.70
16
15
−50
−25
0
25
50
75
TEMPERATURE (°C)
100
4.60
−50
125
70
85
69
84
68
83
67
82
66
81
65
64
78
77
61
76
0
25
50
75
TEMPERATURE (°C)
100
100
125
79
62
−25
25
50
75
TEMPERATURE (°C)
80
63
60
−50
0
Figure 10. FB Pin Open Voltage VFB(ref)
DMAX (%)
fOSC (kHz)
Figure 9. FB Pin Internal Pull−up Resistor
RFB(up)
−25
75
−50
125
Figure 11. Oscillator Frequency fOSC
−25
0
25
50
75
TEMPERATURE (°C)
100
125
Figure 12. Maximum Duty Cycle DMAX
2.20
1.50
2.15
1.45
VFB(foldE) (V)
VFB(foldS) (V)
2.10
2.05
2.00
1.95
1.40
1.35
1.30
1.90
1.25
1.85
1.80
−50
−25
0
25
50
75
100
125
1.20
−50
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. FB Pin Voltage Below Which
Frequency Foldback Starts VFB(foldS)
Figure 14. FB Pin Voltage Below Which
Frequency Foldback is Complete VFB(foldE)
www.onsemi.com
9
125
NCP1234
TYPICAL PERFORMANCE CHARACTERISTICS
0.77
0.88
0.75
0.86
0.84
Vskip(out) (V)
Vskip(in) (V)
0.73
0.71
0.69
0.67
0.82
0.80
0.78
0.76
0.65
0.74
0.63
−50
−25
0
25
50
75
100
125
0.72
−50
−25
0
TEMPERATURE (°C)
25
50
75
100
125
TEMPERATURE (°C)
Figure 15. FB Pin Skip−in Level Vskip(in)
Figure 16. FB Pin Skip−Out Level Vskip(out)
30
150
29
145
140
27
IOPC(365) (mA)
fOSC(min) (kHz)
28
26
25
24
130
125
23
120
22
115
21
20
−50
−25
0
25
50
75
100
125
110
−50
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Minimum Switching Frequency
fOSC(min)
Figure 18. Maximum Overpower
Compensating Current IOPC(365) Flowing Out
of CS Pin
2.60
2.40
2.55
2.35
2.50
2.30
2.45
2.25
VFB(OPCE) (V)
VFB(OPCF) (V)
135
2.40
2.35
2.30
2.25
125
2.20
2.15
2.10
2.05
2.20
2.00
2.15
1.95
1.90
2.10
−50
−25
0
25
50
75
TEMPERATURE (°C)
100
125
−50
Figure 19. FB Pin Level VFB(OPCF) Above
Which is the Overpower Compensation
Applied
−25
0
25
50
75
TEMPERATURE (°C)
100
Figure 20. FB Pin Level VFB(OPCE) Below
Which is No Overpower Compensation
Applied
www.onsemi.com
10
125
NCP1234
TYPICAL PERFORMANCE CHARACTERISTICS
0.85
2.65
0.84
2.60
0.83
0.82
VOTP (V)
VOVP (V)
2.55
2.50
2.45
0.81
0.80
0.79
0.78
0.77
2.40
0.76
2.35
−50
0.75
−25
0
25
50
75
TEMPERATURE (°C)
100
125
−50
1.34
2.80
1.32
2.70
1.30
2.60
1.28
2.50
Vclamp1 (V)
Vclamp0 (V)
0
25
50
75
TEMPERATURE (°C)
100
125
Figure 22. Latch Pin Low Threshold VOTP
Figure 21. Latch Pin High Threshold VOVP
1.26
1.24
2.40
2.30
1.22
2.20
1.20
2.10
1.18
2.00
−50
−25
0
25
50
75
TEMPERATURE (°C)
100
125
−50
Figure 23. Latch Pin Open Voltage Vclamp0
110
220
105
210
100
200
95
90
85
150
25
50
75
100
100
125
170
75
0
25
50
75
TEMPERATURE (°C)
180
160
−25
0
190
80
70
−50
−25
Figure 24. Latch Pin Voltage Vclamp1 (Latch−off
Pin is Sinking 1 mA)
INTC(SSTART) (mA)
INTC (mA)
−25
140
−50
125
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 25. Current INTC Sourced from the
Latch Pin, Allowing Direct NTC Connection
Figure 26. Current INTC(SSTART) Sourced from
the Latch Pin, During Soft−Start
www.onsemi.com
11
125
NCP1234
APPLICATION INFORMATION
Introduction
The NCP1234 includes all necessary features to build a safe
and efficient power supply based on a fixed−frequency
flyback converter. It is particularly well suited for
applications where low part count is a key parameter,
without sacrificing safety.
• Current−Mode Operation with slope compensation:
The primary peak current is permanently controlled by
the FB voltage, ensuring maximum safety: the DRV
turn−off event is dictated by the peak current setpoint.
It also ensures that the frequency response of the
system stays a first order if in DCM, which eases the
design of the FB loop. The controller can be also used
in CCM applications with a wide input voltage range
thanks to its fixed ramp compensation that prevents the
appearance of sub−harmonic oscillations in most
applications.
• Fixed−Frequency Oscillator with Jittering: The
NCP1234 is available in different frequency options to
fit any application. The internal oscillator features a
low−frequency jittering that helps passing the EMI
limits by spreading out the energy content of frequency
peaks in quasi−peak and average mode of
measurement.
• Latched Timer−Based Overload Protection: The
overload protection depends only on the FB signal,
making it able to work with any transformer, even with
very poor coupling or high leakage inductance. The
protection is fully latched on the A version (the power
supply has to be stopped then restarted in order to
resume operation, even if the overload condition
disapears), and autorecovery on the B version. The
timer duration is fixed. The controller also enters the
same protection mode if the voltage on the CS pin
reaches 1.5 times the maximum internal setpoint
(allows to detect winding short-circuits).
• High Voltage Start−Up Current Source: Thanks to
ON Semiconductor’s Very High Voltage technology,
the NCP1234 can directly be connected to the high
input voltage. The start-up current source ensures a
clean start-up while ensuring low losses when it is off,
and the Dynamic Self-Supply (DSS) restarts the
start-up current source to supply the controller if the
VCC supply transiently drops.
• Adjustable Overpower Compensation: The high
input voltage sensed on the HV pin is converted into a
current to build on the current sense voltage an offset
proportional to the input voltage. By choosing the value
of the resistor in series with the CS pin, the amount of
compensation can be adjusted to the application.
• Frequency foldback then skip mode for light load
operation: In order to ensure a high efficiency under all
load conditions, the NCP1234 implements a frequency
•
•
•
•
•
foldback for light load condition and a skip mode for
extremely low load condition. The switching frequency
is decreased down to 27 kHz to reduce switching
losses.
Extended VCC range: The NCP1234 accepts a supply
voltage as high as 28 V, with an overvoltage threshold
VCC(ovp) (typically 26.5 V) that latches the controller
off.
Clamped Driver Stage: Despite the high maximum
supply voltage, the voltage on DRV pin is safely
clamped below 16 V, allowing the use of any standard
MOSFET, and reducing the current consumption of the
controller.
Dual Latch−off Input: The NCP1234 can be latched
off by 2 ways: The voltage increase applied to its Latch
pin (typically an overvoltage) or by a decrease this
voltage. Thanks to the internal precise pull−up current
source a NTC can be directly connected to the latch pin.
This NTC will provide an overtemperature protection
by decreasing its resistance and consequently the
voltage at Latch pin,
Soft−Start: At every start−up the peak current is
gradually increased during 4.0 ms to minimize the
stress on power components.
Temperature Shutdown: The NCP1234 is internally
protected against self−overheating: if the die
temperature is too high, the controller shuts all
circuitries down (including the HV start−up current
source), allowing the silicon to cool down before
attempting to restart. This ensures a safe behavior in
case of failure.
Typical Operation
• Start−up: The HV start−up current source ensures the
•
•
charging of the VCC capacitor up to the start−up
threshold VCC(on), until the input voltage is high
enough (above VHV(start)) to allow the switching to
start. The controller then delivers pulses, starting with a
soft−start period tSSTART during which the peak current
linearly increases before the current−mode control takes
over. During the soft−start period, the low level latch is
ignored, and the latch current is double, to ensure a fast
pre−charge of the Latch pin decoupling capacitor.
Normal operation: As long as the feedback voltage is
within the regulation range and VCC is maintained
above VCC(min), the NCP1234 runs at a fixed frequency
(with jittering) in current−mode control. The peak
current (sensed on the CS pin) is set by the voltage on
the FB pin. Fixed ramp compensation is applied
internally to prevent sub−harmonic oscillations from
occurring.
Light load operation: When the FB voltage decreases
below VFB(foldS), typically corresponding to a load of
www.onsemi.com
12
NCP1234
•
33% of the maximum load (for a DCM design), the
switching frequency starts to decrease down to
fOSC(min). By lowering the switching losses, this feature
helps to improve the efficiency in light load conditions.
The frequency jittering is enabled in light load
operation as well.
No load operation: When the FB voltage decreases
below Vskip(in), typically corresponding to a load of 2%
of the maximum load, the controller enters skip mode.
By completely stopping the switching while the
feedback voltage is below Vskip(out), the losses are
further reduced. This allows minimizing the power
dissipation under extremely low load conditions. As the
skip mode is entered at very light loads, for which the
peak current is very small, there is no risk of audible
noise. VCC can be maintained between VCC(on) and
VCC(min) by the DSS, if the auxiliary winding does not
•
•
provide sufficient level of VCC voltage under this
condition.
Overload: The NCP1234 features timer−based
overload detection, solely dependent on the feedback
information: as soon as the internal peak current
setpoint hits the VILIM clamp, an internal timer starts to
count. When the timer elapses, the controller stops and
enter the protection mode, autorecovery for the B
version (the controller initiates a new start−up after
tautorec elapses), or latched for the A version (the latch
is released only if VCC is reset).
Latch−off: When the Latch input is pulled up (typically
by an over−voltage condition), or pulled down
(typically by an over−temperature condition, using the
provided current source with an NTC), the controller
latches off. The latch is released when the VCC is reset.
www.onsemi.com
13
NCP1234
DETAILED DESCRIPTION
High−Voltage Current Source
The NCP1234 HV pin can be connected either to the
rectified bulk voltage, or to the ac line through a rectifier.
However, the overpower compensation will work correctly
only if the HV pin is connected to the bulk voltage.
Start−up
HV
Istart
TSD
Control
IC Start
VCC
+
−
+
VCC(on)
R
Q
S
−
+
+
VCC(min)
blanking
−
+
+
UVLO
tUVLO(blank)
VCC(off )
−
+
+
Reset
VCC(reset)
Figure 27. HV Start−up Current Source Functional Schematic
condition, otherwise the power dissipation on the die would
be too much. As a result, an auxiliary voltage source is
needed to supply VCC during normal operation.
The DSS is useful to keep the controller alive when no
switching pulses are delivered, e.g. in latch condition, or to
prevent the controller from stopping during load transients
when the VCC might drop.
At start−up, the current source turns on when the voltage
on the HV pin is higher than VHV(min), and turns off when
VCC reaches VCC(on), then turns on again when VCC reaches
VCC(min), until VCC is supplied by an internal source. The
controller actually starts the next time VCC reaches VCC(on).
Even though the DSS is able to maintain the VCC voltage
between VCC(on) and VCC(min) by turning the HV start−up
current source on and off, it can only be used in light load
www.onsemi.com
14
NCP1234
VHV
VHV(min)
time
VCC
VCC(on)
VCC(min)
HV
current
source =
Istart1
HV
current
source =
Istart2
VCC(inhibit)
time
DRV
time
Figure 28. Start−up Timing Diagram
regulation. At the same time, VCC drops, but because there
is no voltage anymore on the HV pin, the DSS isn’t able to
turn on. As a result, VCC drops even more and reach the
VCC(off) threshold, that turns the controller off, and resets the
internal fault timer, to prevent any unwanted latch−off and
allow a fast restart in case of a short OFF/ON sequence.
As soon as the application is turned back on, the HV
start−up current source starts to charge the VCC capacitor.
Note that the threshold at which VCC discharges has no
influence on the ability of the controller to restart. The
switching then turns on when VCC reaches VCC(on), without
additional delay or “hiccup”.The case of a fast OFF/ON
sequence is described at Figure 29.
For safety reasons, the start−up current is lowered when
VCC is below VCC(inhibit), to reduce the power dissipation in
case the VCC pin is shorted to GND (in case of VCC capacitor
failure, or external pull−down on VCC to disable the
controller).
There are only two conditions for which the current source
doesn’t turn on when VCC reaches VCC(min): the voltage on
HV pin is too low (below VHV(min)), or a thermal shutdown
condition (TSD) has been detected. In all other conditions,
the HV current source will always turn on and off to maintain
VCC between VCC(min) and VCC(on).
When the application is turned off, the input capacitor
quickly discharges, and the output starts to fall out of
www.onsemi.com
15
NCP1234
VHV
The board is
unplugged
VHV(min)
time
VCC
VCC(on)
VCC(min)
VCC(off)
Controller
stops at
VCC(off)
VCC charges
up when VHV is
high enough
time
Output
Loss of
regulation when
VHV is too low
Switching
restarts at
VCC(on)
DRV
time
time
Fault timer
(internal)
Fault timer
reset by
VCC(off)
Figure 29. Fast Application Off − On Sequence
www.onsemi.com
16
time
NCP1234
Oscillator with Maximum Duty Cycle and Frequency
Jittering
Clamped Driver
The supply voltage for the NCP1234 can be as high as
28 V, but most of the MOSFETs that will be connected to the
DRV pin cannot accept more than 20 V on their gate. The
driver pin is therefore clamped safely below 16 V. This
driver has a typical current capability of ±500 mA.
The NCP1234 includes an oscillator that sets the
switching frequency with an accuracy of ±7%. Two
frequency options can be ordered: 65 kHz and 100 kHz. The
maximum duty cycle of the DRV pin is 80%, with an
accuracy of ±7%.
In order to improve the EMI signature, the switching
frequency jitters ±6% around its nominal value, with a
triangle−wave shape and at a frequency of 125 Hz. This
frequency jittering is active even when the frequency is
decreased to improve the EMI in light load condition.
VCC
Clamp
DRV signal
fOSC
fOSC + 6
Nominal fOSC
fOSC − 6
Figure 31. Clamped Driver
Time
8%
(125 Hz)
Figure 30. Frequency Jittering
www.onsemi.com
17
DRV
NCP1234
CURRENT−MODE CONTROL WITH OVERPOWER COMPENSATION AND SOFT−START
Current sensing
input of the PWM comparator through a 250 ns LEB block.
On the other input the FB voltage divided by 5 sets the
threshold: when the voltage ramp reaches this threshold, the
output driver is turned off.
The maximum value for the current sense is 0.7 V, and it
is set by a dedicated comparator.
NCP1234 is a current−mode controller, which means that
the FB voltage sets the peak current flowing in the
inductance and the MOSFET. This is done through a PWM
comparator: the current is sensed across a resistor and the
resulting voltage is applied to the CS pin. It is applied to one
VFB(ref)
KFB
+
−
RFB(up)
PWM
Jitter
Soft−start
+
−
Oscillator
Soft−start ramp
Start
tSSTART
Reset
FB
IC Start
IC Stop
S
Q
R
blanking
tLEB
CS
DRV Stage
+
−
+
VILIM
IC stop
blanking
tBCS
+
−
+
Protection
Mode
VCS(stop)
UVLO
Latch
TSD
Fault
Figure 32. Current Sense Block Schematic
Each time the controller is starting, i.e. the controller was
off and starts – or restarts – when VCC reaches VCC(on), a
soft−start is applied: the current sense setpoint is linearly
increased from 0 (the minimum level can be higher than 0
because of the LEB and propagation delay) until it reaches
VILIM (after a duration of tSSTART), or until the FB loop
imposes a setpoint lower than the one imposed by the
soft−start (the 2 comparators outputs are OR’ed). The
soft−start ramp signal is generated by the D/A converter in
the NCP1234, that’s why there are observable 15 discrete
steps instead the truly linearly increasing current setpoint
ramp.
www.onsemi.com
18
NCP1234
VFB
VFB(fault)
Time
Soft-start ramp
VFB takes
over soft-start
VILIM
Time
tSSTART
CS Setpoint
VILIMI
Time
Figure 33. Soft−Start
Overpower compensation
Under some conditions, like a winding short−circuit for
instance, not all the energy stored during the on time is
transferred to the output during the off time, even if the on
time duration is at its minimum (imposed by the propagation
delay of the detector added to the LEB duration). As a result,
the current sense voltage keeps on increasing above VILIM,
because the controller is blind during the LEB blanking
time. Dangerously high current can grow in the system if
nothing is done to stop the controller. That’s what the
additional comparator, that senses when the current sense
voltage on CS pin reaches VCS(stop) (= 1.5 x VILIM), does:
as soon as this comparator toggles, the controller
immediately enters the protection mode (latched or
autorecovery according to the chosen option).
The power delivered by a flyback power supply is
proportional to the square of the peak current in the
discontinuous conduction mode:
P OUT +
1
@ h @ L p @ F SW @ I p
2
2
(eq. 1)
Unfortunately, due to the inherent propagation delay of
the logic, the actual peak current is higher at high input
voltage than at low input voltage, leading to a significant
difference in the maximum output power delivered by the
power supply.
www.onsemi.com
19
NCP1234
IP
IP to be
compensated
ILIMIT
High
Line
Low
Line
time
tdelay
tdelay
Figure 34. Line Compensation for True Overpower Protection
would be in the same order of magnitude. Therefore the
compensation current is only added when the FB voltage is
higher than VFB(OPCE).
However, because the HV pin can be connected to an ac
voltage, there is needed an additional circuitry to read or at
least closely estimate the actual voltage on the bulk
capacitor.
To compensate this and have an accurate overpower
protection, an offset proportional to the input voltage is
added on the CS signal by turning on an internal current
source: by adding an external resistor in series between the
sense resistor and the CS pin, a voltage offset is created
across it by the current. The compensation can be adjusted
by changing the value of the resistor.
But this offset is unwanted to appear when the current
sense signal is small, i.e. in light load conditions, where it
HV
(32 ms)
Watch
Dog
VHVstop
A/D 3 bit
Converter
+
Peak Detector
3 bit
Register
I Generator
I ctrl
FB
To CS
Block
Tblanking
LEB
CS
VFB (OPC)
Figure 35. Schematic Overpower Compensation Circuit
A 3 bit A/D converter with the peak detector senses the ac
input, and its output is periodically sampled and reset, in
order to follow closely the input voltage variations. The
sample and reset events are given by the VHVsample
comparator used for sampling detection for the AC line
input. If only the DC high voltage input is used, no reset
signal is generated by the VHVsample condition and the 32 ms
watch dog is used to generate the sampling events for
sampling the DC input high voltage line.
www.onsemi.com
20
NCP1234
IOPC
VHV
VFB
VFB(OPCE)
VFB(OPCF)
Figure 36. Overpower Compensation Current Relation to Feedback Voltage and Input Voltage
VHV
VHVsample
time
Peak
detector
Reset
Reset
Reset
twd
Reset
Reset
time
IOPC
Sample
Sample
Sample
Sample
Reset
time
Figure 37. Overpower Compensation Current if the HV Pin is Connected to AC Voltage
www.onsemi.com
21
NCP1234
VHV
VHV(stop)
time
twd
twd
twd
Peak
detector
Reset
time
IOPC
Sample
Sample
Reset
Sample
tHV
time
Figure 38. Overpower Compensation if the HV Pin is Connected to DC Voltage
Feedback with Slope Compensation
The ratio from the FB voltage to the current sense setpoint
is 5, meaning that the FB voltage corresponding to VILIM is
3.5 V. There is a pull−up resistor of 20 kW from FB pin to an
internal reference.
VFB(ref)
20 kW
FB
K FB
+
−
CS
PWM
blanking
tLEB
Figure 39. FB Circuitry
In order to allow the NCP1234 to operate in CCM with a
duty cycle above 50%, a fixed slope compensation is
internally applied to the current−mode control. The slope
appearing on the internal voltage setpoint for the PWM
comparator is −32.5 mV/ms typical for the 65 kHz version,
and −50 mV/ms for the 100 kHz version.
www.onsemi.com
22
NCP1234
Overcurrent protection with Fault timer
latched off (latched protection, version A), or it enters an
autorecovery mode (version B). The timer is reset when the
CS setpoint goes back below VILIM before the timer elapses.
To provide maximum output power at the low input line
voltages the fault timer is not started if the driver signal is
reset by the max duty cycle.
When an overcurrent occurs on the output of the power
supply, the FB loop asks for more power than the controller
can deliver, and the CS setpoint reaches VILIMIT. When this
event occurs, an internal tfault timer is started: once the timer
times out, DRV pulses are stopped and the controller is either
PWM
FB
+
−
/5
R
Q
S
timer
tfault
Protection
Mode
Reset DRV
release
Autorecovery
protection
mode only
blanking
CS
timer
tLEB
+
+
−
t autorec
Reset
VILIM
Figure 40. Timer−Based Overcurrent Protection
www.onsemi.com
23
NCP1234
In autorecovery mode, the controller tries to restart after tautorec. If the fault has gone, the supply resumes operation; if not,
the system starts a new burst cycle.
Fault
disappears
Output Load Overcurrent
applied
Max Load
Fault Flag
time
Fault
timer
starts
VCC
time
VCC(on)
VCC(min)
Restart
At VCC(on)
(new burst
cycle if Fault
still present)
DRV
time
Controller
stops
Fault timer
time
tfault
tfault
tautorec
Figure 41. Autorecovery Timer−Based Protection Mode
www.onsemi.com
24
time
NCP1234
In the latched version, the controller can restart only if a
VCC reset occurs, which in a real application can only
happen if the power supply is unplugged from the mains
line.
Output Load
No restart
when fault
disappears
Overcurrent
applied
Max Load
Fault Flag
time
Fault
timer
starts
VCC
time
VCC(on)
VCC(min)
DRV
time
Controller
latches off
Fault timer
time
tfault
tfault
Figure 42. Latched Timer−Based Overcurrent Protection
www.onsemi.com
25
time
NCP1234
LOW LOAD OPERATION
Frequency Foldback
VFB(foldS), and is complete before VFB reaches Vskip(in),
whatever the nominal switching frequency option is. The
current−mode control is still active while the oscillator
frequency decreases. Note that the frequency foldback is
disabled if the controller runs at its maximum duty cycle.
In order to improve the efficiency in light load conditions,
the frequency of the internal oscillator is linearly reduced
from its nominal value down to fOSC(min). This frequency
foldback starts when the voltage on FB pin goes below
fOSC
Nominal fOSC
Skip
fOSC(min)
Vskip(in)
FB
VFB(foldS)
VFB(foldE)
Figure 43. Frequency Foldback when the FB Voltage Decreases
Skip Cycle Mode
−
+
+
Vskip
S
Q
DRV stage
R
FB
KFB
CS
blanking
tLEB
+
−
Figure 44. Skip Cycle Schematic
When the FB voltage reaches Vskip(in) while decreasing,
skip mode is activated: the driver stops, and the internal
consumption of the controller is decreased. While VFB is
below Vskip(out), the controller remains in this state; but as
soon as VFB crosses the skip out threshold, the DRV pin
starts to pulse again.
www.onsemi.com
26
NCP1234
VFB
VFB(fold)
Vskip(out)
Vskip(in)
Exits
Exits
skip
Enters
Enters
skip
skip
Time
skip
DRV
Time
Figure 45. Skip Cycle Timing Diagram
Latch−off Input
VDD
+
INTC
blanking
+
−
tLatch(OVP)
VOVP
INTC
Latch
+
1 kW
−
+
S
Q
R
blanking
tLatch(OTP)
Latch
VOTP
Vclamp
Reset
Soft−start
end
Figure 46. Latch Detection Schematic
To avoid any false triggering, spikes shorter than 50 ms
(for the high latch and 65 kHz version) or 350 ms (for the low
latch) are blanked and only longer signals can actually latch
the controller.
Reset occurs when VCC is cycled down to a reset voltage,
which in a real application can only happen if the power
supply is unplugged from the AC line.
Upon start−up, the internal references take some time
before being at their nominal values; so one of the
comparators could toggle even if it should not. Therefore the
internal logic does not take the latch signal into account
before the controller is ready to start: once VCC reaches
VCC(on), the latch pin High latch state is taken into account
The Latch pin is dedicated to the latch−off function: it
includes two levels of detection that define a working
window, between a high latch and a low latch: within these
two thresholds, the controller is allowed to run; but as soon
as either the low or the high threshold is crossed, the
controller is latched off. The lower threshold is intended to
be used with an NTC thermistor, thanks to an internal current
source INTC.
An active clamp prevents the voltage from reaching the
high threshold if it is only pulled up by the INTC current. To
reach the high threshold, the pull−up current has to be higher
than the pull−down capability of the clamp (typically
1.5 mA at VOVP).
www.onsemi.com
27
NCP1234
and the DRV switching starts only if it is allowed; whereas
the Low latch (typically sensing an overtemperature) is
taken into account only after the soft−start is finished. In
addition, the NTC current is doubled to INTC(SSTART) during
the soft−start period, to speed up the charging of the Latch
pin capacitor. The maximum value of Latch pin capacitor is
given by the following formula (The standard start−up
condition is considered and the NTC current is neglected) :
C LATCHmax +
t SSTARTmin @ I NTC(SSTART)min
V clamp0min
(eq. 2)
2.8 @ 10 −3 @ 130 @ 10 −6
+
F + 364 nF
1.0
VCC
VCC(on)
VCC(min)
Start-up
initiated by
VCC(on)
Internal Latch Signal
Noise spike
ignored
(tLatch blanking)
Latch signal
high during
pre-start phase
time
time
DRV
Latch-off
Switching
allowed (no
latch event)
time
Figure 47. Latch−off Function Timing Diagram
Temperature Shutdown
instantaneously, and the HV current source is turned off.
Internal logic state is reset. When the temperature falls
below the low threshold, the HV start−up current source is
enabled, and a regular start−up sequence takes place.
The die includes a temperature shutdown protection with
a trip point guaranteed above 135°C and below 165°C, and
a typical hysteresis of 30°C. When the temperature rises
above the high threshold, the controller stops switching
www.onsemi.com
28
NCP1234
STATE DIAGRAMS
HV Start−up Current Source
VCC > VCC(inhibit)
Istart1
No TSD
Istart2
VCC < VCC(inhibit)
TSD
TSD
Stop
TSD
VCC < VCC(min)
VCC > VCC(on)
TSD
Off
Figure 48. HV Start−up Current Source State Diagram
www.onsemi.com
29
NCP1234
Controller Operation (Latched Version: A Option)
• High Latch
• VCC > VCC(ovp)
VCC > VCC(on)
Soft−start
• VCC < VCC(off )
• TSD
Soft−start ends
• TSD
Stopped
• VCC < VCC(off )
• TSD
• Fault
• VCC < VCC(off )
• TSD
Skip
• VCC reset
Skip in
Latch
• High Latch
• Low Latch
• VCC > VCC(ovp)
Skip out
Running
• VCC > VCC(ovp)
• High Latch
• Low Latch
With Fault=
• tfault expires
• VCS > VCS(stop)
Figure 49. Controller Operation State Diagram (Latched Protection)
www.onsemi.com
30
NCP1234
Controller Operation (Autorecovery Version: B Option)
• High Latch
• VCC > VCC(ovp)
VCC > VCC(on)
Soft−start
• VCC < VCC(off)
• TSD
Soft−start ends
• tautorec counting
• TSD
Stopped
• VCC < VCC(off)
• TSD
• Fault
• VCC < VCC(off)
• TSD
Skip
• VCC reset
Skip in
Latch
• High Latch
• Low Latch
• VCC > VCC(ovp)
Skip out
Running
• VCC > VCC(ovp)
• High Latch
• Low Latch
With Fault=
• tfault expires
• VCS > VCS(stop)
Figure 50. Controller Operation State Diagram (Autorecovery Protection)
www.onsemi.com
31
NCP1234
Table 1. ORDERING INFORMATION
Overload Protection
Switching Frequency
Package
Shipping†
NCP1234AD65R2G
Latched
65 kHz
SOIC−7
(Pb−Free)
2500 / Tape & Reel
NCP1234BD65R2G
Autorecovery
65 kHz
SOIC−7
(Pb−Free)
2500 / Tape & Reel
NCP1234AD100R2G
Latched
100 kHz
SOIC−7
(Pb−Free)
2500 / Tape & Reel
NCP1234BD100R2G
Autorecovery
100 kHz
SOIC−7
(Pb−Free)
2500 / Tape & Reel
Part No.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
32
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−7
CASE 751U−01
ISSUE E
DATE 20 OCT 2009
SCALE 1:1
−A−
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5
−B− S
0.25 (0.010)
B
M
M
1
4
G
C
R
X 45 _
J
−T−
SEATING
PLANE
H
0.25 (0.010)
K
M
D 7 PL
M
T B
S
A
DIM
A
B
C
D
G
H
J
K
M
N
S
INCHES
MIN MAX
0.189 0.197
0.150 0.157
0.053 0.069
0.013 0.020
0.050 BSC
0.004 0.010
0.007 0.010
0.016 0.050
0_
8_
0.010 0.020
0.228 0.244
S
GENERIC
MARKING DIAGRAM
SOLDERING FOOTPRINT*
8
1.52
0.060
7.0
0.275
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
1
XXX
A
L
Y
W
G
4.0
0.155
0.6
0.024
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
1.270
0.050
SCALE 6:1
XXXXX
ALYWX
G
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
98AON12199D
DESCRIPTION:
7−LEAD SOIC
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−7
CASE 751U−01
ISSUE E
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6.
7. NOT USED
8. EMITTER
DATE 20 OCT 2009
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. NOT USED
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. NOT USED
8. SOURCE, #1
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5.
6.
7. NOT USED
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6.
7. NOT USED
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. NOT USED
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR (DIE 1)
2. BASE (DIE 1)
3. BASE (DIE 2)
4. COLLECTOR (DIE 2)
5. COLLECTOR (DIE 2)
6. EMITTER (DIE 2)
7. NOT USED
8. COLLECTOR (DIE 1)
STYLE 9:
PIN 1. EMITTER (COMMON)
2. COLLECTOR (DIE 1)
3. COLLECTOR (DIE 2)
4. EMITTER (COMMON)
5. EMITTER (COMMON)
6. BASE (DIE 2)
7. NOT USED
8. EMITTER (COMMON)
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. NOT USED
8. GROUND
STYLE 11:
PIN 1. SOURCE (DIE 1)
2. GATE (DIE 1)
3. SOURCE (DIE 2)
4. GATE (DIE 2)
5. DRAIN (DIE 2)
6. DRAIN (DIE 2)
7. NOT USED
8. DRAIN (DIE 1)
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. NOT USED
8. COMMON CATHODE
DOCUMENT NUMBER:
98AON12199D
DESCRIPTION:
7−LEAD SOIC
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
onsemi Website: www.onsemi.com
◊
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
工商网监
湘ICP备2023018690号
