NCP1239FDR2G

NCP1239 Low−Standby High Performance PWM Controller Housed in SO−16 the NCP1239 represents a major leap toward ultra−compact Switch Mode Power Supplies specifically tailored for medium to high power off−line applications, e.g. notebook adapters. The NCP1239 offers everything needed to build a rugged and efficient power supply, including a dedicated event management to drive a Power Factor Correction (PFC) front−end circuitry. The circuit disables the front−end PFC stage while still in fault or standby conditions by interrupting the PFC controller powering for improved no−load consumption figures. As soon as normal operating mode recovers, the NCP1239 feeds back the PFC that wakes−up. When power demand is low, the IC automatically enters the so−called skip−cycle mode and provides excellent efficiency at light loads. Because this occurs at a user adjustable low peak current, no acoustic noise takes place. Features http://onsemi.com 16 1 SO−16 FD or VD SUFFIX CASE 751B MARKING DIAGRAM 16 NCP1239xDG AWLYWW 1 NCP1239xD x A WL Y WW G = Device Code = F or V = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package • • • • • • • • • • • • • • • • • • • Current−Mode Operation with Internal Ramp Compensation Internal High−Voltage Current Source for loss−less Startup Adjustable Skip−Cycle Capability Selectable Soft−Start Period Internal Frequency Dithering for Improved EMI Signature Go−to−Standby Signal for PFC Front−Stage Large VCC Operation from 12.2 V to 36 V 500 mV Overcurrent Limit 500 mA/−800 mA Peak Current Capability 5 V/10 mA Pinned−out Reference Voltage Adjustable Switching Frequency up to 250 kHz. Overload Protection Independent of the Auxiliary VCC Adjustable Over Power Compensation (NCP1239F) Programmable Maximum Duty Cycle (NCP1239V) Pb−Free Packages are Available* PIN CONNECTIONS 1 GTS REF5V Fault Detect Rt Brown−out SS/Timer Skip Adjust FB NCP1239F 1 GTS REF5V Fault Detect Rt Brown−out SS/Timer Skip Adjust FB NCP1239V 16 16 HV NC NC VCC Drv GND CS Over Power Limit Typical Applications High Power AC/DC Adapters for Notebooks etc. Offline Battery Chargers Telecom and PC Power Supplies Flyback Applications (NCP1239F) and Forward Applications (NCP1239V) HV NC NC VCC Drv GND CS Max Duty− Cycle *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. 1 October, 2005 − Rev. 5 Publication Order Number NCP1239/D NCP1239 Vbulk Rbo1 to PFC_VCC OVP REF5V NTC Thermistor + 1 REF5V (5V/10mA) 2 3 15 14 13 12 11 Rramp 7 8 Rt Cbo Css NCP1239F + 10 9 Rcomp VCC GND 16 Vout + Cbulk BO 4 5 6 Rbo2 GND Figure 1. NCP1239F Typical Application Example Vbulk Rbo1 to PFC_VCC D3 L2 OVP REF5V NTC Thermistor D4 1 REF5V (5V/10mA) 2 3 15 14 13 12 11 10 9 NCP1239V Rdmax Cbo Css + Rramp VCC 16 + Vout GND + Cbulk BO 4 5 6 Rbo2 7 8 Rt GND Figure 2. NCP1239V Typical Application Example http://onsemi.com 2 NCP1239 MAXIMUM RATINGS Rating Power Supply Voltage Pins 1 to 10 (except Vref Pin) Maximum Voltage Maximum Voltage on Pin 16 (HV) Thermal Resistance, Junction−to−Air, SOIC Version Maximum Junction Temperature Storage Temperature Range ESD Capability, HBM Model (All Pins except HV) ESD Capability Machine Model (All Pins except VCC) Machine Model (VCC Pin) RqJA TJMAX Symbol VCC Value 36 −0.3, +10 500 145 150 −60 to +150 2 200 160 Unit V V V °C/W °C °C kV V Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Vpin16 = 48 V, VCC = 20 V unless otherwise noted.) Symbol Supply Section VCCON VCCOFF HYST1 VCCLATCH VCCRESET ICC1 Turn−on Threshold Level, VCC Going up Minimum Operating Voltage after Turn−on Difference (VCCON − VCCOFF) VCC Decreasing Level at which the Latch−off Phase ends VCC Level at which the Internal Logic gets reset Internal IC Consumption, no output load on Pin 12 (@IRt = 20 mA) NCP1239F NCP1239V Internal IC Consumption, 1 nF output load on Pin 12 NCP1239F (65 kHz) NCP1239V (118 kHz) Internal IC Consumption, 1 nF output load on Pin 12 NCP1239F (100 kHz) NCP1239V (182 kHz) Internal IC Consumption, 1 nF output load on Pin 12 NCP1239F (130 kHz) NCP1239V (236 kHz) Internal IC Consumption, latchoff phase (NCP1239F and NCP1239V) 13 13 13 13 13 13 − − 13 − − 13 − − 13 − − 13 − 0.40 0.75 4.6 6.7 5.9 9.6 mA 3.9 5.5 5.0 8.5 mA 3.1 4.2 3.8 6.5 mA 2.1 2.6 3.0 4.0 mA 15.5 10.5 4.5 6.5 − 16.4 11.2 5.1 6.9 4.0 17.5 12.2 − 7.2 − V V V V V mA Rating Pin Min Typ Max Unit ICC2a ICC2b ICC2c ICC3 Internal Startup Current Source IC1_hv IC1_VCC IC2 High−Voltage Current Source (sunk by Pin 16), VCC = 10 V Startup Charge Current flowing out of the VCC Pin, VCC=10 V High−Voltage Current Source, VCC = 0 16 13 16 2.0 1.8 − 4.0 3.6 4.2 5.3 4.5 − mA mA mA 5 V Reference Voltage (REF5V) REF5V Reference Voltage @ No load on Pin 2 @ Ipin2 = 5 mA Current Capability 2 4.7 4.6 2 5.0 5.0 4.9 10 5.2 5.1 − mA V Iref http://onsemi.com 3 NCP1239 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Vpin16 = 48 V, VCC = 20 V unless otherwise noted.) Symbol Drive Output Vcl Trise Tfall Vsource Isource ROL Isink Oscillator fsw Vosc Kosc Recommended Switching Frequency Range Pin 4 Voltage @ Rt = 100 kW Product (Switching Frequency times the Rt Pin 4 resistance) (Note 1) @ 65 kHz and 130 kHz (NCP1239F) @ 118 kHz and 236 kHz (NCP1239V) Internal Modulation Swing, in percentage of fsw Maximum Duty−Cycle 12 4 25 − 6050 11000 − 75.5 − 1.6 6500 11800 ±3.5 80.0 250 − 6950 12600 − 83.0 % % kHz V kHz*kW Output Voltage Positive Clamp Output Voltage Rise−Time @ CL = 1 nF, 10−90% of output signal Output Voltage Fall−Time @ CL = 1 nF, 10−90% of output signal High State Voltage Drop @ Ipin12 = 3 mA and VCC = 12 V Source Current Capability (@ Vpin12 = 0 V) Sink Resistance @ Vpin12 =1 V Sink Current Capability (@ Vpin12 = 10 V) 12 12 12 12 12 12 12 11.5 − − − − − − 13.6 40 25 2.5 500 3.8 800 16 − − 3.3 − 7.5 − V ns ns V mA W mA Rating Pin Min Typ Max Unit Dfsw Dmax Current Limitation ILimit TDEL_CS TLEB−65kHz TLEB−130kHz TLEB−118kHz TLEB−236kHz Maximum Internal Set−Point Propagation Delay from Vpin10 > ILimit to gate turned off (Pin 12 loaded by 1 nF) Leading Edge Blanking Duration (Pins 9 and 10) @ 65 kHz (NCP1239F) Leading Edge Blanking Duration (Pins 9 and 10) @ 130 kHz (NCP1239F) Leading Edge Blanking Duration (Pin 10) @ 118 kHz (NCP1239V) Leading Edge Blanking Duration (Pin 10) @ 236 kHz (NCP1239V) 10 10 9, 10 9, 10 10 10 0.84 − − − − − 0.90 130 420 230 320 170 0.95 220 − − − − V ns ns ns ns ns mA 60 120 9 0.48 0.47 9 − 0.50 0.50 130 0.52 0.52 220 ns 80 160 100 185 V Over Power Limit (NCP1239F) Iocp Internal Current Source of the Over Power Limit Pin @ 1 V on Pin 5 and Vpin9 = 0.5 V @ 2 V on Pin 5 and Vpin9 = 0.5 V Over Power Limitation Threshold @ TJ = 25°C @ TJ = 0°C to 125°C Propagation Delay from Vpin9 > Vopl to gate turned off (Pin 12 loaded by 1 nF) 9 Vopl TDEL_OCP Maximum Duty−Cycle (Dmax) Control (NCP1239V) IDmax Dmax KDmax Pin 9 Current Source @ Vpin9 = 1.0 V and Vpin9 = 2.0 V Maximum Duty Cycle @ 118 kHz and Vpin9 = 1.0 V Dmax Coefficient @ 118 kHz and Vpin9 = 1.0 V (Note 2) 9 9 9 46 20 1.10 55 24 1.30 63 29 1.53 mA % %/kW 1. The nominal switching frequency fsw equals: fsw = KOSC/Rt. The implemented jittering makes the switching frequency continuously vary around this nominal value ($3.5% variation). 2. KDmax is the proportionality coefficient that links the maximum duty−cycle to the Pin 9 resistor: Dmax = KDmax*Rpin9. KDmax is defined in the “Maximum Duty−Cycle Limitation” section of the operating description. http://onsemi.com 4 NCP1239 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Vpin16 = 48 V, VCC = 20 V unless otherwise noted.) Symbol Soft−Start and Timer Ich Idisch Vjitter VjitterH VtimerL ItimerC ItimerD Rup Ifb Iratio Soft−Start or Jittering charge current @ Vpin6 = 2.4 V Jittering Discharge Current @ Vpin6 = 2.4 V Jittering Saw−Tooth Lower Threshold Jittering Saw−Tooth Upper Threshold Timer Peak Threshold Timer Charge Current @ Vpin6 = 3.5 V and Pin 8 open Timer Discharge Current @ Vpin6 = 3.5 V and Pin 8 open Internal Pullup Resistor Source Current @ Vpin8 = 0.5 V Pin 8 to current Setpoint division ratio 6 6 6 6 6 6 6 60 77 1.67 2.85 4.0 3.9 − 95 107 1.80 3.00 4.3 5.2 400 110 137 1.89 3.20 4.6 6.4 − mA mA V V V mA mA kW mA − kW V kW mA mV mV − kW − Rating Pin Min Typ Max Unit Feedback Section 8 8 − − − − 20 200 3.0 − − − Internal Ramp Compensation Rramp Vramp Rgts Igts FB−skip FB_stby−out Vstby−out/Vskip Rpin7 Internal Resistor Internal Saw−Tooth Amplitude 10 10 − − 32 3.2 − − Skipping Mode and Standby Management Pin 1 output impedance in standby state (Pin 8 grounded, Vpin6 > 4.5 V) @ VCC = 12.5 V Sink Current Source in Normal Mode @ Vpin8 = 2 V, Pin 7 open @ VCC − Vpin1=0.7 V Default Feedback Level for Skip−Cycle Operation and Standby Detection Default Feedback Level to Leave Standby Ratio leave standby Setpoint to skip−cycle Setpoint Internal Pin 7 Impedance Pin 7 to Skipping Setpoint ratio Brown−Out Detection BOthH BOthL BOhyst Protections TSD Thermal Shutdown: Thermal Shutdown Threshold Hysteresis Fault Detection Threshold 3 2.2 °C 140 30 2.4 2.6 V Brown−Out Detection Upper Threshold Brown−Out Detection Low Threshold Brown−Out Hysteresis 5 5 5 0.45 0.20 0.20 0.50 0.24 0.26 0.55 0.28 0.30 V V V 7 1 1 7 7 4.0 0.6 380 650 1.5 − − 8.0 1.0 430 740 1.7 110 3.0 18 − 480 810 1.9 − − Vfault ORDERING INFORMATION Device NCP1239FDR2 NCP1239FDR2G NCP1239VDR2 NCP1239VDR2G Package SOIC−16 SOIC−16 (Pb−Free) SOIC−16 SOIC−16 (Pb−Free) Shipping † 2500 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NCP1239 PIN FUNCTION DESCRIPTION Pin No. 1 Pin Name GTS Function Shuts the PFC down in standby A 5V reference voltage Pin Description The standby detection block changes Pin 1 state in accordance to the mode (standby or normal mode). Pin1 is designed to drive an external pnp transistor that connects or disconnects the NCP1239’s VCC to the PFC’s. This pin helps to internally bias the controller but can also be used to power surrounding logic gates for any purposes. The typical output current is 10 mA. This voltage source is disabled during the circuit startup and latched−off phases. A 100 nF filtering capacitor must be placed between Pin 2 and ground. If the Pin 3 voltage exceeds 2.4 V, the circuit is permanently shut down. This pin can be used to monitor the voltage across a thermistor in order to protect the application from excessive heating and/or to detect an overvoltage condition. Pin 4 resistor allows a precise frequency programming. The circuit is optimized to operate between 50 kHz and 150 kHz (NCP1239F) and between 100 kHz and 250 kHz (NCP1239V). This pin receives a portion of the bulk capacitor to authorize operation above a certain level of mains only. It also serves to elaborate an offset voltage on Pin 9 used for Over Power Compensation. During Power on and fault conditions, the capacitor connected to this pin ensures a soft−start period. When a fault is detected, this pin is internally brought high by a current source. If 4.3 V are reached, the fault is confirmed and the circuit enters an auto−recovery burst mode, otherwise the pin goes back to a lower value and oscillates to perform frequency jittering. By adjusting the skip−cycle level, it is possible to fight against noisy transformers and modify the standby detection thresholds. Keep Pin 7 open to operate with the default levels (skip threshold setpoint: 140 mV, normal mode recovery setpoint: 250 mV). An opto−coupler collector pulls this pin low to regulate This pin delivers a current proportional to Vpin5, an image of the high voltage rail. Inserting a resistor between Pin 9 and the current sense resistor, an offset proportional to the input voltage is built. Such offset compensates the circuit and power switch propagation delays for an accurate power limitation in the whole input voltage range. This terminal sources a constant current. Connect a resistor between Pin 9 and Ground to select the maximum duty−cycle. This pin receives the primary current information via a sense element. By inserting a resistor in series with this pin, it becomes possible to introduce ramp compensation. − By offering up to +500 mA/−800 mA peak, this pin lets you drive large Qg MOSFET’s. It is clamped to 16 V maximum not to exceed the maximum gate−source voltage of most power MOSFET’s. This pin accepts up to 36 V from an auxiliary winding. Creepage distance. Creepage distance. This pin connects to the bulk capacitor to generate the startup current. 2 REF5V 3 Fault Detect Enables to permanently shutdown the part Timing resistor 4 Rt 5 Brown−Out Brown−Out 6 SS/Timer Performs soft−start and fault timeout 7 Skip Adjust Adjust skip level 8 9 FB Over Power Limit (NCP1239F) Feedback signal Enables a precise peak current clamp and then an accurate Over Power Detection Enables to precisely clamp the maximum duty−cycle. The current sense input 9 Max Duty− Cycle (NCP1239V) CS 10 11 12 Ground Drv The IC ground Drives the MOSFET 13 14 15 16 VCC NC NC HV Supplies the controller − − The high−voltage startup http://onsemi.com 6 NCP1239 FB Skip high + Skip 7 adjust 100k + FB 450mV 15r + 25r − FB>1.6*Vpin1 =>Stby_detect RESET Fault detect Internal Thermal Shutdown UVLO TSD 3 2.5V Vcc R 10k PFC_Vcc 1 pfcON 1mA Stby Vdd Vdd R OVL Divider by 2 Stby_detect SS / timer 6 Soft−Start and timer management Error_Flag OUTon Soft−Start Ipk limit REF5V 2 + 5V Jittering Modulation 14V clamp Ramp Compensation pfcON 32k 11 CLK BO_in BO 5 + 0.5V / 0.25V Vdd Vstop Vdd BO_in Oscillator Rt 4 2.5V − + Skip Jittering Modulation Vdd 20k FB 8 to Skip /3 0.9V Soft−Start Ipk limit Error flag “Jittered” Reference − + − + 0.5V + LEB CLK 75 mA/V x Vpin5 9 Over Power Limit − + BO_out GND Output Buffer 12 Drv VccStby_detect RESET Fault detect Internal Thermal Shutdown UVLO TSD 3 2.5V Vcc R 10k PFC_Vcc 1 pfcON 1mA Stby Vdd Vdd R OVL Divider by 2 Stby_detect SS / timer 6 Soft−Start and timer management Error_Flag OUTon Soft−Start Ipk limit REF5V 2 + 5V Jittering Modulation 14V clamp Ramp Compensation pfcON 32k 11 CLK BO_in BO 5 + 0.5V / 0.25V Vdd Vstop − + BO_out GND Output Buffer 12 Drv Vcc3, 35/V(bulk), 0) } bulk line timing Rupper 2.4Meg V1 V2 + − cmp BrownOut Rlower 10k Cfil 220n 5 Bbrown Voltage V(CMP) > 3, 250m : 500m V2 timing 0 PWL 0 0.2 3s 1 7s 1 10s 0.2 V1 line 0 SIN 0 150 50 PSpice: EBbrown Value = { IF ( V(CMP) > 3, 250m, 0) } A simple simulation configuration helps to tailor the right value for Cfil Figure 46. 200 16.0 Turn− voltage occurs at: off VinRMS = 72.3 volts 100 12.0 0 8.0 −100 4.0 Vbrown− out −200 0 8.156 8.175 8.195 8.215 8.235 Typical signals obtained from the simulator Figure 47. http://onsemi.com 27 NCP1239 Rectified AC Line Sensing to converter PFC Preconverter Input filtering Capacitor Rupper + Cbulk Rlower Cfil 5 ac line A second option to directly sense the mains Figure 48. This second option that directly senses the input voltage (see Figure 48), enables a more direct under−mains detection. Even in a brown−out conditions, the PFC pre−converter may be able to maintain a sufficient bulk voltage, possibly at the price of some excessive stress. Measuring the rectified AC line instead of the bulk voltage, the NCP1239 more surely protects the PFC stage in brown−out conditions. Using: − Rlower = 10 kW, − Rupper = 2. 39 MW, − Cfil = 1 mF, One obtains the following voltage thresholds: − Vtrip = 85 Vrms, − VBO = 65 Vrms. Over Power Limit (NCP1239F) Overload conditions may push the converter to draw an excessive power (which generally increases versus the input voltage). One must avoid such a behavior: a) not to have to dimension the converter for a power higher than the nominal one, b) to meet SMPS specifications that often request the power not to exceed a given level. In addition, it is not recommended to provide the output with more power than normally necessary. To the light of these statements, it becomes interesting to accurately limit the amount of power drawn from the AC line in fault conditions. The easiest way to do so consists of clamping the peak current since in a discontinuous mode flyback converter, the input power (Pin) can be calculated as follows: Pin = 1/2 * Lp * Ippk2 * fsw, where Lp is the primary inductor, Ippk is the inductor peak current and fsw is the switching frequency. Practically, a sense resistor converts the primary current into a voltage that is compared to a voltage reference. When the voltage representative of the current exceeds the voltage reference, the controller turns off the power switch. The theoretical maximum peak current is then: Imax = Vocp/Rsense, where Vocp is the reference voltage (or overcurrent protection threshold) and Rsense is the sense resistor. Unfortunately, the controller cannot turn off the power switch immediately when it detects that the current exceeds its maximum permissible level. Internal propagation delays differ the drive turn low. In addition, the power switch needs some time to turn off. Finally, the real current stop can be 250ns or more delayed. During this time, the current continues ramping up so that an overcurrent is obtained. http://onsemi.com 28 NCP1239 Actual Peak Current DIHL Low Input Voltage DILL High Input Voltage Vopl/Rsense Wished Maximum Peak Current Dt Dt The propagation delay (Dt) produces overcurrents (DILL at low line, DIHL at high line in the figure) that are proportional to the input voltage. As a consequence, the actual maximum current and then the power limit gets higher when the AC line increases. Figure 49. I max + Vocp ) Vin @ dt , where Vin is the converter Rsense Lp Then, Ipth + Vopl * (Rcomp @ 80 mA V @ kBO @ Vin) Rsense input voltage and Dt is the total delay in turning off the power switch. The NCP1239 enables the compensation of the second term in the Imax equation for a precise limitation of the peak current. A current source (Ipin9) proportional to the Pin 5 voltage flows out of Pin 9. Since Pin 5 receives a voltage proportional to the input voltage for brown−out detection, Ipin9 is proportional to the input voltage too. An external resistor Rcomp can be connected between Pin 9 and the positive terminal of Rsense, so that Pin 9 monitors the following voltage: Vpin9 + [Rsense @ (Ip ) Ipin9)] ) (Rcomp @ Ipin9) Taking into account the overcurrent resulting from the propagation delays, the maximum current is finally: I max + Rcomp @ 80 mA V @ kBO @ Vin Vin @ dt Vocp * ) Rsense Rsense Lp Choosing Rcomp so that Rcomp @ 80 mA V @ kBO ) dt , Rsense Lp Ipin9 being small compared to the inductor current, the Pin 9 voltage simplifies as follows: Vpin9 + (Rsense @ Ip) ) (Rcomp @ Ipin9) the current limit is made constant in the whole input voltage range (Imax = Vocp/Rsense). As an example, let’s assume that: − the minimum input voltage for operation is 100 V => kBO=0.5/100=0.005, − Rsense is 0.25 W, − Lp=500 mH, − The total propagation delays are Dt = 350 ns, Then, the Rcomp resistor should be: Rcomp + dt @ Rsense + 350 n @ 0.25 [ 438 W . 80 m @ 0.005 @ 500 m 80 m @ kBO @ Lp Ipin9 is proportional to the Pin 5 voltage (80 mA/V*Vpin5 – see parameters specification table) and Vpin5 is a portion of the input voltage (Vpin5 = kBO*Vin). Finally, Ipin9 + 80 mA V @ kBO @ Vin The voltage Vpin9 is compared to the internal reference Vocp. When Vpin9 reaches Vocp, the corresponding threshold current (Ipth) is deducted from: Vopl + (Rsense @ Ipth) ) (Rcomp @ 80 mA V @ kBO @ Vin) http://onsemi.com 29 NCP1239 CLK PWM Latch 80mA/V*V pin5 Q Q R to Brown−Out Comparator Vdd Vpin5 5 Brown−Out Cbo Rbo2 Rbo1 Vin S Vcomp = k*Rcomp*Vpin5 Rcomp + − + 0.5V to Current Sense Comparator LEB 9 Over Power Limit Vcomp Rsense Rramp 10 Current Sense An (averaged) portion of the input voltage is applied to the brown−out pin. A current source proportional to this voltage, flows through an external resistor Rcomp to form an offset proportional to the (average) input voltage. Rcomp should be selected so that the offset compensates the overcurrent sensed by the current sensing resistor Rsense. Figure 50. NCP1239F Maximum Duty Cycle Limitation (NCP1239V) Pin 9 sources a 55 mA current. By placing a resistor between this pin and ground, one builds a voltage that forces the maximum on−time. Practically the Pin 9 voltage is compared to the positive ramp of the internal oscillator and the power switch is allowed to be on, only when the ramp is below Vpin9. Then the maximum on−time is given by: (ton)max + Cosc @ Vpin9 Iosc Vpin9 being the product of the Pin 9 current by the Pin 9 resistance (Rpin9 – external resistor connected to Pin 9), results in: (ton)max + Cosc @ IDmax @ Rpin9 , where IDmax is the Iosc Pin 9 current source. One can deduct the maximum duty cycle (Dmax) by dividing by the period T: Dmax + Cosc @ IDmax @ Rpin9 + KDmax @ Rpin9 Iosc @ T Cosc @ IDmax . Iosc @ T where Cosc and Iosc are respectively the capacitor and the charging current of the oscillator. where KDmax + KDmax is specified within the parameters’ table. Please note that Cosc and Iosc are the internal capacitor and current (respectively), that set the switching period (T). Hence, Cosc Iosc @ T is a constant and KDmax is independent of the switching frequency. In the NCP1239F, the maximum duty−cycle is fixed (80% typically). http://onsemi.com 30 NCP1239 Soft−Start The NCP1239 features an internal soft−start activated during the Power On sequence (PON). As soon as VCC reaches 16.4 V, the current setpoint is gradually increased from nearly zero up to the maximum clamping level (e.g. 0.9 V/Rsense). This situation lasts a programmable time that is adjusted by the Pin 6 capacitor (7.5 ms typically with Cpin6 = 390 nF). Further to that time period, the current setpoint is blocked to 0.9 V/Rsense until the supply enters regulation. The soft−start is also activated at each start of the active phase of fault burst operation. Every restart attempt is followed by a soft−start activation. Generally speaking, the soft−start will be activated when VCC ramps up either from zero (fresh power−on sequence) or 6.9 V, the latch−off threshold after an overload detection (OVL) for instance. Figure 51 shows the soft−start behavior. The time scales are purposely shifted to offer a better zoom portion. 16.4V 6.9V Soft−start is activated during a startup sequence or an OVL condition Figure 51. Inserting a resistor in series with the current sense information brings ramp compensation Figure 52. http://onsemi.com 31 + Internal Ramp Compensation Ramp compensation is a known mean to cure sub−harmonic oscillations. These oscillations take place at half the switching frequency and occur only during Continuous Conduction Mode (CCM) with a duty−cycle greater than 50%. To lower the current loop gain, one usually injects between 50 and 100% of the inductor down−slope. Figure 52 depicts how internally the ramp is generated: 3.2V 0V 32k Rramp LEB CS Rsense − from setpoint NCP1239 In the NCP1239, the ramp features a swing of 3.2 V. Suppose we select a 65 kHz version. Over a 65 kHz frequency, it corresponds to a 130 mV/ms ramp. In our FLYBACK design, let’s assume that our primary inductance Lp is 350 mH, and the SMPS delivers 12 V with a Np:Ns ratio of 1:0.1. The OFF time slope of the primary current is: (Vout ) Vf) @ Ns Lp Np The ramp is disabled during standby (i.e., when pfcON is low). This inhibition avoids that the ramp compensation modifies the setpoint above which the NCP1239 enables PFC. Frequency Jittering Frequency jittering is a method used to soften the EMI signature by spreading the energy in the vicinity of the main switching component. NCP1239 offers a +3.5% deviation of the nominal switching frequency. The sweep saw−tooth is internally generated and modulates the clock up and down with a period depending on the Pin 6 capacitor (10 ms typically with 390 nF, 10 mS * Cpin6 / 390 nF in general). Again, if one selects a 65 kHz version, the frequency will equal 65 kHz in the middle of the ripple and will increase as Vpin6 rises or decrease as Vpin6 ramps down. Figure 53 portrays the behavior we have adopted: that is, 371 mA/ms or 37 mV/ms, once projected over a 0.1 W Rsense for instance. If we select 75% of the down−slope as the required amount of ramp compensation, then we shall inject 27 mV/ms. Our internal compensation being of 208 mV/ms, the divider ratio (divratio) between Rramp and the 32 kW is 0.178. A few lines of algebra to determine Rramp: 19 k @ divratio Rramp + + 6.92 kW. (1 * divratio) Internal ramp 67.6kHz 65kHz 62.4kHz 10ms Internal sawtooth The Vpin6 ramp is used to introduce frequency jittering on the oscillator saw−tooth Figure 53. http://onsemi.com 32 NCP1239 Skipping Cycle Mode The NCP1239 automatically skips switching cycles when the output power demand drops below a given level. This is accomplished by monitoring the FB pin. In normal operation, Pin 8 imposes a current setpoint accordingly to the load value. If the load demand decreases, the internal loop asks for less peak current. When this setpoint reaches a fixed determined level, the IC prevents the current from decreasing further down and starts to blank the output pulses: the IC enters the so−called skip−cycle mode, also named controlled burst operation. The default skip−cycle current is internally frozen to 30% of the maximum peak current which is 0.5 V/Rsense The power transfer now depends upon the width of the pulse bunches (Figure 54). FB Pin Voltage 4.3 V, FB Pin open 2.7 V upper dynamic range Normal current mode operation 0.43 V Skip−cycle operation Ip MIN = 150 mV/Rsense Suppose we have the following component values: Lp, primary inductance = 350 mH fsw , switching frequency = 65 kHz Ip skip = 600 mA (or 140 mV/Rsense) The theoretical power transfer is therefore: 1/2 * Lp * Ip2 * fsw = 4 W If this IC enters skip−cycle mode with a bunch length of 10 ms over a recurrent period of 100 ms, then the total power transfer is: 4 W * 10 ms/100 ms = 400 mW To better understand how this skip−cycle mode takes place, a look at the operation mode versus the FB level immediately gives the necessary insight: Figure 54. When FB is below the skip−cycle threshold (0.43 V by default), the circuit skips the switching cycle. When the IC enters the skip−cycle mode, the peak current cannot go below (0.43 V/3)/Rsense or 140 mV/Rsense. Figure 55 shows different values of pulse widths when the SMPS starts to skip−cycles at different power levels: Power P1 Power P2 Power P3 Output pulses at various power levels (X = 5ms/div) P1 < P2 < P3 Figure 55. http://onsemi.com 33 NCP1239 Max peak current 300.0M 200.0M 25% of max Ip 100.0M 0 315.4U 882.7U 1.450M 2.017M 2.585M The skip−cycle takes place at low peak currents which guaranties noise free operation Figure 56. PFC Inhibition in Standby The circuit detects a light load condition by permanently monitoring the skip−cycle comparator activity: in normal load condition this comparator keeps quiet. As soon as the load strongly decreases, this comparator starts to toggle at a low frequency rate: we are entering skip−cycle and the opto−coupler operates in a digital manner, ON/OFF. Figure 56 shows the way skip−cycle is detected. In skip mode, the feedback voltage oscillates around Vpin7 (If no voltage is applied to the Pin 7, a 430 mV voltage source supplies a default value through a high impedance resistor). In these conditions, the skip comparator (“COMP1”) that turns on and off (to adjust the skip mode bunches of pulses), sets the standby detection latch. A second comparator (“COMP2”) compares the feedback voltage (FB or Vpin8) to 1.7*Vpin7. As long as the load keeps light, FB does not exceed 1.7*Vpin7 (i.e., 0.74 V typical if no voltage is forced to Pin 7). A timer counts down and if COMP2 keeps high for 100 ms (typically with 390 nF on Pin 6), the NCP1239 considers that the system runs in the standby mode. Pin 1 turns high, a 10 kW resistor tying the pin to VCC. If as shown in Figure 39, Pin 1 directly drives a pnp transistor that is connected between VCC and the PFC VCC, this switch turns off in standby. As a result, this transistor stops feeding the PFC VCC and ultimately shuts the PFC down. As soon as FB exceeds 1.7*Vpin7, the circuit leaves the standby mode without any delay by forcing a 1 mA sinking current source on Pin 1, that re−activates the pnp transistor and then the PFC stage. One can note that there is a 1/3 ratio between the actual current setpoint and the feedback value FB. Therefore the default thresholds for standby detection and normal mode recovery (0.43 V, 0.74 V) actually corresponds to the 140 mV and 250 mV setpoints. 70% A delay is inserted to avoid false tripping of the GTS signal Figure 57. http://onsemi.com 34 NCP1239 One clearly sees that the GTS signal does not react to the fugitive low FB Pin condition during startup Figure 58. REF5V FB < Vpin7 => Skip high + Skip R1 Skip Adjust 7 100k + 0.43V FB 15r 25r − COMP1 S Q Q + − COMP2 R Stby_detect R2 FB > 1.7 * Vpin7 => Stby_detect RESET GTS pin1 100 ms timer (*) (SS and timer block) (*) the 100 ms delay is programmed by the Pin 6 capacitor Internal Go−To−Standby signal elaboration Figure 59. Suppose our Flyback controller is built with a transformer primary inductance of 250 mH. To pass 120 W, we assume that a peak current of 4.2 A was needed. Due to these numbers, we can easily now when the GTS signal will be asserted: Lp, primary inductance = 250 mH h = 85% fsw, switching frequency = 65 kHz Ip + 2 @ Pout + 4.2 A h @ Lp @ fsw The theoretical region at which the SMPS will enter standby is: 1/2 * Lp * Ip2 * fsw * h  11 W. This number can vary depending on the line level since the propagation delay becomes a sensitive parameter, and on the efficiency that is difficult to precisely predict in light load conditions. The peak current at which the SMPS will leave standby is 48% of the peak current which means that a power of 28 W is necessary to re−trigger the PFC. Ip skip = 30% of Ip max = 1.26 A http://onsemi.com 35 NCP1239 INFORMATIVE WAVEFORMS The following plots were obtained using a 150 W application (output 19 V/7 A). The NCP1239 enables the PFC VCC as soon as the FB pin voltage has gone below a threshold (about 2.7 V), that is when the internal error flag stops being asserted. Figure 60. Startup Sequence The feedback voltage goes high and asserts the internal error flag. The Pin 6 timer counts for about 100 ms (Cpin6 = 390 ns) before shutting down the SMPS. One “VCC cycle over two is skipped” to limit the duty cycle in overload. Figure 61. Overload Conditions http://onsemi.com 36 NCP1239 When the load current falls to a low level (CH4), the FB pin voltage diminishes to take into account the decay of the power demand. As a consequence, the FB pin voltage goes below the “Vskip” threshold and the soft start timer counts about 100 ms (if Cpin6 = 330 nF). When the 100 ms time has elapsed, the PFC VCC stops being fed. Figure 62. Transition Normal to Standby When the load current increases from 1A to 5A, the FB pin increases too so that the supplied power matches the new demand. The normal mode is recovered without delay. Figure 63. Transition Standby to Normal http://onsemi.com 37 NCP1239 PACKAGE DIMENSIONS SO−16 FD SUFFIX CASE 751B−05 ISSUE J −A− 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 −B− 1 8 P 8 PL 0.25 (0.010) M B S G F K C −T− SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S The product described herein (NCP1239), may be covered by one or more of the following U.S. patents: 6,362,067, 6,385,060, 6,429,709. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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