NCP1250BSN65T1G

NCP1250 PWM Controller, Current Mode, for Offline Power Supplies The NCP1250 is a highly integrated PWM controller capable of delivering a rugged and high performance offline power supply in a tiny TSOP−6 or PDIP−8 package. With a supply range up to 28 V, the controller hosts a jittered 65 kHz or 100 kHz switching circuitry operated in peak current mode control. When the power on the secondary side starts to decrease, the controller automatically folds back its switching frequency down to a minimum level of 26 kHz. As the power further goes down, the part enters skip cycle while limiting the peak current. Over Power Protection (OPP) is a difficult exercise especially when no−load standby requirements drive the converter specifications. The ON proprietary integrated OPP lets you harness the maximum delivered power without affecting your standby performance simply via two external resistors. An Over Voltage Protection input is also combined on the same pin and protects the whole circuitry in case of optocoupler failure or adverse open loop operation. Finally, a timer−based short−circuit protection offers the best protection scheme, letting you precisely select the protection trip point irrespective of a loose coupling between the auxiliary and the power windings. Features • Fixed−Frequency 65 or 100 kHz Current−Mode Control Operation • Internal and Adjustable Over Power Protection (OPP) Circuit • Frequency Foldback Down to 26 kHz and Skip−Cycle in Light Load • • • • • • • • • • • Conditions Internal Ramp Compensation Internal Fixed 4 ms Soft−Start 100 ms Timer−Based Auto−Recovery Short−Circuit Protection Frequency Jittering in Normal and Frequency Foldback Modes Option for Auto−Recovery or Latched Short−Circuit Protection OVP Input for Improved Robustness Up to 28 V VCC Operation +300 mA/−500 mA Source/Sink Drive Capability Less than 100 mW Standby Power at High Line EPS 2.0 Compliant These are Pb−Free Devices Typical Applications • ac−dc Converters for TVs, Set−top Boxes and Printers • Offline Adapters for Notebooks and Netbooks www.onsemi.com MARKING DIAGRAMS TSOP−6 (SOT23−6) SN SUFFIX CASE 318G 1 25xAYWG G 1 PDIP−8 SUFFIX P Case 626 25x x y A WL Y, YY W, WW G or G 125xy65 AWL YYWWG = Specific Device Code = A, 2, C, D, 0, 1 = A or B = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS GND 1 6 DRV FB 2 5 VCC OPP/Latch 3 4 CS TSOP−6 (Top View) GND 1 8 OPP/LATCH DRV 2 7 N/C N/C 3 6 FB VCC 4 5 CS PDIP−8 (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. © Semiconductor Components Industries, LLC, 2015 April, 2015 − Rev. 10 1 Publication Order Number: NCP1250/D NCP1250 Vbulk Vo u t . . OVP OPP . NCP1250 1 6 2 5 3 4 ramp comp. Figure 1. Typical Application Example (TSOP−6) PIN DESCRIPTION Pin N5 PDIP−8 TSSOP−6 Pin Name 1 1 GND − 6 2 FB Feedback pin Hooking an optocoupler collector to this pin will allow regulation. 8 3 OPP/OVP Adjust the Over Power Protection Latches off the part A resistive divider from the auxiliary winding to this pin sets the OPP compensation level. When brought above 3 V, the part is fully latched off. 5 4 CS Current sense + ramp compensation This pin monitors the primary peak current but also offers a means to introduce ramp compensation. 4 5 VCC Supplies the controller This pin is connected to an external auxiliary voltage and supplies the controller. 2 6 DRV Driver output Function Pin Description The controller ground. The driver’s output to an external MOSFET gate. OPTIONS Controller Frequency OCP Latched NCP1250ASN65T1G 65 kHz Yes No NCP1250BSN65T1G 65 kHz No Yes NCP1250ASN100T1G 100 kHz Yes No NCP1250BSN100T1G 100 kHz No Yes NCP1250BP65G 65 kHz No Yes www.onsemi.com 2 OCP Auto−Recovery NCP1250 ORDERING INFORMATION Package Marking OCP Protection Switching Frequency Package Shipping† NCP1250ASN65T1G 25A Latch 65 kHz NCP1250BSN65T1G 252 Autorecovery 65 kHz TSOP−6 (Pb−Free) 3000 / Tape & Reel NCP1250ASN100T1G 25C Latch 100 kHz NCP1250BSN100T1G 25D Autorecovery 100 kHz 1250B65 Autorecovery 65 kHz PDIP−8 (Pb−Free) 50 Units / Rail Device NCP1250BP65G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Vcc and logic management OPP 600−ns time constant vdd power on reset IpFlag Up counter Vlatch OVP gone? UVLO hiccup RST 4 S Q Rlim Q vdd R Power on reset Frequency modulation Vcc Iscr 1−us blanking 65 100 kHz clock Clamp S Q Q R Frequency foldback Drv Vfold Vskip Rramp vdd 4 ms SS The soft−start is activated during: RFB IpFlag − the startup sequence − the auto−recovery burst mode / 4.2 VFB < 1.05 V ? setpoint = 250 mV FB VOPP CS LEB 250 mV peak current freeze Vlimit + VOPP + GND Vlimit Figure 2. Internal Circuit Architecture www.onsemi.com 3 NCP1250 MAXIMUM RATINGS TABLE Symbol VCC VDRVtran Rating Value Unit 28 V Maximum DRV pin voltage when DRV in H state, transient voltage (Note 1) VCC + 0.3 V Maximum voltage on low power pins CS, FB and OPP −0.3 to 10 V Power Supply voltage, VCC pin, continuous voltage IOPP Maximum injected negative current into the OPP pin −2 mA ISCR Maximum continuous current in to the VCC Pin while in latched mode 3 mA RqJA Thermal Resistance Junction−to−Air 360 °C/W TJ,max Maximum Junction Temperature Storage Temperature Range ESD Capability, Human Body Model (HBM), all pins ESD Capability, Machine Model (MM) ESD Capability, Charged Device Model (CDM) 150 °C −60 to +150 °C 2 kV 200 V 1 kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The transient voltage is a voltage spike injected to DRV pin being in high state. Maximum transient duration is 100 ns. 2. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per JESD22, Method A114E. Machine Model Method 200 V per JESD22, Method A115A. Charged Device Model per JEDEC Standard JESD22−C101D 3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. www.onsemi.com 4 NCP1250 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol Rating Min Typ Max Unit VCC increasing level at which driving pulses are authorized 16 18 20 V VCC(min) VCC decreasing level at which driving pulses are stopped 8.2 8.8 9.4 V VCCHYST Hysteresis VCCON − VCC(min) 6.0 SUPPLY SECTION − (For the best efficiency performance, we recommend a VCC below 20 V) VCCON VZENER 7.0 Clamped VCC when latched off / burst mode activation @ ICC = 500 mA ICC1 Start−up current ICC2 Internal IC consumption with IFB = 50 mA, FSW = 65 kHz and CL = 0 nF ICC3 V V 15 mA 1.4 2.2 mA Internal IC consumption with IFB = 50 mA, FSW = 65 kHz and CL = 1 nF 2.1 3.0 mA ICC2 Internal IC consumption with IFB = 50 mA, FSW = 100 kHz and CL = 0 nF 1.7 2.5 mA ICC3 Internal IC consumption with IFB = 50 mA, FSW = 100 kHz and CL = 1 nF 3.1 4.0 mA ICCLATCH ICCstby Rlim Current flowing into VCC pin that keeps the controller latched (Note 4) TJ = −40°C to +125°C TJ = 0°C to +125°C mA 40 32 Internal IC consumption while in skip cycle (VCC = 12 V, driving a typical 6 A/600 V MOSFET) 550 mA Current−limit resistor in series with the latch SCR 4.0 kW DRIVE OUTPUT Tr Output voltage rise−time @ CL = 1 nF, 10−90% of output signal 40 ns Tf Output voltage fall−time @ CL = 1 nF, 10−90% of output signal 30 ns ROH Source resistance 13 W ROL Sink resistance 6.0 W Peak source current, VGS = 0 V – (Note 5) 300 mA Peak sink current, VGS = 12 V – (Note 5) 500 mA Isource Isink VDRVlow DRV pin level at VCC close to VCC(min) with a 33 kW resistor to GND 8.0 VDRVhigh DRV pin level at VCC = 28 V – DRV unloaded 10 V 12 14 V CURRENT COMPARATOR IIB Input Bias Current @ 0.8 V input level on CS Pin 0.02 mA VLimit1 Maximum internal current setpoint – TJ = 25°C – OPP/Latch Pin grounded 0.744 0.8 0.856 V VLimit2 Maximum internal current setpoint – TJ = −40°C to 125°C – OPP/Latch Pin grounded 0.72 0.8 0.88 V Vfold Default internal voltage set point for frequency foldback trip point – 45% of Vlimit 357 mV Internal peak current setpoint freeze ([31% of Vlimit) 250 mV TDEL Propagation delay from current detection to gate off−state 100 TLEB Leading Edge Blanking Duration 300 ns TSS Internal soft−start duration activated upon startup, auto−recovery 4.0 ms IOPPo Setpoint decrease for the OPP/Latch pin biased to –250 mV – (Note 6) 31.3 % IOOPv Voltage setpoint for the OPP/Latch pin biased to −250 mV – (Note 6), TJ = 25°C 0.51 0.55 0.60 V IOOPv Voltage setpoint for the OPP/Latch pin biased to −250 mV – (Note 6), TJ = −40°C to 125°C 0.50 0.55 0.62 V IOPPs Setpoint decrease for the OPP/Latch pin grounded Vfreeze 150 0 ns % INTERNAL OSCILLATOR fOSC Oscillation frequency (65 kHz version) 61 65 71 kHz fOSC Oscillation frequency (100 kHz version) 92 100 108 kHz www.onsemi.com 5 NCP1250 ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol Rating Min Typ Max Unit 76 80 84 % INTERNAL OSCILLATOR Dmax Maximum duty−cycle fjitter Frequency jittering in percentage of fOSC ±5 % fswing Swing frequency 240 Hz FEEDBACK SECTION Rup Internal pull−up resistor 20 kW Req Equivalent ac resistor from FB to GND 16 kW Iratio FB Pin to current setpoint division ratio 4.2 Feedback voltage below which the peak current is frozen 1.05 V 1.5 V Vfreeze FREQUENCY FOLDBACK Vfold Frequency folback level on the feedback pin – [45% of maximum peak current Ftrans Transition frequency below which skip−cycle occurs Vfold,end End of frequency foldback feedback leve, Fsw = Fmin 350 mV Vskip Skip−cycle level voltage on the feedback pin 300 mV Skip hysteresis Hysteresis on the skip comparator – (Note 5) 30 mV 22 26 30 kHz INTERNAL SLOPE COMPENSATION Vramp Internal ramp level @ 25°C – (Note 7) 2.5 V Rramp Internal ramp resistance to CS pin 20 kW PROTECTIONS Vlatch Latching level input 2.7 3.0 Tlatch−blank Blanking time after drive turn off 1.0 Tlatch−count Number of clock cycles before latch confirmation 4.0 OVP detection time constant 600 Tlatch−del Timer Internal auto−recovery fault timer duration 100 130 3.3 V ms ns 160 ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. For design robustness, we recommend to inject 60 mA as a minimum at the lowest input line voltage. 5. Guaranteed by design 6. See characterization table for linearity over negative bias voltage 7. A 1 MW resistor is connected from OPP/Latch Pin to the ground for the measurement. www.onsemi.com 6 NCP1250 TYPICAL CHARACTERISTICS 72 85 84 70 83 68 81 FSW (kHz) Dmax (%) 82 80 79 78 77 66 64 62 76 75 −50 −25 0 25 50 75 100 60 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 3. Figure 4. 31 100 125 100 125 100 125 440 30 29 390 F_swing (Hz) Ftrans (kHz) 28 27 26 25 24 23 −25 0 25 50 75 100 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 5. Figure 6. 490 0.87 440 0.85 FSW = 65 kHz 390 VLskip (mV) 0.83 Vlimit (mV) 240 140 −50 125 0.89 0.81 0.79 0.77 340 290 240 0.75 190 0.73 0.71 −50 290 190 22 21 −50 340 −25 0 25 50 75 100 140 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. Figure 8. www.onsemi.com 7 NCP1250 TYPICAL CHARACTERISTICS 44 0.6 39 34 IOOPV (V) IOOPO (%) 0.58 29 24 19 −50 −25 0 25 50 75 100 0.5 −50 125 25 50 75 Figure 9. Figure 10. 100 125 100 125 100 125 9.5 9.3 18.9 9.1 18.4 17.9 17.4 8.9 8.7 8.5 16.9 8.3 16.4 −25 0 25 50 75 100 8.1 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. Figure 12. 14 16 13 14 12 12 ICC1 (mA) 11 10 9 8 10 8 6 7 4 6 2 5 −50 0 TEMPERATURE (°C) 19.4 15.9 −50 −25 TEMPERATURE (°C) VCC(min) (V) VCC(ON) (V) 0.54 0.52 19.9 VCC(Hyst) (V) 0.56 −25 0 25 50 75 100 0 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. Figure 14. www.onsemi.com 8 NCP1250 TYPICAL CHARACTERISTICS 2.5 2 FSW = 65 kHz 2 ICC3 (mA) ICC2 (mA) 1.5 1 0.5 0 −50 FSW = 65 kHz 1.5 1 0.5 −25 0 25 50 75 100 0 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Figure 16. 100 125 100 125 100 125 30 10 25 ICCLatch (mA) Vzener (V) 8 6 4 2 0 −50 −25 0 25 50 75 100 10 0 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. Figure 18. 160 140 340 120 Req (kW) 290 Tleb (V) 15 5 390 240 190 100 80 60 40 140 90 −50 20 20 −25 0 25 50 75 100 0 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 19. Figure 20. www.onsemi.com 9 NCP1250 TYPICAL CHARACTERISTICS 4.8 3.4 3.3 4.6 3.2 Vlatch (V) Iratio (−) 4.4 4.2 4 3.1 3 2.9 2.8 3.8 −25 0 25 50 75 100 2.6 −50 125 0 25 50 75 TEMPERATURE (°C) Figure 21. Figure 22. 100 100 80 80 60 40 100 125 100 125 100 125 60 40 20 20 0 −50 −25 TEMPERATURE (°C) tfall (ns) trise (ns) 3.6 −50 2.7 −25 0 25 50 75 100 0 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 23. Figure 24. 11 35 10 30 9 25 7 Roh (W) Rol (W) 8 6 5 15 4 10 3 2 −50 20 −25 0 25 50 75 100 5 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 25. Figure 26. www.onsemi.com 10 NCP1250 TYPICAL CHARACTERISTICS 14 100 13 12 Vdrv_low (V) Vovp_del (ms) 80 60 40 11 10 9 20 0 −50 8 −25 0 25 50 75 100 7 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 27. Figure 28. 12.9 100 125 100 125 100 125 4.9 12.4 4.4 11.4 TSS (ms) Vdrv_high (V) 11.9 10.9 10.4 9.9 3.9 3.4 9.4 8.9 −50 −25 0 25 50 75 100 2.9 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 29. Figure 30. 1.9 360 1.8 358 1.6 Vfold(CS) (mV) Vfold(FB) (V) 1.7 1.5 1.4 356 354 1.3 352 1.2 1.1 −50 −25 0 25 50 75 100 350 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 31. Figure 32. www.onsemi.com 11 NCP1250 TYPICAL CHARACTERISTICS 0.41 390 340 0.37 Vskip (mV) Vfold_end (V) 0.39 0.35 0.33 240 0.31 0.29 −50 −25 0 25 50 75 100 190 −50 125 50 75 Figure 34. 100 125 100 125 1.7 1.5 Vfreeze(FB) (V) Vfreeze (mV) 25 TEMPERATURE (°C) 290 240 1.3 1.1 0.9 −25 0 25 50 75 100 0.7 −50 125 25 50 75 TEMPERATURE (°C) Figure 36. 3.5 150 3 140 2.5 130 2 120 1.5 110 1 100 0.5 0 0 Figure 35. 160 −25 −25 TEMPERATURE (°C) ICC (mA) TIMER (ms) 0 Figure 33. 340 90 −50 −25 TEMPERATURE (°C) 390 190 −50 290 25 50 75 100 0 125 FSW = 65 kHz 0 0.5 1 1.5 2 2.5 3 TEMPERATURE (°C) ADAPTER OUTPUT CURRENT (A) Figure 37. Figure 38. Controller Consumption vs. Adapter Output Current www.onsemi.com 12 3.5 NCP1250 APPLICATION INFORMATION Introduction The NCP1250 implements a standard current mode architecture where the switch−off event is dictated by the peak current setpoint. This component represents the ideal candidate where low part−count and cost effectiveness are the key parameters, particularly in low−cost ac−dc adapters, open−frame power supplies etc. Capitalizing on the NCP120X series success, the NCP1250 packs all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as a non−dissipative OPP. • Current−mode operation with internal ramp compensation: Implementing peak current mode control at a fixed 65 kHz or 100 kHz, the NCP1250 offers an internal ramp compensation signal that can easily by summed with the sensed current. Sub harmonic oscillations are eliminated via the inclusion of a single resistor in series with the current−sense information. • Internal OPP: By routing a portion of the negative voltage present during the on−time on the auxiliary winding to the dedicated OPP pin, the user has a simple and non−dissipative means to alter the maximum peak current setpoint as the bulk voltage increases. If the pin is grounded, no OPP compensation occurs. If the pin receives a negative voltage down to –250 mV, then a peak current reduction down to 31.3% typical can be achieved. For an improved performance, the maximum voltage excursion on the sense resistor is limited to 0.8 V. • Low startup current: Achieving a low no−load standby power always represents a difficult exercise when the controller draws a significant amount of current during start−up. Due to its proprietary architecture, the NCP1250 is guaranteed to draw less than 15 mA typical, easing the design of low standby power adapters. • EMI jittering: An internal low−frequency modulation signal varies the pace at which the oscillator frequency is modulated. This helps by spreading out energy in conducted noise analysis. To improve the EMI signature at low power levels, the jittering remains active in frequency foldback mode. • Frequency foldback capability: A continuous flow of pulses is not compatible with no−load/light−load standby power requirements. To excel in this domain, the controller observes the feedback pin and when it • • • reaches a level of 1.5 V, the oscillator then starts to reduce its switching frequency as the feedback level continues to decrease. When the feedback pin reaches 1.05 V, the peak current setpoint is internally frozen and the frequency continues to decrease. It can go down to 26 kHz (typical) reached for a feedback level of roughly 350 mV. At this point, if the power continues to drop, the controller enters classical skip−cycle mode. Internal soft−start: A soft−start precludes the main power switch from being stressed upon start−up. In this controller, the soft−start is internally fixed to 4 ms. The soft−start is activated when a new startup sequence occurs or during an auto−recovery hiccup. OVP input: The NCP1250 includes a latch input Pin that can be used to sense an overvoltage condition on the adapter. If this pin is brought higher than the internal reference voltage Vlatch, then the circuit permanently latches off. The VCC pin is pulled down to a fixed level, keeping the controller latched. The latch reset occurs when the user disconnects the adapter from the mains and lets the VCC falls below the VCC reset. Short−circuit protection: Short−circuit and especially over−load protections are difficult to implement for transformers with high leakage inductance between auxiliary and power windings (the aux winding level does not properly collapse in presence of an output short). Here, every time the internal 0.8 V maximum peak current limit is activated (or less when OPP is used), an error flag is asserted and a time period starts, thanks to an internal timer. If the timer reaches completion while the error flag is still present, the controller stops the pulses and goes into a latch−off phase, operating in a low−frequency burst−mode. When the fault is cleared, the SMPS resumes operation. Please note that some versions offer an auto−recovery mode as described and some latch off in case of a short circuit. Start−up Sequence The NCP1250 start−up voltage is made purposely high to permit a large energy storage in a small VCC capacitor value. This helps to operate with a small start−up current which, together with a small VCC capacitor, will not hamper the start−up time. To further reduce the standby power, the start−up current of the controller is extremely low, below 15 mA maximum. The start−up resistor can therefore be connected to the bulk capacitor or directly to the mains input voltage to further reduce the power dissipation. www.onsemi.com 13 NCP1250 R3 200k 3 10 R2 200k 5 D2 1N4007 D1 1N4007 11 12 R1 200k Cbulk 22uF input mains D6 1N4148 1 D5 1N4935 VCC D4 1N4007 D3 1N4007 2 C1 4.7uF 4 aux. C3 47uF Figure 39. The Startup Resistor Can Be Connected to the Input Mains for Further Power Dissipation Reduction The first step starts with the calculation of the VCC capacitor which will supply the controller when it operates until the auxiliary winding takes over. Experience shows that this time t1 can be between 5 ms and 20 ms. If we consider we need at least an energy reservoir for a t1 time of 10 ms, the VCC capacitor must be larger than: CV CC w I CCt 1 VCC on * VCC min 3m w 10m 9 This calculation is purely theoretical, and assumes a constant charging current. In reality, the take over time can be shorter (or longer!) and it can lead to a reduction of the VCC capacitor. Hence, a decrease in charging current and an increase of the start−up resistor, thus reducing the standby power. Laboratory experiments on the prototype are thus mandatory to fine tune the converter. If we chose the 413 kW resistor as suggested by Equation 4, the dissipated power at high line amounts to: w 3.3 mF (eq. 1) Let us select a 4.7 mF capacitor at first and experiments in the laboratory will let us know if we were too optimistic for the time t1. The VCC capacitor being known, we can now evaluate the charging current we need to bring the VCC voltage from 0 to the VCCon of the IC, 18 V typical. This current has to be selected to ensure a start−up at the lowest mains (85 V rms) to be less than 3 s (2.5 s for design margin): I charge w VCC onC VCC 2.5 w 18 4.7m 2.5 w 34 mA P Rstart*up + + I CVCC,min + p * VCC on (eq. 2) (eq. 3) R start*up To make sure this current is always greater than 49 mA, then the minimum value for Rstart−up can be extracted: V ac,rmsǸ2 R start*up v p * VCC on I CVCC,min 85 v 1.414 p * 18 49m 2 4R start*up 230 2 0.827Meg + ǒ230 4 Ǹ2Ǔ 413k 2 (eq. 5) + 64 mW Now that the first VCC capacitor has been selected, we must ensure that the self−supply does not disappear when in no−load conditions. In this mode, the skip−cycle can be so deep that refreshing pulses are likely to be widely spaced, inducing a large ripple on the VCC capacitor. If this ripple is too large, chances exist to touch the VCCmin and reset the controller into a new start−up sequence. A solution is to grow this capacitor but it will obviously be detrimental to the start−up time. The option offered in Figure 39 elegantly solves this potential issue by adding an extra capacitor on the auxiliary winding. However, this component is separated from the VCC pin via a simple diode. You therefore have the ability to grow this capacitor as you need to ensure the self−supply of the controller without jeopardizing the start−up time and standby power. A capacitor ranging from 22 to 47 mF is the typical value for this device. One note on the start-up current. If reducing it helps to improve the standby power, its value cannot fall below a certain level at the minimum input voltage. Failure to inject If we account for the 15 mA that will flow inside the controller, then the total charging current delivered by the start−up resistor must be 49 mA. If we connect the start−up network to the mains (half−wave connection then), we know that the average current flowing into this start−up resistor will be the smallest when VCC reaches the VCCon of the controller: V ac,rmsǸ2 V ac,peak v 413.5 kW (eq. 4) www.onsemi.com 14 NCP1250 enough current (30 mA) at low line will turn a converter in fault into an auto-recovery mode since the SCR won’t remain latched. To build a sufficient design margin, we recommend to keep at least 60 mA flowing at the lowest input line (80 V rms for 85 V minimum for instance). An excellent solution is to actually combine X2 discharge and start-up networks as proposed in Figure 13 of application note AND8488/D. the current−sense offset. A way to reduce the power capability at high line is to capitalize on the negative voltage swing present on the auxiliary diode anode. During the power switch on−time, this point dips to −NVin, N being the turns ratio between the primary winding and the auxiliary winding. The negative plateau observed on Figure 41 will have an amplitude dependant on the input voltage. The idea implemented in this chip is to sum a portion of this negative swing with the 0.8 V internal reference level. For instance, if the voltage swings down to −150 mV during the on time, then the internal peak current set point will be fixed to 0.8 − 0.150 = 650 mV. The adopted principle appears in Figure 41 and shows how the final peak current set point is constructed. Internal Over Power Protection There are several known ways to implement Over Power Protection (OPP), all suffering from particular problems. These problems range from the added consumption burden on the converter or the skip−cycle disturbance brought by 1 v(24) 40.0 off−time 20.0 N1(Vout +Vf) v(24) (V) 1 0 −20.0 −N2Vbulk on−time −40.0 464u 472u 480u time (s) 488u 496u Figure 40. The Signal Obtained on the Auxiliary Winding Swings Negative During the On−time Let’s assume we need to reduce the peak current from 2.5 A at low line, to 2 A at high line. This corresponds to a 20% reduction or a set point voltage of 640 mV. To reach this level, then the negative voltage developed on the OPP pin must reach: V OPP + 640m * 800m + −160 mV www.onsemi.com 15 (eq. 6) NCP1250 RoppU swings to: Vout during toff −N V in during ton VCC aux This p oin t will be adjusted to reduce the ref at hi line to the desired level. from FB OPP K1 SUM2 ref CS K2 + Io p p reset − VDD 0.8 V $5% R oppL ref = 0.8 V + VOPP (V O P P is negativ e) Figure 41. The OPP Circuitry Affects the Maximum Peak Current Set Point by Summing a Negative Voltage to the Internal Voltage Reference Let us assume that we have the following converter characteristics: Vout = 19 V Vin = 85 to 265 Vrms N1 = Np:Ns = 1:0.25 N2 = Np:Naux = 1:0.18 Given the turns ratio between the primary and the auxiliary windings, the on−time voltage at high line (265 Vac) on the auxiliary winding swings down to: V aux + −N 2V in,max + −0.18 375 + −67.5 V Div + 0.16 [ 2.4m 67.5 (eq. 8) If we arbitrarily fix the pull−down resistor ROPPL to 1 kW, then the upper resistor can be obtained by: R OPPU + 67.5 * 0.16 0.16ń1k [ 421 kW (eq. 9) If we now plot the peak current set point obtained by implementing the recommended resistor values, we obtain the following curve (Figure 42): (eq. 7) To obtain a level as imposed by Equation 6, we need to install a divider featuring the following ratio: Peak current setpoint 100% 80% 375 Vbulk Figure 42. The Peak Current Regularly Reduces Down to 20% at 375 Vdc clamped slightly below –300 mV which means that if more current is injected before reaching the ESD forward drop, then the maximum peak reduction is kept to 40%. If the voltage finally forward biases the internal zener diode, then care must be taken to avoid injecting a current beyond –2 mA. Given the value of ROPPU, there is no risk in the present example. The OPP pin is surrounded by Zener diodes stacked to protect the pin against ESD pulses. These diodes accept some peak current in the avalanche mode and are designed to sustain a certain amount of energy. On the other side, negative injection into these diodes (or forward bias) can cause substrate injection which can lead to an erratic circuit behavior. To avoid this problem, the pin is internally www.onsemi.com 16 NCP1250 Finally, please note that another comparator internally fixes the maximum peak current set point to 0.8 V even if the OPP pin is inadvertently biased above 0 V. foldback and reduces its switching frequency. The peak current setpoint follows the feedback pin until its level reaches 1.05 V. Below this value, the peak current freezes to Vfold/4.2 (250 mV or 31% of the maximum 0.8 V setpoint) and the only way to further reduce the transmitted power is to reduce the operating frequency down to 26 kHz. This value is reached at a voltage feedback level of 350 mV typically. Below this point, if the output power continues to decrease, the part enters skip cycle for the best noise−free performance in no−load conditions. Figure 43 depicts the adopted scheme for the part. Frequency Foldback The reduction of no−load standby power associated with the need for improving the efficiency, requires a change to the traditional fixed−frequency type of operation. This controller implements a switching frequency foldback when the feedback voltage passes below a certain level, Vfold, set around 1.5 V. At this point, the oscillator enters frequency Frequency Peak current setpoint Fsw FB VCS max 65 kHz 26 kHz max 0.8 V [ 0.36 V min 350 mV 1.5 V Vfold Vfold,end 3.4 V [ 0.25 V VFB min Vfreeze Vfold 1.05 V 1.5 V 3.4 V VFB Figure 43. By Observing the Voltage on the Feedback Pin, the Controller Reduces its Switching Frequency for an Improved Performance at Light Load Auto−Recovery Short−Circuit Protection due to the resistive starting network. When VCC reaches VCCON, the controller attempts to re−start, checking for the absence of the fault. If the fault is still there, the supply enters another cycle of so−called hiccup mode. If the fault has cleared, the power supply resumes normal operation. Please note that the soft−start is activated during each of the re−start sequence. In case of output short−circuit or if the power supply experiences a severe overloading situation, an internal error flag is raised and starts a countdown timer. If the flag is asserted longer than 100 ms, the driving pulses are stopped and the VCC pin slowly goes down to around 7 V. At this point, the controller wakes−up and the VCC builds up again www.onsemi.com 17 NCP1250 15.9 4.32 14.8 9.90 3.35 6.05 vcc in volts 23.6 3.89 ilprim in amperes Plot1 vdrv in volts 1 vcc 2 vdrv 3 ilprim 1 Vcc (t) VDRV (t) 2.38 2 −2.72 −2.12 1.41 ILp (t) SS −11.5 −8.13 445m 500u 1.50m 2.50m time in seconds 3.50m 3 4.50m Figure 44. An Auto−Recovery Hiccup Mode is Activated for Faults Longer than 100 ms Slope Compensation converters. These oscillations take place at half the switching frequency and occur only during CCM with a duty−cycle greater than 50%. To lower the current loop gain, one usually injects between 50% and 100% of the inductor downslope. Figure 45 depicts how internally the ramp is generated. Please note that the ramp signal will be disconnected from the CS pin, during the off time. The NCP1250 includes an internal ramp compensation signal. This is the buffered oscillator clock delivered only during the on time. Its amplitude is around 2.5 V at the maximum duty−cycle. Ramp compensation is a known means used to cure sub harmonic oscillations in Continuous Conduction Mode (CCM) operated current−mode 2.5 V 0V ON latch reset 20k + Rcomp LEB CS − Rsense from FB setpoint Figure 45. Inserting a Resistor in Series with the Current Sense Information Brings Ramp Compensation and Stabilizes the Converter in CCM Operation. In the NCP1250 controller, the oscillator ramp features a 2.5 V swing reached at a 80% duty−ratio. If the clock operates at a 65 kHz frequency, then the available oscillator slope corresponds to: S ramp + V ramp,peak D maxT SW + 0.8 2.5 15m + 208 kVńs or 208 mVńms www.onsemi.com 18 (eq. 10) NCP1250 Latching Off the Controller In our flyback design, let’s assume that our primary inductance Lp is 770 mH, and the SMPS delivers 19 V with a Np :Ns ratio of 1:0.25. The off−time primary current slope Sp is thus given by: The OPP pin not only allows a reduction of the peak current set point in relationship to the line voltage, it also offers a means to permanently latch−off the part. When the part is latched−off, the VCC pin is internally pulled down to around 7 V and the part stays in this state until the user cycles the VCC down and up again, e.g. by un−plugging the converter from the mains outlet. It is important to note that the SCR maintains its latched state as long as the injected current stays above the minimum value of 30 mA. As the SCR delatches for an injected current below this value, it is the designer duty to make sure the injected current is high enough at the lowest input voltage. Failure to maintain a sufficiently high current would make the device auto recover. A good design practice is to ensure at least 60 mA at the lowest input voltage. The latch detection is made by observing the OPP pin by a comparator featuring a 3 V reference voltage. However, for noise reasons and in particular to avoid the leakage inductance contribution at turn off, a 1 ms blanking delay is introduced before the output of the OVP comparator is checked. Then, the OVP comparator output is validated only if its high−state duration lasts a minimum of 600 ns. Below this value, the event is ignored. Then, a counter ensures that 4 successive OVP events have occurred before actually latching the part. There are several possible implementations, depending on the needed precision and the parameters you want to control. The first and easiest solution is the additional resistive divider on top of the OPP one. This solution is simple and inexpensive but requires the insertion of a diode to prevent disturbing the OPP divider during the on time. N Sp + ǒVout ) VfǓ Nps Lp + (19 ) 0.8) 4 770m + 103 kAńs (eq. 11) Given a sense resistor of 330 mW, the above current ramp turns into a voltage ramp of the following amplitude: S sense + S pR sense + 103k 0.33 (eq. 12) + 34 kVńs or 34 mVńms If we select 50% of the downslope as the required amount of ramp compensation, then we shall inject a ramp whose slope is 17 mV/ms. Our internal compensation being of 208 mV/ms, the divider ratio (divratio) between Rcomp and the internal 20 kW resistor is: divratio + 17m + 0.082 208m (eq. 13) The series compensation resistor value is thus: R comp + R ramp @ divratio + 20k 0.082 [ 1.6 kW (eq. 14) A resistor of the above value will then be inserted from the sense resistor to the current sense pin. We recommend adding a small capacitor of 100 pF, from the current sense pin to the controller ground for an improved immunity to the noise. Please make sure both components are located very close to the controller. D2 1N4148 R3 5k 11 RoppU 421k VCC 9 OP P C1 100p aux. winding 4 10 8 1 ROPPL 1k 5 Vlatch OPP OVP Figure 46. A Simple Resistive Divider Brings the OPP Pin Above 3 V in Case of a VCC Voltage Runaway above 18 V First, calculate the OPP network with the above equations. Then, suppose we want to latch off our controller when Vout exceeds 25 V. On the auxiliary winding, the plateau reflects the output voltage by the turns ratio between the power and the auxiliary winding. In case of voltage runaway for our 19 V adapter, the plateau will go up to: V aux,OVP + 25 0.18 + 18 V 0.25 (eq. 15) Since our OVP comparator trips at a 3 V level, across the 1 kW selected OPP pulldown resistor, it implies a 3 mA current. From 3 V to go up to 18 V, we need an additional www.onsemi.com 19 NCP1250 margin. A 100 pF capacitor can be added between the OPP pin and GND to improve noise immunity and avoid erratic trips in presence of external surges. Do not increase this capacitor too much otherwise the OPP signal will be affected by the integrating time constant. A second solution for the OVP detection alone, is to use a Zener diode wired as recommended by. 15 V. Under 3 mA and neglecting the series diode forward drop, it requires a series resistor of: R OVP + V latch * V VOP V OVPńR OPPL + 18 * 3 3ń1k + 15 + 5 kW 3m (eq. 16) In nominal conditions, the plateau establishes to around 14 V. Given the divide−by−6 ratio, the OPP pin will swing to 14/6 = 2.3 V during normal conditions, leaving 700 mV D3 15V D2 1N4148 11 ROPPU 421k VCC OPP 8 aux. winding 4 10 C1 22pF 9 1 ROPPL 1k 5 Vlatch OPP OVP Figure 47. A Zener Diode in Series with a Diode Helps to Improve the Noise Immunity of the System probe connections!) and check that enough margin exists to that respect. For this configuration to maintain an 18 V level, we have selected a 15 V Zener diode. In nominal conditions, the voltage on the OPP pin is almost 0 V during the off time as the Zener is fully blocked. This technique clearly improves the noise immunity of the system compared to that obtained from a resistive string as in Figure 46. Please note the reduction of the capacitor on the OPP pin to 10 pF − 22 pF. This capacitor is necessary because of the potential spike coupling through the Zener parasitic capacitance from the bias winding due to the leakage inductance. Despite the 1 ms blanking delay at turn off. This spike is energetic enough to charge the added capacitor C1 and given the time constant, could make it discharge slower, potentially disturbing the blanking circuit. When implementing the Zener option, it is important to carefully observe the OPP pin voltage (short Over Temperature Protection In a lot of designs, the adapter must be protected against thermal runaways, e.g. when the temperature inside the adapter box increases above a certain value. Figure 48 shows how to implement a simple OTP using an external NTC and a series diode. The principle remains the same: make sure the OPP network is not affected by the additional NTC hence the presence of this isolation diode. When the NTC resistance decreases as the temperature increases, the voltage on the OPP pin during the off time will slowly increase and, once it passes 3 V for 4 consecutive clock cycles, the controller will permanently latch off. www.onsemi.com 20 NCP1250 NT C D2 1N4148 ROPPU 841k VCC au x. winding OP P ROPPL 2.5k full−latch Vlatch OPP Figure 48. The Internal Circuitry Hooked to OPP/Latch Pin Can Be Used to Implement Over Temperature Protection (OTP) Back to our 19 V adapter, we have found that the plateau voltage on the auxiliary diode was 13 V in nominal conditions. We have selected an NTC which offers a resistance of 470 kW at 25°C and drops to 8.8 kW at 110°C. If our auxiliary winding plateau is 14 V and we consider a 0.6 V forward drop for the diode, then the voltage across the NTC in fault mode must be: V NTC + 14 * 3 * 0.6 + 10.4 V limit at the chosen output power level. Suppose we need a 200 mV decrease from the 0.8 V set point and the on−time swing on the auxiliary anode is −67.5 V, then we need to drop over ROPPU a voltage of: V ROPPU + 67.5 * 0.2 + 67.3 V The current flowing in the pulldown resistor ROPPL in this condition will be: (eq. 17) Based on the 8.8 kW NTC resistor at 110 °C, the current through the device must be: I NTC + 10.4 8.8k [ 1.2 mA I ROPPU + 3 + 2.5 kW 1.2m 200m 2.5k + 80 mA (eq. 21) The ROPPU value is therefore easily derived: (eq. 18) R OPPU + As such, the bottom resistor ROPPL, can easily be calculated: R OPPL + (eq. 20) 67.3 + 841 kW 80m (eq. 22) Combining OVP and OTP The OTP and Zener−based OVP can be combined together as illustrated by Figure 49. (eq. 19) Now that the pulldown OPP resistor is known, we can calculate the upper resistor value ROPPU to adjust the power www.onsemi.com 21 NCP1250 D3 15V D2 1N4148 NT C 11 ROPPU 841k VCC 9 OPP 10 8 au x. winding 4 ROPPL 2.5k 1 5 OVP Vlatch OPP Figure 49. With the NTC Back in Place, the Circuit Nicely Combines OVP, OTP and OPP on the Same Pin Zener diode and the series diode. To prevent an adverse triggering of the Over Voltage Protection circuitry, it is possible to install a small RC filter before the detection network. Typical values are those given in Figure 50 and must be selected to provide the adequate filtering function without degrading the stand−by power by an excessive current circulation. In nominal VCC / output conditions, when the Zener is not activated, the NTC can drive the OPP pin and trigger the adapter in case of an over temperature. During nominal temperature if the loop is broken, the voltage runaway will be detected and the controller will shut down the converter. In case the OPP pin is not used for either OPP or OVP, it can simply be grounded. Filtering the Spikes The auxiliary winding is the seat of spikes that can couple to the OPP pin via the parasitic capacitances exhibited by the D3 15V ad d ition al fil ter D2 1N4148 NT C 11 2 C1 330pF ROPPU 841k VCC R3 220 9 3 aux. winding OP P 10 4 ROPPL 2.5k 1 5 Vlatch OVP OPP Figure 50. A Small RC Filter Avoids the Fast Rising Spikes from Reaching the Protection Pin of the NCP1250 in Presence of Energetic Perturbations Superimposed on the Input Line www.onsemi.com 22 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE V 1 SCALE 2:1 D H ÉÉ ÉÉ 6 E1 1 NOTE 5 5 2 L2 4 GAUGE PLANE E 3 L b SEATING PLANE C DETAIL Z e DIM A A1 b c D E E1 e L L2 M c A 0.05 M DATE 12 JUN 2012 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 2: PIN 1. EMITTER 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. BASE 2 6. COLLECTOR 2 STYLE 3: PIN 1. ENABLE 2. N/C 3. R BOOST 4. Vz 5. V in 6. V out STYLE 4: PIN 1. N/C 2. V in 3. NOT USED 4. GROUND 5. ENABLE 6. LOAD STYLE 5: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 6: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 7: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. N/C 5. COLLECTOR 6. EMITTER STYLE 8: PIN 1. Vbus 2. D(in) 3. D(in)+ 4. D(out)+ 5. D(out) 6. GND STYLE 9: PIN 1. LOW VOLTAGE GATE 2. DRAIN 3. SOURCE 4. DRAIN 5. DRAIN 6. HIGH VOLTAGE GATE STYLE 10: PIN 1. D(OUT)+ 2. GND 3. D(OUT)− 4. D(IN)− 5. VBUS 6. D(IN)+ STYLE 11: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1/GATE 2 STYLE 12: PIN 1. I/O 2. GROUND 3. I/O 4. I/O 5. VCC 6. I/O STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 STYLE 14: PIN 1. ANODE 2. SOURCE 3. GATE 4. CATHODE/DRAIN 5. CATHODE/DRAIN 6. CATHODE/DRAIN STYLE 15: PIN 1. ANODE 2. SOURCE 3. GATE 4. DRAIN 5. N/C 6. CATHODE STYLE 16: PIN 1. ANODE/CATHODE 2. BASE 3. EMITTER 4. COLLECTOR 5. ANODE 6. CATHODE STYLE 17: PIN 1. EMITTER 2. BASE 3. ANODE/CATHODE 4. ANODE 5. CATHODE 6. COLLECTOR GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 XXXAYWG G 1 6X 3.20 XXX A Y W G 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB14888C TSOP−6 1 IC 0.95 XXX MG G = Specific Device Code =Assembly Location = Year = Work Week = Pb−Free Package STANDARD XXX = Specific Device Code M = Date Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PDIP−8 CASE 626−05 ISSUE P DATE 22 APR 2015 SCALE 1:1 D A E H 8 5 E1 1 4 NOTE 8 b2 c B END VIEW TOP VIEW WITH LEADS CONSTRAINED NOTE 5 A2 A e/2 NOTE 3 L SEATING PLANE A1 C D1 M e 8X SIDE VIEW b 0.010 eB END VIEW M C A M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY. 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). DIM A A1 A2 b b2 C D D1 E E1 e eB L M INCHES MIN MAX −−−− 0.210 0.015 −−−− 0.115 0.195 0.014 0.022 0.060 TYP 0.008 0.014 0.355 0.400 0.005 −−−− 0.300 0.325 0.240 0.280 0.100 BSC −−−− 0.430 0.115 0.150 −−−− 10 ° MILLIMETERS MIN MAX −−− 5.33 0.38 −−− 2.92 4.95 0.35 0.56 1.52 TYP 0.20 0.36 9.02 10.16 0.13 −−− 7.62 8.26 6.10 7.11 2.54 BSC −−− 10.92 2.92 3.81 −−− 10 ° NOTE 6 GENERIC MARKING DIAGRAM* STYLE 1: PIN 1. AC IN 2. DC + IN 3. DC − IN 4. AC IN 5. GROUND 6. OUTPUT 7. AUXILIARY 8. VCC XXXXXXXXX AWL YYWWG XXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98ASB42420B PDIP−8 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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