NCP1256BSN65T1G

Low Power Offline PWM Current Mode Controller with Brown-Out Protection NCP1256 The NCP1256 includes everything to build cost−effective switch mode power supplies ranging from a few watts up to several tens of watts. Housed in a tiny TSOP−6 package, the part can be supplied up to 30 V. It hosts a jittered 65 or 100−kHz switching circuitry operated in peak current mode control. When the power in the secondary side starts decreasing, the controller automatically folds back its switching frequency down to a minimum level of 26 kHz. As the power further goes down, the part enters skip cycle while freezing the peak current. NCP1256 comes with several protection features such as a timer−based auto−recovery short circuit protection, lossless OPP, and an easily adjustable Brown Out (BO) pin. Two inputs are provided to latch off the part in a practical way, for instance with OVP and OTP events. Several options exists to chose latch or auto−recovery for these events. www.onsemi.com 1 TSOP−6 CASE 318G STYLE 13 MARKING DIAGRAM 6xxAYWG G Features • Fixed−frequency 65−kHz or 100−kHz Current−mode Control • • • • • • • • • • • • • • • Operation Adjustable Over Power Protection (OPP) Circuit, Disabled at Low Line Adjustable Brown Out Level Frequency Foldback down to 26 kHz and Skip−cycle in Light Load Conditions Internally−fixed Slope Compensation Ramp Internally−fixed 4−ms Soft−start 70−ms Timer−based Auto−recovery Short−circuit Protection Frequency Jittering in Normal and Frequency Foldback Modes Double Hiccup Auto−recovery Short−circuit Protection Pre−short Ready for Latched OCP Option Latched/Auto−Recovery OVP Protection on Vcc Latched Inputs for Improved Robustness (OVP and OTP implementations) Auto−Recovery ac Line OVP Protection (E Version) +500 mA/ −500 mA Source/Sink Drive Capability EPS 2.0 Compliant These are Pb−Free Devices 1 6xx x A Y W G = Specific Device Code = A, E or 2 = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS GND 1 6 DRV FB 2 5 VCC BO 3 4 CS (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 23 of this data sheet. Typical Applications • Ac−dc Adapters for Portable Devices, Computers, Tablets etc. • Auxiliary Power Supplies © Semiconductor Components Industries, LLC, 2015 December, 2020 − Rev. 6 1 Publication Order Number: NCP1256/D NCP1256 Vbulk . . Vout . 1 6 2 5 3 4 NCP1256 OPP adjust Figure 1. Typical Application Example – Latched OVP on Vcc Vbulk . . . 1 6 2 5 3 4 NCP1256 OPP adjust Figure 2. Typical Application Example – OVP is Latched on BO www.onsemi.com 2 Vout NCP1256 Vbulk . Vout . . 1 6 2 5 3 4 OPP adjust NCP1256 Figure 3. Typical Application Example – OVP is Latched on Vcc, OTP Latched on CS Table 1. PIN DESCRIPTIONS Pin No Pin Name Function 1 GND − Pin Description The controller ground. 2 FB Feedback pin Hooking an optocoupler collector to this pin will allow regulation. 3 BO/OVP Adjust the BO level Latch input A voltage below the programmed level stops the controller. When above, the controller can start. When the pin is brought above 4.5 V for four consecutive clock cycles, the part latches off. With the E version, an auto−recovery ac line OVP is available through this pin. 4 CS Current sense + OPP adjustment Latch input 5 Vcc Supplies the controller – protects the IC 6 DRV Driver output This pin monitors the primary peak current but also offers a means to introduce over power compensation. When the pin is brought above 1.5 V during the off time, the part permanently latches off. This pin is connected to an external auxiliary voltage. An OVP comparator monitors this pin and offers a means to latch the converter in fault conditions. The driver’s output to an external MOSFET gate. Table 2. OPTIONS Controller Frequency OCP OVP on BO OVP/OTP CS OVP Vcc NCP1256ASN65T1G 65 kHz Latched Latched Latched Latched NCP1256BSN65T1G 65 kHz Auto−recovery Latched Latched Latched NCP1256ASN100T1G 100 kHz Latched Latched Latched Latched NCP1256BSN100T1G 100 kHz Auto−recovery Latched Latched Latched NCP1256ESN65T1G 65 kHz Auto−recovery Auto−recovery Auto−recovery Auto−recovery www.onsemi.com 3 NCP1256 OVP on BO Validated during off time (option) Auto−recovery for E version OCP timer completed Auto−recovery dble hiccup VOVP 20 us Up counter Event gone? 1−us time constant 1−us time constant OVP on CS Logic mngt RST 4 Vcc and logic management Pre−short Latched OCP (option) UVLO double hiccup Power on reset Vdd S BO reset Q Q power on reset Vlatch1 Vcc R BO BO no clamp for E version 65/100 kHz clock Jitter mod. RdBO Clamp VBO1 VBO2 DZBO S Q Q invert Frequency foldback R OPPGM Drv Vfold IOPPLL Vlatch2 I1 latched OCP opt. I2 VFB < VfoldF Iopp3 = 0 VFB > VoppF Iopp3 = I1 I2=0 VFB I1=I2 Vskip vdd RFB + FB vdd 4 ms SS slope compensation Iopp3 /3 = 1 if timer completed UVLO? checked at PON only Ip flag = 1 if over current −−> start timer −−> auto rec. VFB < 0.75 V ? setpoint = 250 mV peak current freeze ICSO LEB1 CS GND Figure 4. Internal Block Diagram Table 3. MAXIMUM RATINGS TABLE Symbol Vcc Rating Value Unit Power Supply voltage, Vcc pin, continuous voltage −0.3 to 28 V Maximum voltage on low power pins CS, FB and BO −0.3 to 10 V −0.3 to Vcc+0.3 V VDRV Maximum voltage on DRV pin RθJ−A Thermal Resistance Junction−to−Air 360 °C/W TJ,max Maximum Junction Temperature 150 °C −60 to +150 °C Storage Temperature Range HBM Human Body Model ESD Capability per JEDEC JESD22−A114F 4 kV MM Machine Model ESD Capability per JEDEC JESD22−A115C 200 V Charged−Device Model ESD Capability per JEDEC JESD22−C101E 750 V CDM Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 4 NCP1256 Table 4. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, Vcc = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit VCC increasing level at which driving pulses are authorized 5 16 18 20 V VCC(min) VCC decreasing level at which driving pulses are stopped 5 8.3 8.9 9.5 V VCCHYST Hysteresis VccON−Vcc(min) 5 8.4 − 9.25 V VCCreset Latched state reset voltage 5 8.1 VCC(min)−2 50 mV 8.8 V ICC1 Start−up current 5 5 7.5 mA ICC2 Internal IC consumption with VFB = 3.2 V and CL = 0 FSW = 65 kHz FSW = 100 kHz 5 ICC3 Internal IC consumption with VFB = 3.2 V and CL = 1 nF FSW = 65 kHz FSW = 100 kHz 5 Natural part consumption in hiccup mode – non switching SUPPLY SECTION VCCON Idis ICCstby ICCnoload mA − − 1.30 1.35 − − − − 1.8 2.5 − − 5 − 350 − mA Static consumption between two skip cycles 5 − 420 − mA Internal IC consumption while in skip mode (Vcc = 14 V, driving a typical 7−A/600−V MOSFET, includes opto current) (Note 1) 5 − 440 − mA mA DRIVE SECTION Tr Output voltage rise−time @ CL = 1 nF, 10−90% of output signal 6 − 40 − ns Tf Output voltage fall−time @ CL = 1 nF, 10−90% of output signal 6 − 30 − ns ROH Source resistance 6 − 13 − W ROL Sink resistance 6 − 6 − W Peak source current, VGS = 0 V (Note 2) 6 − 500 − mA Isource Peak sink current, VGS = 12 V (Note 2) 6 − 500 − mA VDRVlow Isink DRV pin level at VCC close to VCC(min) with a 33−kW resistor to GND 6 8 − − V VDRVhigh DRV pin level at VCC= VOVP−0.2 V – DRV unloaded 6 10 12 14 V CURRENT COMPARATOR VLimit Maximum internal current setpoint – no OPP 4 0.744 0.8 0.856 V VfoldI Default internal voltage set point for frequency foldback trip point ≈ 63% of Vlimit 4 − 500 − mV Internal peak current setpoint freeze (≈31% of Vlimit) 4 − 250 − mV TDEL Propagation delay from current detection to gate off−state 4 − 40 60 ns TLEB1 Leading Edge Blanking Duration – first OCP path 4 − 300 − ns VfreezeI TSS Internal soft−start duration activated upon startup, auto−recovery − − 4 − ms ICSO Internal pull−up source for pin opening safety test 4 − 1 − mA IOPP1 Voltage on VFB < VfoldF, percentage of applied OPP current 4 − 0 − % IOPP2 Voltage on VFB > VfoldF + 0.7 V, percentage of applied OPP current 4 − 100 − % IOPP3 Voltage on pin 3 = 2.65 V (265 V rms in) AND VFB > VfoldF 4 170 185 210 mA IOPP3clp Voltage on pin 3 > 2.65 V – clamped OPP current 4 − 185 − mA IOPPLL OPP current delivered from CS pin for Vpin3 = VBOon 4 − − 6 mA OPPgm Internal OTA for OPP current generation from BO −40°C to +125°C +25°C to +125°C 4 101 103 115 115 125 125 www.onsemi.com 5 mS NCP1256 Table 4. ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, Vcc = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max 61 93 65 100 70 107 80 83 Unit INTERNAL OSCILLATOR Oscillation Frequency 65 kHz version 100 kHz version − Dmax Maximum duty ratio − 77 fjitter Frequency jittering in percentage of fOSC − − ±5 − % fswing Swing frequency over the whole frequency range − − 240 − Hz fOSC,nom kHz % FEEDBACK SECTION Rup Internal pull−up resistor 2 − 30 − kW Req Equivalent ac resistance from FB to gnd 2 19 23 26 kW Iratio Pin 2 to current setpoint division ratio − − 3 − Feedback voltage below which the peak current is frozen 2 − 0.75 − V 1.5 − V VfreezeF FREQUENCY FOLDBACK VfoldF Frequency foldback level on the feedback pin – ≈63% of maximum peak current − − Ftrans Minimum operating frequency − 22 26 30 kHz − 1.2 − V Vfold,end End of frequency foldback feedback level, Fsw = Ftrans Vskip Skip−cycle level voltage on the feedback pin − − 0.6 − V Skip hysteresis Hysteresis on the skip comparator (Note 3) − − 45 − mV INTERNAL SLOPE COMPENSATION S65 Compensation ramp slope, Fsw = 65 kHz − − 30 − mV/ms S100 Compensation ramp slope, Fsw = 100 kHz − − 50 − mV/ms PROTECTIONS Vlatch1 Latching level input, brown−out input 3 4.3 4.5 4.7 V Vlatch2 Latching level, current sense input, off time only 4 1.45 1.5 1.55 V Number of clock cycles before latch confirmation from pin 3&4 − − 4 − OVP detection time constant − 1 − ms Timer Internal auto−recovery fault timer duration − 50 70 90 ms VOVP Latched over voltage protection on the Vcc rail 6 25.3 26 26.8 V Delay before OVP confirmation on Vcc 6 − 25 − ms Brown−Out input bias current, VBO < DZBO 3 − 0.02 − mA VBOon Turn−on voltage 3 0.76 0.8 0.87 V VBOoff Turn−off voltage 3 0.66 0.7 0.74 V TBO De−bouncing filter on BO comparator 3 − 50 − ms RdBO Dynamic Zener diode resistance (all versions except E) 3 − 1 − kW DZBO Active Zener diode clamping BO signal (all versions except E) 3 3.1 3.3 3.5 V DZBO Active Zener diode clamping BO signal (all versions except E) 3 3.1 3.3 3.5 V Tlatch−count Tlatch−del TOVP−del IBO Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. For information only, collected on a typical 45−W adapter. 2. Guaranteed by design 3. Not tested in production. www.onsemi.com 6 NCP1256 TYPICAL CHARACTERISTICS 20.0 9.5 19.5 9.3 18.5 VCC(off) (V) VCC(on) (V) 19.0 18.0 17.5 9.1 8.9 8.7 17.0 8.5 16.5 16.0 −50 −25 0 25 50 75 100 125 8.3 −50 150 50 75 100 125 150 Figure 5. VCC(on) vs. Junction Temperature Figure 6. VCC(off) vs. Junction Temperature 2.5 9 2.4 2.3 ICC3 (65 kHz) (mA) ICC1 (mA) 25 JUNCTION TEMPERATURE (°C) 8 7 6 5 4 2.2 2.1 2.0 1.9 1.8 1.7 3 −25 0 25 50 75 100 125 1.6 1.5 −50 150 −25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 7. ICC1 vs. Junction Temperature Figure 8. ICC3 vs. Junction Temperature 3.0 500 2.9 480 2.8 460 2.7 440 ICCstby (mA) ICC3 (100 kHz) (mA) 0 JUNCTION TEMPERATURE (°C) 10 2 −50 −25 2.6 2.5 2.4 420 400 380 2.3 360 2.2 340 2.1 2.0 −50 320 300 −50 −25 0 25 50 75 100 125 150 −25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 9. ICC3 vs. Junction Temperature Figure 10. ICCstby vs. Junction Temperature www.onsemi.com 7 NCP1256 0.844 0.55 0.824 0.53 0.804 0.51 Vfoldl (V) VLimit (V) TYPICAL CHARACTERISTICS 0.784 0.47 0.764 −25 0 25 50 75 100 125 0.45 −50 150 −25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 11. VLimit vs. Junction Temperature Figure 12. Vfoldl vs. Junction Temperature 0.30 55 0.28 45 0.26 35 TDEL (ns) VFreezel (V) 0.744 −50 0.24 25 15 0.22 0.20 −50 −25 0 25 50 75 100 125 5 −50 150 −25 0 25 50 75 100 125 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 13. VFreezel vs. Junction Temperature Figure 14. TDEL vs. Junction Temperature 400 210 380 205 360 IOPP3 (mA) 320 300 280 260 195 190 185 180 240 220 200 −50 150 200 340 TLEB1 (ns) 0.49 175 −25 0 25 50 75 100 125 170 −50 150 −25 0 25 50 75 100 125 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 15. TLEB1 vs. Junction Temperature Figure 16. IOPP3 vs. Junction Temperature www.onsemi.com 8 150 NCP1256 70 107 69 105 fOSC(nom) 100 kHz (kHz) fOSC(nom) 65 kHz (kHz) TYPICAL CHARACTERISTICS 68 67 66 65 64 63 61 −50 −25 0 25 50 75 100 125 99 97 93 −50 150 −25 0 25 50 75 100 125 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 17. fOSC(nom) vs. Junction Temperature Figure 18. fOSC(nom) vs. Junction Temperature 83 26 82 25 150 24 Req (kW) 81 Dmax (%) 101 95 62 80 79 23 22 21 78 20 77 −50 −25 0 25 50 75 100 125 19 −50 150 −25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 19. Dmax vs. Junction Temperature Figure 20. Req vs. Junction Temperature 0.85 1.70 0.83 1.65 0.81 1.60 0.79 0.77 VfoldF (V) VfrezzeF (V) 103 0.75 0.73 0.71 1.55 1.50 1.45 1.40 0.69 0.67 0.65 −50 1.35 −25 0 25 50 75 100 125 1.30 −50 150 −25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 21. VfreezeF vs. Junction Temperature Figure 22. VfoldF vs. Junction Temperature www.onsemi.com 9 NCP1256 1.40 30 1.35 29 1.30 28 1.25 27 Ftrans (kHz) Vfold,end (V) TYPICAL CHARACTERISTICS 1.20 1.15 25 1.10 24 1.05 23 1.00 −50 −25 0 25 50 75 100 125 22 −50 150 −25 0 25 50 75 100 125 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 23. Vfold,end vs. Junction Temperature Figure 24. Ftrans vs. Junction Temperature 650 4.70 640 4.65 630 150 4.60 Vlatch1 (V) 620 Vskip (mV) 26 610 600 590 580 4.55 4.50 4.45 4.40 570 560 550 −50 4.35 −25 0 25 50 75 100 125 4.30 −50 150 −25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 25. Vskip vs. Junction Temperature Figure 26. Vlatch1 vs. Junction Temperature 1.55 90 85 80 Timer (ms) Vlatch2 (V) 1.53 1.51 1.49 75 70 65 60 1.47 55 1.45 −50 −25 0 25 50 75 100 125 50 −50 150 −25 0 25 50 75 100 125 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 27. Vlatch2 vs. Junction Temperature Figure 28. Timer vs. Junction Temperature www.onsemi.com 10 150 NCP1256 TYPICAL CHARACTERISTICS 26.7 0.84 26.5 0.83 0.82 VBOon (V) VOVP (V) 26.3 26.1 25.9 25.7 0.80 0.79 0.78 25.5 0.77 25.3 −50 −25 0 25 50 75 125 100 0.76 −50 150 −25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 29. VOVP vs. Junction Temperature Figure 30. VBOon vs. Junction Temperature 1.5 8.9 1.4 8.8 1.3 8.7 1.2 RdBO (kW) 9.0 8.6 8.5 8.4 1.1 1.0 0.9 0.8 8.3 8.2 0.7 8.1 8.0 −50 0.6 0.5 −50 −25 0 25 50 75 100 125 150 −25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 31. VCCreset vs. Junction Temperature Figure 32. RdBO vs. Junction Temperature 3.50 3.45 3.40 DZBO (V) VCCreset (V) 0.81 3.35 3.30 3.25 3.20 3.15 3.10 −50 −25 0 25 50 75 100 125 JUNCTION TEMPERATURE (°C) Figure 33. DZBO vs. Junction Temperature www.onsemi.com 11 150 NCP1256 APPLICATION INFORMATION NCP1256 implements a standard current mode architecture where the switch−off event is dictated by the peak current setpoint. This component represents the ideal candidate where low part−count and cost effectiveness are key design parameters, particularly in low−cost ac−dc adapters, open−frame power supplies etc. NCP1256 brings all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as a non−dissipative OPP, a brown−out protection and two independent latch inputs for OVP/OTP implementations. All these features are packed in a tiny TSOP−6 package. • Current−mode operation with internal slope compensation: implementing peak current mode control at a fixed 65−kHz or 100−kHz frequency, the NCP1256 includes an internal slope compensation signal whose level will cover most of offline design cases. Additional ramp can be added via a simple scheme around the feedback or current sense pin as described below. • Brown−out protection: a portion of the input mains (or the rectified bulk rail) is brought to pin 3 via a resistive network. When the voltage on this pin is too low, the part stops pulsing. No re−start attempt is made until the controller senses that the voltage is back within its normal range. When the brown−out comparator senses the voltage is acceptable, it sends a general reset to the controller (latched states are released) and authorizes re−start. Please note that a re−start is always synchronized with a VCCON transition event for a clean start−up sequence. If Vcc is naturally above VCCON when the BO circuit recovers, re−start is immediate. • Internal OPP: the part internally buffers the brown out voltage and transforms it into a current, sourced out of the CS pin. By inserting a resistance between the sense resistor and the CS pin, the designer has the ability to build an offset and precisely adjust the OPP level he needs. Please note that the OPP current starts from 0 when the BO voltage is 0.8 V, a low−line condition. It helps pass maximum power at the lowest input voltage despite a strong compensation at high line. OPP is also disabled in frequency foldback mode for a better light−load efficiency. • Low startup current: reaching a low no−load standby power always represents a difficult exercise when the controller draws a significant amount of current during start−up. Thanks to its proprietary architecture, the NCP1256 is guaranteed to draw less than 10 mA maximum (guaranteed at a 125−°C Tj), easing the design of low standby power adapters. • EMI jittering: an internal low−frequency modulation signal varies the pace at which the oscillator frequency • • • • • is modulated. This helps spreading out energy in conducted noise analysis. To improve the EMI signature at low power levels, the jittering is kept in frequency foldback mode (light load conditions). Frequency foldback capability: a continuous flow of pulses is not compatible with no−load/light−load standby power requirements. To excel in this domain, the controller observes the feedback pin and when it reaches a level of 1.5 V, it starts reducing switching frequency. When the feedback level reaches 1.2−V, the frequency hits its lower stop at 26 kHz. When the feedback pin goes further down and reaches 0.75 V, the peak current setpoint is internally frozen at 31% of the maximum limit. Below this point, if power continues to drop, the feedback pins passes below 0.6 V and the controller enters classical skip−cycle mode. Internal soft−start: a soft−start precludes the main power switch from being stressed upon start up and it reduces output voltage overshoots. In this controller, the soft−start is internally fixed to 4 ms. Soft−start is activated when a new startup sequence occurs or during an auto−recovery hiccup. OVP inputs: the NCP1256 welcomes two inputs. One is located in the brown out input whose upper dynamic range is less than 3 V at a 375−V dc input. If an external event lifts the BO pin above 4.5 V for four consecutive clock cycles, the part permanently latches off. Noise immunity is strengthened by reducing the BO pin resistance when the voltage on the pin exceeds 3.3 V (beyond the OPP dynamic range). In the E version, the clamp is removed and the fault is fully auto−recovery for an efficient ac line OVP. The second OVP input is placed in the current sense pin and is only observed during the off−time duration. If during the off time the current sense pin is lifted above 1.5 V typically four consecutive clock cycles, the part latches off. By connecting an NTC via a diode to the auxiliary winding, a cheap and accurate OTP can be implemented. Regardless of the trip mode (BO or CS), when latched, Vcc hiccups between both UVLO levels while all drive pulses are off. Reset occurs when a) the BO voltage drops below VBO(off) during a going−down Vcc cycle or b) Vcc passes below the reset voltage VCCreset which is VCC(min)−250 mV. When either event is detected, the IC goes through a new fresh start−up sequence. Vcc OVP: an OVP protects the circuit against Vcc runaways. The fault must be present at least 20 ms to be validated. This OVP is latched, except on E version where it is auto−recovery. Short−circuit protection: short−circuit and especially over−load protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the auxiliary winding www.onsemi.com 12 NCP1256 level does not properly collapse in presence of an output short). In this controller, every time the internal 0.8−V maximum peak current limit is activated (or less when OPP is used), an error flag is asserted and a time period starts, thanks to the programmable timer. When the timer has elapsed, the controller enters a double−hiccup auto−recovery mode or is fully latched depending on the selected option. 2. if an UVLO signal is detected but the error flag is not asserted, double−hiccup auto−recovery occurs and the part tries to resume operations. 3. if the error flag is asserted without UVLO, the part classically permanently latches off. Start−up Sequence The NCP1256 start−up voltage is purposely made high to permit large energy storage in a small Vcc capacitor value. This helps operate with a small start−up current which, together with a small Vcc capacitor, will not hamper the start−up time. To further reduce the standby power, the controller start−up current is purposely kept low, below 10 mA. Start−up resistors can therefore be connected to the bulk capacitor or directly to the mains input voltage if you wish to save a few more mW. Please note that with the latched OCP option, the part becomes sensitive to the UVLO event only at the first power−on sequence. Any UVLO event is ignored afterwards (normal auto−recovery operation). This is to pass the pre−short test at power up: 1. if the internal error flag is armed (short circuit) AND a UVLO event is sensed, the part is immediately latched. UVLO sensing is ignored after the first sucessful start−up sequence. D1 R3 R4 R1 R2 D2 Vcc Input mains Cbulk C1 I2 I1 X2 D6 BAV21 I3 . ICC1 D3 D5 1N4148 CVcc C4 aux D4 Figure 34. The startup resistor can be connected to the input mains for further power dissipation reduction Figure 34 shows a typical recommended configuration where start−up resistors connect together to the mains input. This technique offers the benefit of freely discharging the X2 capacitor usually part of the EMI filter. The calculation of these resistors depends on several parameters. Assuming a 0.47−mF X2 capacitor, the safety standard recommends a time constant less than 1 s maximum when a resistor is connected in parallel to provide a discharge path. This sets the upper limit for the sum of discharge resistors connected to the controller Vcc: R startup t 1 t 2.1 MW 0.47 m (eq. 2) CV CC w I CCt 1 1.5 m 10 m w w 1.6 mF 9 VCC on * VCC min Let us select a 2.2−mF capacitor at first and experiments in the laboratory will let us know if we were too optimistic for t1. Experiments across temperature range are important as capacitance and ESR of this Vcc capacitor can be affected. The Vcc capacitor being known, we can now evaluate the charging current we need to bring the Vcc voltage from 0 to the IC VCCon voltage, 18 V typical. This current has to be selected to ensure start−up at the lowest mains (85 V rms) to be less than 3 s (2.5 s for design margin): (eq. 1) The first step starts with the calculation of the needed Vcc capacitor which will supply the controller until the auxiliary winding takes over. Experience shows that this time t1 can be between 5 and 20 ms. Considering that we need at least an energy reservoir for a t1 time of 10 ms, the Vcc capacitor must be larger than: I charge w VCC onC V 2.5 CC w 18 2.2 m w 16 mA 2.5 (eq. 3) If we account for the 10−mA current that will flow inside the controller (I1 in Figure 34), then the total charging current delivered by the start−up resistor must be 26 mA, rounded to 30 mA. If we connect the start−up network to both www.onsemi.com 13 NCP1256 mains inputs (two half−wave connections then), half of the average current I1 is defined by: I1 + 2 Vac,rmsǸ2 * VCC on p R startup Now that the first Vcc capacitor has been selected, we must ensure that the self−supply does not disappear in no−load conditions. In this mode, the skip−cycle can be so deep that refreshing pulses are likely to be widely spaced, inducing a large ripple on the Vcc capacitor. If this ripple is too large, chances exist to touch the VCC(min) and reset the controller into a new start−up sequence. A solution is to grow this capacitor but it will obviously be detrimental to the start−up time. The option offered in Figure 34 elegantly solves this potential issue by adding an extra capacitor on the auxiliary winding. However, this component is separated from the Vcc pin via a simple diode. You therefore have the ability to grow this capacitor as you need to ensure the self−supply of the controller without affecting the start−up time and standby power. (eq. 4) To make sure this current is always greater than 15 mA (half of the necessary 30−mA current), the minimum value for Rstart−up can be extracted: (eq. 5) V ac,rmsǸ2 85 1.414 −18 −VCC on p p R start−up v v v 1.3MW 15 m I CV ,min cc We could thus connect two resistors of 1.3 MW (total 2.6 MW) across the line to a) power the IC at start up b) ensure X2 discharge when the user unplugs the adapter. This calculation is purely theoretical, considering a constant charging current. In reality, the take over time at start up can be shorter (or longer!) and it can lead to a reduction of the Vcc capacitor. This brings a decrease in the charging current and an increase of the start−up resistor, for the benefit of standby power. Laboratory experiments on the prototype are thus mandatory to fine tune the converter. If we chose the two 1−MW resistors as suggested by Equation 5, the dissipated power per resistance at high line amounts to: PR startup,max [ V ac,peak 2 4R start−up + ǒ230 4 Ǹ2Ǔ 1Meg Brown−Out Protection Brown−out (BO) is a means to protect the converter against an erratic behavior that can occur at the lowest input voltage level. By safely stopping the output pulses when the mains is below a predetermined value, the converter prevents thermal runaway, greatly improving its robustness. Brown−out protection is another way to avoid an erratic hiccup mode when too low an input voltage limits the power delivery. Some applications, such as printer power supplies, forbid this kind of operations and impose a clean stop. In that case, brown−out detection/protection is the way to go. Figure 35 shows a simplified version of what is implemented in the controller. (eq. 6) 2 + 105k + 26mW 4Meg or a total of 52 mW. L To diode bridge N R4 1Meg R3 1Meg VccON sync. R1 1.4Meg BO C1 1uF R2 80k VBO BO ok hysteresis Gnd Figure 35. A simple comparator monitors the input voltage via a single pin. When this voltage is too low, the pulses are stopped and the Vcc hiccups www.onsemi.com 14 NCP1256 To ensure a clean re−start, the BO information is only validated when Vcc reaches VCCON. This ensures a fully−charged Vcc capacitor when the controller pulses again (fresh start up). An asynchronous BO−related re−start could induce aborted start−up sequences if the Vcc capacitor would be too close to the UVLO threshold. From the above schematic, the calculation of the resistor is straightforward. We have connected the resistor to the input line and thus observe a single−wave signal peaking to Vin,peak. The average voltage seen on top of R4 in Figure 35 is: V in,avg + V in,peak p upper resistive network, the turn−off voltage can then easily be derived: V turn−off + (eq. 7) V BOon + 0.8 + 80 kW I bridge 10 m (eq. 8) Now suppose we want a typical turn−on voltage Vturn−on of 80 V rms. From the two above equations, we can calculate the value of the upper resistive string: ǒ Ǔ Vturn−onǸ2 −V BOon p R upper + I bridge 80 + (eq. 9) 1.414 −0.8 3.14 +3.5MW 10 m The hysteresis on the internal reference source is 140 mV typically. The ratio of the two voltages is 1.14. With the BO is synced to VCCON. BO is synced to VCCON. Vcc VCCON VCC(min) BO BO not Ok Vcc is discharged BO not Ok Vcc is discharged Ok Not Ok (eq. 10) A 1−mF capacitor is necessary to filter out the input ripple. Reducing its value, hence allowing more ripple, can help fine−tune the hysteresis, if necessary. A simulation has been run with an upper−side resistor of 3.7 MW, a lower−side resistor of 80 kW and a 1−mF filtering capacitor. The measured turn−on voltage is 80 V rms and the turn−off voltage is around 70 V rms. Please check the demonstration board schematic in which the BO sensing is done in a slightly different way, capitalizing on the X2 discharge resistors. Be aware that BO test has to be carried without oscilloscope probes or any leakage path that could affect the high−impedance sensing. When the controller senses a BO event, all pulses are immediately cut. The IC internal consumption brings Vcc down towards UVLO. When this level is reached, the controller goes back into low−consumption mode and lifts Vcc up again. At VCCON, a check on the BO comparator is made: if the input level is correct, the part re−starts, if still too low, the part consumption brings Vcc down again. As a result, Vcc operates in hiccup mode during a BO event. The below figure describes the typical waveforms obtained at start−up and in operation. Please note the synchronization of the BO validation with the VCCON point. This ensures a clean start−up sequence with a fully charged Vcc capacitor. Then, choose a bridge current compatible with the power consumption you can accept. If we chose 10 mA, the pull−down resistor R2 calculation is straightforward: R2 + V turn−on + 80 [ 70 V 1.14 1.14 BO validated t Ok Not Ok DRV t A small delay ensures BG is ready. t Figure 36. the brown−out recovery is always synchronized to the Vcc signal: when it reaches VCCON, the driver delivers the output pulses. www.onsemi.com 15 NCP1256 Please note that the IC will restart immediately if the BO comparator sends the green light while Vcc is above VCCON. In that case, as Vcc is already high, there is no need to go through a fresh start−up sequence and the part can switch again. at low line. NCP1256 senses the input voltage via a resistive network primarily used for brown−out protection. This line image is transformed into a current information further applied to the current sense pin (CS). A resistor placed in series from the sense resistor to the CS pin will create an offset voltage proportional to the input voltage variation. An added current sink will ensure a 0 OPP current at low line, leaving the converter power capability intact in the lowest operating voltage. Figure 37 presents the internal simplified architecture of this OPP circuitry. Over Power Protection Over Power Protection (OPP) is a known means to limit the output power excursion at high mains. Several elements such as propagation delays and operating mode explain why a converter operated at high line delivers more power than Vbulk Rupper BO C1 Rlower OPPGM VfoldF IOPPLL I1 Iopp3 ROPP Rsense VFB > VfoldF Iopp3 = I1 VFB < VoppF Iopp3 = 0 I2 I2=0 VFB I1=I2 vdd ICSO CS V(FB) To CS comparator offset Figure 37. Over Power Protection is provided via the bulk voltage image present on Brown−Out pin We assume the brown−out network is tweaked so that a 80−V rms input voltage brings 0.8 V on the BO pin. This is the voltage at which the adapter will start working. The voltage will be transformed into a current by the OPPGM block. Its transconductance is 115 mS, leading to a generated current of 92 mA at a 0.8−V bias. However, there is an internal fixed current sink IOPPLL calibrated so that the net current flowing into ROPP is 0 at this low−voltage input. It ensures an almost non−compensated converter at low line. Now, assume a 265−V input voltage, the BO level will be 2.65 V and will generate an offset current of 185 mA as stated in the specs. In our design, as an example, say we need to reduce the maximum peak current setpoint by 250 mV to reduce the maximum power at the 265−V input. In that case, we will need to generate a 250−mV offset across ROPP. With a 185−mA current, ROPP should be equal to 230 m / 185 u = 1.35 kW. A small 100−220 pF capacitor closely connected between the CS and GND pins will form an effective noise filter and will nicely improve the converter immunity to noise. Please note that the OPP current is clamped for a BO pin voltage greater than 2.65 V. Should you lift the pin above this voltage, there will be no increase of the OPP current and the current absorbed by the pin will increase as you approach the OVP level. The offset voltage can affect the standby power performance by reducing the peak current setpoint in light−load conditions. For this reason, it is desirable to smoothly cancel its action as soon as frequency folback occurs. A typical curve variation is shown in Figure 38. At low power, below the frequency folback starting point, 100% of the OPP current is internally absorbed and no offset is created through the CS pin. When feedback increases again and reaches the frequency foldback point, as the frequency goes up, OPP starts to build up and reaches its full value at VfoldF + 0.7 V. www.onsemi.com 16 NCP1256 V series resistor reduce the pin impedance as the voltage starts to increase above 3.3 V. More current is thus needed to actually trigger the internal latch. The example shows how an external event (an OVP in the secondary side for instance) can trip the latch. R5 ensures enough bias circulates in the optocoupler while D2 isolates the circuit from the high− impedance BO bridge. As the voltage on the BO pin starts increasing beyond 3.3 V, more current is drawn on the optocoupler (RdBO is 1 kW typically) and when the BO voltage touches the 4.5−V trip point, the circuit latches off after 4 consecutive clock cycles. If the OVP assertion disappears before the counter counts to 4, a counter reset occurs. A primary−side version of the above circuit can be implemented with the help of a single Zener diode as shown in Figure 40. The Zener will lift the BO pin when the feedback loop is lost and will latch the part immediately. In latch−off mode, the Vcc keeps hiccupping for ever between VCCON and VCC(min) while the drive output is cut. To reset the latch, either cycle the input voltage so that the BO pin passes below VBOoff or unplug the adapter until the controller Vcc goes below VCCreset. In either case, the controller will resume via a fresh start−up sequence. With the E version, the current clamp is removed and the fault is auto−recovery for ac line OVP implementation. You can design in two different ways: 1. You select the ac line OVP and then have a corresponding BO on: assume you design the sensing network to have 4.5 V for 320 Vrms, then, the BO on is 320 x 0.8/4.5 = 57 Vrms. 2. You select the BO on voltage and have a corresponding ac line OVP: assume a turn on voltage of 60 Vrms, then the ac line OVP voltage is set to 60 x 4.5/0.8 = 337 Vrms. max Fsw increases Fsw decreases VFB +0.7 V VfoldF t % 100 OPP current t 0 Figure 38. The OPP current is applied when the feedback voltage exceeds the folback point. It is 0 below it Latch on Brown−Out Input It is possible to latch the controller if an external event brings the BO input above Vlatch1 for four consecutive clock cycles. The simplified internal circuitry appear in Figure 39 where OVP is triggered from the secondary side via a dedicated optocoupler. To improve the controller noise immunity, a circuit made of an active Zener diode and a 1−us time constant Up counter OVP gone? Vbulk R1 Vcc Power on reset BO reset S Q latch Q Vlatch1 BO D2 RST 4 R RdBO R5 R2 DZBO Figure 39. The circuit can easily be latched via a dedicated optocoupler observing the secondary side voltage www.onsemi.com 17 NCP1256 Bulk Vcc R4 D4 Vcc DRV D3 1N4148 BO R5 1k C3 Q1 R2 1k CS R3 Rsense Figure 40. A simple Zener diode (D4) can also be wired on the BO pin, latching off the part in case Vcc runs away (if the secondary−side LED is shorted for instance). Make sure R3, R4, R5 D3, D4 and C3 are closely located to the controller Auto−Recovery Short−Circuit Protection In case of output short−circuit or if the power supply experiences a severe overloading situation, an internal error flag is raised and starts a countdown timer. The flag is raised at the first maximum peak current event. If the flag is asserted longer than its programmed value (70 ms typical), the driving pulses are stopped and Vcc falls down as the auxiliary pulses are missing. Vcc fall out is ensured by the part natural consumption in this mode which is around 400 mA. To ensure Vcc hiccup and thus autorecovery, the start−up current must always be less than these 400 mA otherwise recovery will be lost. Timer reset occurs when 8 successive resets coming from the feedback back into regulation. When the Vcc level crosses VCC(min), the controller consumption is down to a few mA and the Vcc slowly builds up again thanks to the resistive starting network. When Vcc reaches VCCON, the controller purposely ignores the re−start and waits for another Vcc cycle: this is the so−called double hiccup. By lowering the duty ratio in fault condition, it naturally reduces the average input power and the rms current in the output cable. Illustration of such principle appears in Figure 41. Please note that soft−start is activated upon re−start attempt. Vcc (t ) 18 V 8.8 V VDRV (t ) No pulse area Figure 41. An auto−recovery hiccup mode is entered in case a faulty event longer than 70 ms is acknowledged by the controller www.onsemi.com 18 NCP1256 The double hiccup is operating regardless of the brown−out level. However, when the internal comparator toggles indicating that the controller recovers from a brown−out situation (the input line was ok, then too low and back again to normal), the double hiccup is interrupted and the controller re−starts to the next available Vcc peak. 18 V 1 Figure 42 displays the resulting waveform: the controller is protecting the converter against an overload. The mains suddenly went down, and then back again at a normal level. Right at this moment, the double hiccup logic receives a reset signal and ignores the next hiccup to immediately initiate a re−start signal. 1 2 2 1 Vcc (t ) 8.8 V BOK BOK BONOK VDRV (t ) Re−start Brown−out recovery Figure 42. The hiccup latch is reset when a brown−out transition is detected to shorten the re−start time Latched Short Circuit Protection with Pre Short avoid this problem, NCP1256 (with latched−OCP option) combines the error flag assertion together with the UVLO flag to confirm a pre−short situation: upon start up, as maximum power is asked to increase Vout, the error flag is temporarily raised until regulation is met. If during the time the flag is raised an UVLO event is detected, the part latches off immediately. When latched, Vcc hiccups between the two levels, VCCON and VCC(min) until a reset occurs (Brown−out event or Vcc cycled down below VCCreset). In normal operation, if a UVLO event is detected for any reason while the error flag is not asserted, the controller will naturally resume operations in a double hiccup mode. Details of this behavior are given in Figure 43. In some applications, the controller must be fully latched in case of an output short circuit presence. In that case, you would select options A in the controller list. When the error flag is asserted, meaning the controller is asked to deliver its full peak current, upon timer completion, the controller latches off: all pulses are immediately stopped and Vcc hiccups between the two levels, VCCON and VCC(min). However, in presence of a small Vcc capacitor, it can very well be the case where the stored energy does not give enough time to let the timer elapse before Vcc touches UVLO. When this happens, the latch is not acknowledged since the timer countdown has been prematurely aborted. To www.onsemi.com 19 NCP1256 vcc (t ) latched resumed VCCON VCC(min) glitch New sequence t vDRV (t ) UVLO AND err. flag t 1 1 Error flag 0 t Figure 43. In case a UVLO event is sensed while the error flag is asserted, full latch occurs UVLO latch is made available solely during the start−up sequence. When the power supply starts−up, the loop is open and asks for maximum peak current. The internal fault flag is armed and the fault timer counts down. If an UVLO event occurs during this time, the part immediately latches off. If no UVLO occurs, once the output voltage has reached regulation, the internal error flag is released and the latch authorizing UVLO detections is reset: any new UVLO events will simply be ignored. In the latched−OCP version, UVLO test is available at the first power up, when recovering from a brown−out episode or while the part operates in hiccup mode. VCCon ? 1 : 0 Latched is armed at power up 3 S Q Q 2 6 latch 5 1 R 4 Error flag down ? 1 : 0 UVLO ? 1 : 0 VCCON error Figure 44. In case a UVLO event is sensed while the error flag is asserted, full latch occurs. UVLO observation disappears if regulation is successful after the first start−up sequence. www.onsemi.com 20 NCP1256 Frequency Foldback the frequency is fixed and cannot go further down. The peak current setpoint is free to follow the feedback voltage from 2.4 V (full power) down to 0.75 V. At 0.75 V, as both frequency and peak current are frozen (250 mV or ≈31% of the maximum 0.8−V setpoint) the only way to further reduce the transmitted power is to enter skip cycle and chop the switching pattern. This is what happens when the feedback voltage drops below 0.6 V typically. Figure 45 depicts the adopted scheme for the part. The reduction of no−load standby power associated with the need for improving the efficiency, requires a change in the traditional fixed−frequency type of operation. This controller implements a switching frequency foldback when the feedback voltage passes below a certain level, Vfold, set at 1.5 V. At this point, the oscillator turns into a Voltage−Controlled Oscillator (VCO) and reduces switching frequency down to a feedback voltage of 1.2 V where switching frequency is 26 kHz typically. Below 1.2 V, Frequency Peak current setpoint Fsw VCS FB Vfold,end Vfold max 0.8 V 65 kHz [0.5 V 26 kHz min 0.6 V 1.2 V 1.5 V 2.4 V 4V VFB [0.25 V min Vskip Vfreeze Vfold 0.6 V 1.5 V 0.75 V 3.2 V VFB Figure 45. By observing the voltage on the feedback pin, the controller reduces its switching frequency for an improved performance at light load VFB (V) Open loop 4.0 2.4 1.5 1.2 0.75 0.6 Peak current is clamped Ipeak max Fsw is fixed 65 kHz Peak current can change 65 kHz Fsw decreases 26 kHz Ipeak min Peak current is frozen t 0 duty−ratio Figure 46. Another look at the relationship between feeback and current setpoint while in frequency reduction mode. www.onsemi.com 21 NCP1256 Slope Compensation Latching off the Controller Slope compensation is a known means to fight sub−harmonic oscillations in peak−current mode controlled power converters (flyback in our case). By adding an artificial ramp to the current sense information or subtracting it from the feedback voltage, you implement slope compensation. How much compensation do you need? The simplest way is to consider the primary−side inductor downslope and apply 50% of its value for slope compensation. For instance, assume a 65−kHz/19−V output flyback converter whose transformer turns ratio 1:N is 1:0.25. The primary inductor is 600 mH. As such, assuming a 1−V forward drop of the output rectifier, the downslope is evaluated to The part offers a dedicated latch input via the BO pin but also through the CS pin. However, latch through the CS pin is only possible if a fault voltage is applied during the off time. If we would apply the voltage during the on time, let’s say by connecting a Zener diode from the auxiliary Vcc to the CS pin, then peak current reduction would occur as the Zener conducts and a kind of primary−regulated converter would be built. We could not latch off the part. Now, if we use the dynamic voltage present on the auxiliary winding during the off time only, we do not bias the CS pin during the on time and operations are not disturbed. In Figure 48 example, it is possible to realize overtemperature protection without using a single active element. As the auxiliary voltage is positive during the off−time duration, we can use this voltage and scale it down on the CS pin via a dedicated NTC. The series diode blocks when the auxiliary jumps negative at turn on. We recommend using a fast diode with a small junction capacitance. A BAV21 perfectly fits the bill. As temperature increases, the CS pin bias goes up during the off time, cycle by cycle. When it reaches the latch level of typically 1.5 V more than 4 consecutive clock cycles, the part fully latches off. When latched, Vcc hiccups between the two levels, VCCON and VCC(min) until a reset occurs (Brown−out event or Vcc cycled down below VCCreset). S off + V out )V f NL p (eq. 11) 19 ) 1 + + 133kAńs or 133mAńms 0.25 600m If we have a 0.33−W sense resistor, then the current downslope turns into a voltage downslope whose value is simply SȀ off + S offR sense + 133 k 0.33 [ 44 mVńms (eq. 12) 50% of this value is 22 mV/ms. The internal slope compensation level is typically 30 mV/ms (for the 65−kHz version) so it will nicely compensate this design example. What if my converter is under−compensated? You can still add compensation ramp via a simple RC arrangement showed in Figure 47. Please look at AND8029 available from www.onsemi.com regarding calculation details of this configuration. Vcc D2 BAV21 DRV R1 ROTP NTC D1 1N4148 Vcc DRV C1 R4 CS CS Q1 R2 1k R3 C2 220 pF Rsense Rsense Figure 48. A simple NTC wired between the auxiliary winding and the CS pin is enough to implement a precise overtemperature protection Figure 47. An easy means to add more slope compensation is by using an extra RC network building a ramp from the drive signal www.onsemi.com 22 NCP1256 vCS (t ) vCS (t ) Figure 49. Typical waveforms on the CS pin with a controller almos latching off (off voltage close to 1.5 V in these shots). Left condition is light−load DCM while the right one is operating in CCM at nominal load. Latching off with the Vcc pin A more comprehensive circuits allows a combined action from an overtemperature event and an overvoltage on the auxiliary Vcc (or directly via the auxiliary plateau). R3 The NCP1256 hosts a dedicated comparator on the Vcc pin. When the voltage on this pin exceeds 26 V typically for more than 20 ms, a signal is sent to the internal latch and the controller immediately stops the driving pulses while remaining in a lockout state. The part can be reset by cycling down its Vcc, for instance by pulling off the power plug but also if a brown−out recovery is sensed by the controller. This technique offers a simple and cheap means to protect the converter against optocoupler failures. Vcc D2 NTC Q2 2N2907 R4 47k R5 DRV Q1 R2 1k CS Rsense Figure 50. Adding a small PNP bipolar transistor helps combine both faulty events (OTP and OVP) on the CS pin input. ORDERING INFORMATION OCP OVP on BO OVP/OTP CS OVP Vcc 65 kHz Latched Latched Latched Latched 65 kHz Auto−recovery Latched Latched Latched 6A2 100 kHz Latched Latched Latched Latched NCP1256BSN100T1G 622 100 kHz Auto−recovery Latched Latched Latched NCP1256ESN65T1G 6EA 65 kHz Auto−recovery Auto−recovery Auto−recovery Auto−recovery Controller Marking Frequency NCP1256ASN65T1G 6AA NCP1256BSN65T1G 62A NCP1256ASN100T1G www.onsemi.com 23 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE V 1 SCALE 2:1 D H ÉÉ ÉÉ 6 E1 1 NOTE 5 5 2 L2 4 GAUGE PLANE E 3 L b SEATING PLANE C DETAIL Z e DIM A A1 b c D E E1 e L L2 M c A 0.05 M DATE 12 JUN 2012 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 2: PIN 1. EMITTER 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. BASE 2 6. COLLECTOR 2 STYLE 3: PIN 1. ENABLE 2. N/C 3. R BOOST 4. Vz 5. V in 6. V out STYLE 4: PIN 1. N/C 2. V in 3. NOT USED 4. GROUND 5. ENABLE 6. LOAD STYLE 5: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 6: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 7: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. N/C 5. COLLECTOR 6. EMITTER STYLE 8: PIN 1. Vbus 2. D(in) 3. D(in)+ 4. D(out)+ 5. D(out) 6. GND STYLE 9: PIN 1. LOW VOLTAGE GATE 2. DRAIN 3. SOURCE 4. DRAIN 5. DRAIN 6. HIGH VOLTAGE GATE STYLE 10: PIN 1. D(OUT)+ 2. GND 3. D(OUT)− 4. D(IN)− 5. VBUS 6. D(IN)+ STYLE 11: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1/GATE 2 STYLE 12: PIN 1. I/O 2. GROUND 3. I/O 4. I/O 5. VCC 6. I/O STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 STYLE 14: PIN 1. ANODE 2. SOURCE 3. GATE 4. CATHODE/DRAIN 5. CATHODE/DRAIN 6. CATHODE/DRAIN STYLE 15: PIN 1. ANODE 2. SOURCE 3. GATE 4. DRAIN 5. N/C 6. CATHODE STYLE 16: PIN 1. ANODE/CATHODE 2. BASE 3. EMITTER 4. COLLECTOR 5. ANODE 6. CATHODE STYLE 17: PIN 1. EMITTER 2. BASE 3. ANODE/CATHODE 4. ANODE 5. CATHODE 6. COLLECTOR GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 XXXAYWG G 1 6X 3.20 XXX A Y W G 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB14888C TSOP−6 1 IC 0.95 XXX MG G = Specific Device Code =Assembly Location = Year = Work Week = Pb−Free Package STANDARD XXX = Specific Device Code M = Date Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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