NCP1651
Single Stage Power Factor
Controller
The NCP1651 is an active, power factor correction controller that
can operate over a wide range of input voltages. It is designed for
50/60 Hz power systems. It is a fixed frequency controller that can
operate in continuous or discontinuous conduction modes.
The NCP1651 provides a low cost, low component count solution
for isolated AC−DC converters with mid−high output voltage
requirements. The NCP1651 eases the task of meeting the
IEC1000−3−2 harmonic requirements for converters in the range of
50 W − 250 W.
The NCP1651 drives a flyback converter topology to operate in
continuous/discontinuous mode and programs the average input
current to follow the line voltage in order to provide unity power
factor. By using average current mode control CCM algorithm, the
NCP1651 can help provide excellent power factor while limiting the
peak primary current. Also, the fixed frequency operation eases the
input filter design.
The NCP1651 uses a proprietary multiplier design that allows for
much more accurate operation than with conventional analog
multipliers.
Features
•
•
•
•
•
•
•
•
•
•
•
Fixed Frequency Operation
Average Current Mode PWM
Internal High Voltage Startup Circuit
Continuous or Discontinuous Mode Operation
High Accuracy Multiplier
Overtemperature Shutdown
External Shutdown
Undervoltage Lockout
Low Cost/Parts Count Solution
Ramp Compensation Does Not Affect Oscillator Accuracy
This is a Pb−Free Device
• High Current Battery Chargers
• Front Ends for Distributed Power Systems
May, 2015 − Rev. 10
MARKING
DIAGRAM
SOIC−16
D SUFFIX
CASE 751B
16
1
A
WL
Y
WW
G
NCP1651G
AWLYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
OUT 1
16 STARTUP
GND 2
15 NC
CT 3
14 NC
RAMP COMP 4
13 VCC
IS+ 5
12 Vref
Iavg−fltr 6
11 AC COMP
Iavg 7
10 AC REF
9 AC INPUT
FB/SD 8
(Top View)
ORDERING INFORMATION
Device
NCP1651DR2G
Typical Applications
© Semiconductor Components Industries, LLC, 2015
www.onsemi.com
Package
Shipping†
SOIC−16
(Pb−Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1
Publication Order Number:
NCP1651/D
NCP1651
PIN FUNCTION DESCRIPTION
Pin No.
Function
1
Output
Drive output for power FET or IGBT. Capable of driving small devices, or can be connected to an
external driver for larger transistors.
Description
2
Ground
Ground reference for the circuit.
3
CT
4
Ramp
Compensation
5
IS+
6
Iavg−fltr
A capacitor connected to this pin filters the high frequency component from the instantaneous current
waveform, to create a waveform that resembles the average line current.
7
Iavg
An external resistor with a low temperature coefficient is connected from this terminal to ground, to set
and stabilize the gain of the Current Sense Amplifier output that drives the AC error amplifier.
8
Feedback/
Shutdown
The error signal from the error amplifier circuit is fed via an optocoupler or other isolation circuit, to this
pin. A shutdown circuit is also connected to this pin which will put the unit into a low power shutdown
mode if this voltage is reduced to less than 0.6 volts.
9
AC Input
The fullwave rectified sinewave input is connected to this pin. This information is used for the reference
comparator and the average current compensation circuit.
10
AC Reference
A capacitor is connected to this pin to filter the modulated output of the reference multiplier.
11
AC
Compensation
Provides pole for the AC Reference Amplifier. This amplifier compares the sum of the AC input voltage
and the low frequency component of the input current to the reference signal. The response must be
slow enough to filter out most of the high frequency content of the current signal that is injected from the
current sense amplifier, but fast enough to cause minimal distortion to the line frequency information.
12
Vref
6.5 volt regulated reference output.
13
VCC
Provides power to the device. This pin is monitored for undervoltage and the unit will not operate if the
VCC voltage is not within the UVLO range. Initial power is supplied to this pin via the high voltage startup
network.
14
No Connection
This pin is not available due to spacing considerations of the startup pin.
15
No Connection
This pin is not available due to spacing considerations of the startup pin.
16
Startup
Timing capacitor for the internal oscillator. This capacitor adjusts the oscillator frequency.
This pin biases the ramp compensation circuit, to adjust the amount of compensation that is added to
the current signal for stability purposes.
Positive current sense input. Designed to connect to the positive side of the current shunt.
This pin connects to the rectified input signal and provides current to the internal bias circuitry for the
startup period of operation.
NOTE: Pins 14 and 15 have not been used for clearance considerations due to the potential voltages present on pin 16. In order to
maintain proper spacing between the high voltage and low voltage pins, traces should not be placed on the circuit board between
pins 16 and 13.
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2
NCP1651
MAXIMUM RATINGS (Maximum ratings are those that, if exceeded, may cause damage to the device. Electrical Characteristics are
not guaranteed over this range.)
Rating
Symbol
Value
Unit
VCC
−0.3 to 18
V
Current Sense Amplifier Input (Pin 5)
V(IS+)
−0.3 to 1.0
V
FB/SD Input (Pin 8)
VFB/SD
−0.3 to 11
V
VCT
−0.3 to 4.5
V
Vstartup
−0.3 to 500
V
−0.3 to 6.5
V
Power Supply Voltage (Operating)
Output (Pin 1)
CT Input (Pin 3)
Line Voltage
All Other Pins
Thermal Resistance, Junction−to−Air
0.1 in2 Copper
0.5 in2 Copper
JA
Thermal Resistance, Junction−to−Lead
JL
50
°C/W
Pmax
0.77
W
Operating Temperature Range
Tj
−40 to 125
°C
Non−operating Temperature Range
Tj
−55 to 150
°C
Maximum Power Dissipation @ TA = 25°C
130
110
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Pins 1−6: Human Body Model 2000 V per JEDEC Standard JESD22, Method A114E.
Pins 1−6: Machine Model Method 200 V per JEDEC Standard JESD22, Method A115A.
Pin 8 is the HV startup to the device and is rated to the maximum rating of the part, or 500 V.
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3
NCP1651
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 14 volts, CT = 470 pF, C12 = 0.1 F, Tj = 25°C for typical
values. For min/max values Tj is the applicable junction temperature.)
Characteristic
Symbol
Min
Typ
Max
Unit
Fosc
90
100
110
kHz
−
25
−
250
kHz
dmax
0.95
−
−
−
Ramp Peak (Note 2)
VRpeak
−
4.0
−
V
Ramp Valley (Note 2)
VRvalley
−
0.100
−
V
Ramp Compensation Peak Voltage (Pin 4) (Note 2)
−
−
4.0
−
V
Ramp Compensation Current (Pin 4) (Note 2)
−
−
150
−
A
OSCILLATOR
Frequency
Tj = −40°C to +125°C
Frequency Range (Note 2)
Max Duty Cycle
AC ERROR AMPLIFIER (Vcomp = 2.0 V)
Input Offset Voltage
VIO
−
20
−
mV
Transconductance
gm
75
100
150
umho
IOsource
25
70
−
A
IOsink
−25
−70
−
A
Input Bias Current (Pin 5)
Ibias
40
60
80
A
Input Offset Voltage (Vcomp = 2.0) Tj = −40°C to +85°C
Tj = −40°C to +125°C
VIO
0
0
3.0
3.0
10
20
mV
ILIMthr
0.715
−
0.79
V
Output Gain (150 A/0.150 V) (Voltage Loop Outputs)
−
−
1000
−
umho
Output Gain (150 A/0.150 V) (AC E/A Output) (R10 = 15 k)
−
−
1000
−
umho
tLEB
−
200
−
ns
Bandwidth (Note 2)
−
−
1.5
−
MHz
PWM Output Voltage Gain (k = VPWM+ / (Vsense+ − Vsense−))
(Vpin 3 = Vpin 13 = 0)
Av
4.0
5.0
6.0
V/V
Current Limit Voltage Gain
(k = Vace/a− / (Vsense+ − Vsense−)) (Vpin59 = 0) (R7 = 15 k)
Av
8.0
10
12
V/V
Av
−
0.75
−
V/V
−
−
3.50
1.0
−
−
−
7.5
−
−
0.01
−
Output Source
Output Sink
CURRENT AMPLIFIER
Current Limit Threshold
Leading Edge Blanking Pulse (Note 2)
AVERAGE CURRENT COMPENSATION AMPLIFIER
Voltage Gain
REFERENCE MULTIPLIER
Dynamic Input Voltage Range
Ac Input (p−input) (Note 2)
Offset Voltage (a−input)
Multiplier Gain
(Note 2)
Vmax
Vmult out
k+
(VACńVramp pk) (VLOOPcomp * Voffset)
V
k
−
AC INPUT (Pin 5)
Input Bias Current (Total bias current for reference multiplier and current
compensation amplifier) (Note 2)
IINbias
A
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Verified by design.
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4
NCP1651
ELECTRICAL CHARACTERISTICS (continued) (Unless otherwise noted: VCC = 14 volts, CT = 470 pF, C12 = 0.1 F, Tj = 25°C for
typical values. For min/max values Tj is the applicable junction temperature.)
Characteristic
Symbol
Min
Typ
Max
Unit
Rsource
−
8.0
15
Rsink
−
8.0
15
Rise Time (CL = 1.0 nF)
tr
−
50
−
ns
Fall Time (CL = 1.0 nF)
tf
−
50
−
ns
VO(UV)
−
1.0
10
mV
VrefOUT
6.24
6.50
6.76
V
DVrefOUT
0
−
40
mV
IOPTO
0.8
1.1
1.4
mA
Opto Current Source (Shutdown, VFB = 0.1 V)
−
15
20
25
A
Input Voltage for 0 Duty Cycle (Note 3)
−
1.5
−
−
−
Input Voltage for 95% Duty Cycle (Note 3)
−
−
−
4.0
V
VOC
−
−
12
V
DRIVE OUTPUT
Source Resistance (1.0 Volt Drop)
Sink Resistance (1.0 Volt Drop)
Output Voltage in UVLO Condition (Drive out = 100 A in, 1 nF load)
VOLTAGE REFERENCE
Buffered Output (Iload = 0 mA, VCC = 12 VDC, Temperature)
Load Regulation (Buffered Output, Io = 0 to 10 mA, VCC > 10 V)
FB/SD PIN
Opto Current Source (Unit Operational, VFB = 0.5 V)
Open Circuit Voltage (Device Operational) (Note 3)
Clamp Voltage (Device in Shutdown Mode) (Note 3)
VCL
0.9
1.5
1.6
V
Shutdown Start Up Threshold (Pin 8) (Vout Increasing)
VSD
0.40
0.60
0.70
V
Shutdown Hysteresis (Pin 8)
VH
30
75
130
mV
STARTUP/UVLO
UVLO Startup Threshold (VCC Increasing)
VSU
10
10.75
11.5
V
UVLO Hysteresis (Shutdown Voltage = VSU – VH)
VH
0.8
1.0
1.2
V
Overtemperature Trip Point (Note 3)
TSD
140
160
180
°C
Overtemperature Hysteresis (Note 3)
−
−
30
−
°C
ISU
3.0
5.5
8.0
mA
5.0
8.5
12
mA
−
17
20
V
−
−
25
15
40
80
IBIAS
−
4.0
5.0
mA
IBshutdown
−
0.75
1.2
mA
HIGH VOLTAGE STARTUP (Pin 16 = 50 V)
Startup Current (out of pin 13) (VCC = UVLO − 0.2 V)
Startup Current (out of pin 13) (VCC = 0 V)
Min. Startup Voltage (pin 16, pin 13 current = 1 mA)
VSU
Line Pin Leakage (pin 16, Startup Circuit Inhibited)
(VDS = 400 V, TA = +25°C)
TA = +125°C
Ileak
A
TOTAL DEVICE
Operational Bias Current (CL(Driver) = 1.0 nF, fosc = 100 kHz)
Bias Current in Undervoltage Mode
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Verified by design.
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5
NCP1651
16
STARTUP
13
VCC
6.5 V
4V
6.5 V
Vref
REFERENCE
REGULATOR
20 A
3.8 k
12
UVLO
FB/SD
8
0.50 V
V−I
CONVERTER
+
-
÷8 COUNTER
SHUTDOWN
R
Q
Clk
OVER−
TEMPERATURE
SENSOR
A
AC INPUT
9
REFERENCE
MULTIPLIER
AC REFERENCE
BUFFER
0.75 Vline + k ⋅ Iin = Vref
P
+
-
AC REF
10
25 k
4V
V−I
+
AC ERROR
AMP
16 k
S
PWM
Q
R
SET
4.5 V
DOMINANT
DRIVER
AC COMP
RAMP
COMPENSATION
11
LEB
1
20 k
+
+
-
OSCILLATOR
60 k
GND
AVERAGE
CURRENT
COMPENSATION
CURRENT
SENSE
AMPLIFIER
−
2
RAMP COMP
4
3
CT
Figure 1. Block Diagram
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6
OUT
Iavg 7 6 Iavg−fltr
IS+
5
NCP1651
DRIVE
LATCH Q
AC Error Amp + Ramp Comp + Inductor Current
PWM
4V
GND
FB/SD
0.5 V
GND
OSCILLATOR
RAMP
OSCILLATOR
BLANKING PULSE
Figure 2. Switching Timing Diagram
7
7
VCC
8
1
2
3
7
8
7
7
10.8 V
9.8 V
STARTUP OFF
ENABLE
ON
OUTPUT MAX
CURRENT
0
FB/SD
0.5 V
0
SHUTDOWN
STARTUP
CURRENT LIMIT
Figure 3. Divide−by−Eight Counter Timing Diagram
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7
SHUTDOWN
7
8
NCP1651
Typical Performance Characteristics
(Test circuits are located in the document TND308/D)
12
5
10
PIN 6
PIN 7
8
3
Vpin 8 (V)
Vout (V)
4
2
4
1
0
2
0
100
200
300
400
0
500
0
200
400
600
800
1000 1200 1400 1600
IS+ (mV)
Isink (A)
Figure 4. Current Sense Amplifier Gain
Figure 5. FB/SD V−I Characteristics
0.9
5.0
−40°C
0.8
VCC = 14 V
BIAS CURRENT (mA)
0°C
0.7
CURRENT (mA)
6
25°C
80°C
0.6
0.5
125°C
0.4
0.3
0.2
4.5
4.0
3.5
3.0
0.1
0
2
4
6
8
2.5
−50
12
25
50
75
100
125
Figure 6. Bias Current in Shutdown Mode
Figure 7. Bias Current in Operating Mode
25°C
6
125°C
5
80°C
4
3
2
1
10
100
150
39
−40°C
0°C
7
1
0
TEMPERATURE (°C)
8
0
−25
VCC (V)
9
STARTUP CURRENT, PIN 16 (mA)
10
LEAKAGE CURRENT, PIN 16 (A)
0
34
29
24
19
14
9.0
−50
1000
−25
0
25
50
75
100
125
150
STARTUP PIN VOLTAGE (V)
TEMPERATURE (°C)
Figure 8. Startup Current versus High Voltage
Figure 9. Startup Leakage versus Temperature
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8
NCP1651
Typical Performance Characteristics
(Test circuits are located in the document TND308/D)
11.2
1.5
CLAMP VOLTAGE, PIN 8 (V)
TURN−ON
THRESHOLD (V)
10.8
10.5
10.2
TURN−OFF
9.8
9.5
−50
−25
0
25
50
75
100
0
125
0
2
4
6
8
10
12
VCC (V)
Figure 10. UVLO versus Temperature
Figure 11. FB/SD Clamp Voltage versus VCC
1000
2.5 V
FB/SD = 3.0 V
4
2.0 V
VCC, CAPACITANCE (F)
4.5
3.5
AC REF (V)
0.5
TEMPERATURE (°C)
5
3
2.5
1.8 V
2
1.5
1
0.5
0
1.0
100
10
1.6 V
0
1
2
4
3
1
5
1
10
100
1000
10,000
AC INPUT (V)
CHARGE TIME (ms)
Figure 12. Reference Multiplier Gain
Figure 13. VCC Cap Charge Time
100 k
4.40
NOTE: Ramp Valley
Voltage is Zero for
All Frequencies
4.35
4.30
CT (pF)
RAMP PEAK
10 k
1000
4.25
4.20
4.15
4.10
4.05
4.00
100
1
10
100
3.95
1000
0
50
100
150
200
250
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 14. CT versus Frequency
Figure 15. Ramp Peak versus Frequency
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9
300
NCP1651
Typical Performance Characteristics
(Test circuits are located in the document TND308/D)
10,000
FALL TIME
RISE TIME
CAPACITANCE
98
97
96
95
1000
94
93
0
50
100
150
200
250
100
300
0
50
100
150
200
250
300
FREQUENCY (kHz)
10% TO 90% DRIVE RISE AND FALL TIMES
Figure 16. Maximum Duty Cycle versus
Frequency
Figure 17. Capacitance versus 10% to 90%
Drive Rise and Fall Times
350
110
Vref
50 mV/div
10 mA
Vref Load
0 mA
FREQUENCY (kHz)
MAXIMUM DUTY CYCLE
99
105
100
95
90
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
2.0 s/div
Figure 18. Transient Response for 6.5 Volt
Reference
Figure 19. Frequency versus Temperature
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10
150
NCP1651
Typical Performance Characteristics
(Test circuits are located in the document TND308/D)
6.52
NOTE: Valley
Voltage is Zero
25°C
4.10
Vref (V)
6.50
4.08
4.06
4.04
−50
−40°C
6.48
6.46
−25
0
25
50
75
100
6.44
125
125°C
2
0
4
6
8
TEMPERATURE (°C)
Vref LOAD (mA)
Figure 20. Peak Ramp Voltage versus
Temperature
Figure 21. Vref Load Regulation
1
0.8
NO LOAD
Vref (V)
PEAK RAMP VOLTAGE (V)
4.12
0.6
10 k
0.4
3.3 k
0.2
0
−50
−25
0
25
50
75
100
TEMPERATURE (°C)
Figure 22. Vref in Shutdown Condition
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11
125
10
NCP1651
6.5 V
3.8 k
FB/SD
9
SHUT
DOWN
680
V−I
CONVERTER
5
A
REFERENCE
MULTIPLIER
AC INPUT
(Allows external converters to be synchronized to the switching frequency of this unit.)
Figure 23. External Shutdown Circuit
Vref
12
33 k
BAS16LT1
AC COMP
11
MMBT2907AL
R11
0.33 F
C11
Figure 24. Soft−Start Circuit
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NCP1651
NCP1651
THEORY OF OPERATION
Introduction
Optimizing the power factor of units operating off of AC
lines is becoming more and more important. There are a
number of reasons for this.
There are a growing number of government regulations
requiring Power Factor Correction PFC. Many of these are
originating in Europe. Regulations such as IEC1000−3−2
are forcing equipment to utilize input stages with topologies
other than a simple off−line front end which contains a
bridge rectifier and capacitor.
There are also system requirements that dictate the use of
PFC. In order to obtain the maximum power from an
existing circuit in a building, the power factor is very critical.
The real power available from such a circuit is:
Preal + Vrms
Irms
there are two causes of power factor degradation – phase
shift and distortion. Phase shift is normally caused by
reactive loads such as motors which are inductive, or
electroluminescent lighting which is highly capacitive. In
such a case the power factor is relatively simple to analyze,
and is determined by the phase shift.
PF + cos
Where is the phase angle between the voltage and the
current.
Reduced power factor due to distortion is more
complicated to analyze and is normally measured with AC
analyzers, although most circuit simulation programs can
also calculate power factor. One of the major causes of
distortion is rectification of the line into a capacitive filter.
This causes current spikes that do not follow the input
voltage waveform. An example of this type of waveform is
shown in the upper diagram in Figure 25.
A power converter with PFC forces the current to follow
the input waveform. This reduces the peak current, the rms
current and eliminates any phase shift.
In most modern PFC circuits, to lower the input current
harmonics, and improve the input power factor, designers
have historically used a boost topology. The boost topology
can operate in the Continuous (CCM), Discontinuous
(DCM), or Critical Conduction Mode.
Most PFC applications using the boost topology are
designed to use the universal input ac power 85−265 Vac, 50
or 60 Hz, and provide a regulated DC bus (typically
400 Vdc). In most applications, the load can not operate off
the high voltage DC bus, so a DC−DC converter is used to
provide isolation between the AC source and load, and
provide a low voltage output. The advantages to this system
configuration are, low THD, a power factor close to unity,
excellent voltage regulation, and transient response on the
isolated DC output. The major disadvantage of the boost
topology is that two power stages are required which lowers
the systems efficiency, increases components count, cost,
and increases the size of the power supply.
ON Semiconductor’s NCP1651 offers a unique
alternative for Power Factor Correction designs, where the
NCP1651 has been designed to control a PFC circuit
operating in a flyback topology. There are several major
advantages to using the flyback topology. First, the user can
create a low voltage isolated secondary output, with a single
power stage, and still achieve a low input current distortion,
and a power factor close to unity. A second advantage,
compared to the boost topology with a DC−DC converter, is
a lower component count which reduces the size and the cost
of the power supply.
The NCP1651 can operate in either the Continuous or
Discontinuous Mode of operation, the following analysis
will help to highlight the advantages of Continuous versus
Discontinuous Mode of operation.
PF
A typical off−line converter will have a power factor of
0.5 to 0.6, which means that for a given circuit breaker rating
only 50% to 60% of the maximum power is available. If the
power factor is increased to unity, the maximum available
power can be obtained.
There is a similar situation in aircraft systems, where a
limited supply of power is available from the on−board
generators. Increasing the power factor will increase the
load on the aircraft without the need for a larger generator.
V
I
v, i
t
OFF−LINE CONVERTER
V
I
v, i
t
PFC CONVERTER
Figure 25. Voltage and Current Waveforms
Unity power factor is defined as the current waveform
being in phase with the voltage, and undistorted. Therefore,
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13
NCP1651
one half the peak current of a flyback converter operating in
the Discontinuous Conduction Mode.
If we look at a single application and compare the results.
PO = 90 watts
Vin = 85−265 Vrms (analyzed at 85 Vrms input)
Efficiency = 80%
Pin = 108 W
VO = 48 Vdc
Freq = 100 kHz
Transformer turns ration N = 4
Continuous Conduction Mode
A second result of running in DCM can be higher input
current distortion, EMI, and a lower Power Factor, in
comparison to CCM. While the higher peak current can be
filtered to produce the same performance result, it will
require a larger filter.
A simple Fast Fourier Transform (FFT) was run in Spice
to provide a comparison between the harmonic current
levels for CCM and DCM. The harmonic current levels will
affect the size of the input EMI filter which in some
applications are required to meet the levels of C.I.S.P.R. In
the SPICE FFT model we did not add any front end filtering
so the result of the analysis could be compared directly.
Continuous Mode (CCM)
To force the inductor current to be continuous over the
majority of the input voltage range (85−265 Vac), LP needs
to be at least 1 mH. Figure 26 shows the typical current
through the windings of the flyback transformer. During
switch on period, this current flows in the primary and
during the switch off time it flows in the secondary.
300
250
IPK
Iavg
(mA)
200
150
100
TIME
Figure 26.
50
The peak current is:
IPK = Iavg + ((1.414 ⋅ Vin sin ⋅ ton ⋅ 2)/LP)
0
0.2
where Iavg = 1.414 ⋅ Pin/Vin sin
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8 2.0
FREQUENCY (MHz)
Ton = T/((NS/NP ⋅ 1.414 ⋅ Vin sin /VO) +1)
Figure 28. Continuous Conduction Mode
Ton = 6.19 s
At the 100 kHz switching frequency, the rms value from
the FFT is 260 mA, and the 2nd harmonic (200 kHz) is
55 mA rms.
IPK = (1.414 ⋅ 113)/85 sin + (1.414 ⋅ 85 ⋅ 6.15 s ⋅ 2) /1 mH
= 3.35 A
Discontinuous Mode (DCM)
In the discontinuous mode of operation, the inductor
current falls to zero prior to the end of the switching period
as shown in Figure 27.
2.8
2.4
2.0
IPK
(A)
1.6
Iavg
1.2
0.8
TIME
0.4
Figure 27.
0
To ensure DCM, LP needs to be reduced to approximately
100 H.
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8 2.0
FREQUENCY (MHz)
Figure 29. Discontinuous Conduction Mode
IPK = (Vin sin ⋅ 1.414 ⋅ ton)/LP
At 100 kHz the rms value from the FFT are 2.8 A, and the
2nd harmonic (200 kHz) is 500 mA rms.
IPK = 1.414 ⋅ 85 sin 90 ⋅ 5.18 s/100 H = 6.23 A
The results show that the peak current for a flyback
converter operating in the Continuous Conduction Mode is
www.onsemi.com
14
NCP1651
Results
It is clear from the result of our analysis that a flyback PFC
converter operating in CCM has half the peak current and
one tenth the fundamental (100 kHz) harmonic current
compared to a flyback PFC converter operating in DCM.
The results are lower conduction losses in the MOSFET, and
secondary rectifying diode, and a smaller input EMI filter if
the designer needs to meet the requirements C.I.S.P.R.
conducted emission levels. On the down side to CCM
operation, the flyback transformer will be larger because of
the required higher primary inductance.
The advantages to operating in DCM include lower
switching losses because the current falls to zero prior to the
next switching cycle, and smaller transformer size.
It will ultimately be up to the designer to perform a
trade−off study to determine which topology, Boost versus
Flyback, Continuous versus Discontinuous Mode of
operation will meet all the system performance
requirements. But the recent introduction of the NCP1651
allows the system designer one additional option.
For an average current mode flyback topology based PFC
converter, determining the transformer parameters (primary
inductance and turns ratio) involves several trade−offs.
These include peak−to−average current ratio (higher
inductance or turns ratio result in lower peak current),
switching losses (higher turns ratio leads to higher peak
voltage and higher switching losses), CCM vs. DCM
operation (lower values of turns ratio or higher values of
inductance extend the CCM range) and range of duty cycles
over the operational line and load range. ON Semiconductor
has designed an Excel−based spreadsheet to help design
with the NCP1651 and balance these trade−offs. The design
aid is downloadable free−of−charge from our website
(www.onsemi.com).
The ideal solution depends on the specific application
requirements and the relative priority between factors such
as THD performance, cost, size and efficiency. The design
aid allows the designer to consider different scenarios and
settle on the best solution foe a given application. Following
guidelines will help in settling towards the most feasible
solution.
1. Turns Ratio Limitations: While higher turns ratio
can limit the reflected primary voltage and current,
it is constrained by the inherent limitations of the
flyback topology. A turns ratio of higher than 20:1
will result in very high leakage inductance and
lead to high leakage spikes on the primary switch.
Thus, practical application of this approach is
restricted to output voltages 12 V and above.
2. CCM Operation: The NCP1651 is designed to
operate in both CCM and DCM modes. However,
the CCM operation results in much better THD
than the DCM operation. Thus, it is recommended
that the circuit be designed to operate in CCM at
the specified test condition for harmonics
compliance (typically at 230 V, full load). Please
keep in mind that at or near zero crossing
( fz:
Av + RfbńRdc1
10
Iin
IS+
MODULATOR AND OUTPUT STAGE
R7
Iin
+
Vref RS 75, 000
Vline Rac2
Rac1 ) Rac2
ǒ Ǔ ǒ
Np
Vout
T * ton
+
RL
ton
Iin
Ns
fp +
Ǔ
1
2 RL C
Figure 43. Voltage Regulation Loop
Loop Model
The model for the voltage loop has been broken down into
six sections. The voltage divider, error amplifier, and opto
Transfer are external to the chip, and the reference signal,
modulator and output stage are internal.
The modulator and output stage circuitry is greatly
simplified based on the assumption that that poles and zeros
in the current feedback loop are considerably greater than
the bandwidth of the overall loop. This should be a good
assumption, because a bandwidth in the kilohertz is
necessary for a good current waveform, and the voltage error
amplifier needs to have a bandwidth of less than the lowest
line frequency that will be used.
There are two poles in this circuit. The output filter has a
pole that varies with the load. The pole on the voltage error
amplifier will be determined by this analysis.
Voltage Error Amplifier
The voltage error amplifier is constrained by the two
equations. When this amplifier is compensated with a
pole−zero pair, there will be a unity gain pole which will be
cancelled by the zero at frequency fz. The corresponding
bode plot would be:
GAIN (dB)
20
0
Unity Gain
AV
fz
−20
Voltage Divider
The voltage divider is located on the secondary side
circuitry. It is a simple resistive divider that reduces the
output voltage to the level required by the internal reference
on the voltage error amplifier. If the amplifier circuit of
Figure 42 is used, there are four resistors instead of 2. To
determine the gain of this circuit, Rdc1 is the equivalent of
the upper two resistors, 9.31 k and 453 Ohms respectively,
and Rdc2 is the equivalent of the lower two resistors, 422 and
5.23 k respectively.
f, FREQUENCY
Figure 44. Pole−zero Bode Plot
The gain at frequencies greater than fz is determined by
Rfb. Once Rfb is determined, the value of Cfb can be easily
calculated using the formula for fz.
www.onsemi.com
29
NCP1651
Optocoupler Transfer
The optocoupler is used to allow for galvanic isolation for
the error signal from the secondary to primary side circuits.
The gain is based on the Current Transfer Ratio of the
device. This can change over temperature and time, but will
not result in a large change in dB.
The recommended capacitor at pin 8 is 0.022 F. If a larger
capacitor is used, the pole may become low enough that it
will have an effect on the gain phase plots near the unity gain
crossover frequency. In this case and additional zero will be
required in the error amplifier bias circuitry.
The gain of the loop will vary as the input voltage changes.
It is recommended that the compensation for the error
amplifier be calculated under high line, full load conditions.
This should be the greatest bandwidth that the unit will see.
By necessity, the unity gain (0 dB) loop bandwidth for a
PFC unit, must be less than the line frequency. If the
bandwidth approaches or exceeds the line frequency, the
voltage error amplifier signal will have frequency
components in its output that are greater than the line
frequency. These components will cause distortion in the
output of the reference amplifier, which is used to shape the
current waveform. This in turn will cause distortion in the
current and reduce the power factor.
Typically the maximum bandwidth for a 60 Hz PFC
converter is 10 Hz, and slightly less for a 50 Hz system. This
can be adjusted to meet the particular requirements of a system.
The unity gain bandwidth is determined by the frequency at
which the loop gain passes through the 0 dB level.
For stability purposes, the gain should pass through 0 dB
with a slope of −20 dB for approximately on decade on either
side of the unity gain frequency. This assures a phase margin
of greater than 45°.
The gain can be calculated graphically using the equations
of Figure 18 as follows:
Divider: Calculate V′/Vo in dB, this value is constant so it
will not change with frequency.
Optocoupler Transfer: Calculate Vfb/Vea using the equation
provided. Convert this value into dB.
Reference Signal: Calculate Vref/Vfb using the peak level of
the AC input signal at high line that will be seen on pin 9.
Convert this to dB. This is also a constant value.
Modulator and Output Stage: Calculate the gain in dB for
DIo/DVref for the modulator, and also the gain in dB for the
output stage (DVout/DIin). Calculate the pole frequency. The
gain will be constant for all frequencies less than fp. Starting
at the pole frequency, this gain will drop off at a rate of
20 dB/decade.
Plot the sum of all of the calculated values. Be sure to
include the output pole. It should resemble the plot of
Figure 45. This plot shows a gain of 34 dB until the pole of
the output filter is reached at 3 Hz. After that, the gain is
reduced at a rate of 20 dB/decade.
Reference Signal
The error signal is transmitted to the primary side circuit
via. the optocoupler, is converted to a current by the V−I
converter and is then used as an input to the reference
multiplier. The gain of this block is dependent on the AC
input voltage, because of the multiplier which requires two
inputs for one output.
Modulator and Output Stage
The modulator receives an input from the reference
multiplier and forces the current to follow the shape and
amplitude. The is an internal loop within this section due to
the current sense amplifier. Based on the assumptions listed
in the introduction to this analysis, this is not analyzed
separately.
The equation for the gain is good for frequencies below
the pole. There is a single pole due to the output filter. Since
the NCP1651 is a current mode converter, the inductor is not
part of the output pole as can be seen in that equation.
The modulator and output stage transfer functions have
been split into two sets of equations. The first defines the
relationship between the input current and AC reference
signal, and the later, define the output stage gain and pole.
Due to the nature of a flyback transformer, the gain of the
output stage is dependant on the duty cycle (ton/T). For
continuous mode operation, the on−time is:
ton + N
S
NP
T
@
Ǹ2@Vrms
Vout
)1
Calculating the Loop Gain
At this point in the design process, all of the parameters
involved in this calculation have been determined with the
exception of the pole−zero pair on the output of the voltage
error amplifier.
All equations give gains in absolute numbers. It is
necessary to convert these to the decibel format using the
following formula:
A(dB) = 20 Log10 (A)
For example, the voltage divider would be:
A+
5.6 k
+ 0.0099
560 k ) 5.6 k
A(dB) = 20 Log10 0.0099 = −40 dB
www.onsemi.com
30
NCP1651
cut in half or more and probably remain stable. This can be
tested in the circuit, or simulated with a model in SPICE or
a similar analysis program.
The gain and phase plots of the completed loop are shown
in Figures 46 and 47. These include the effects of all of the
stages shown.
40
35
30
GAIN (dB)
25
20
15
80
10
5
60
0
−5
40
0.01
0.1
1
10
FREQUENCY (Hz)
100
GAIN (dB)
−10
−15
1000
Figure 45. Forward Gain Plot
0
For a crossover frequency of 10 Hz, the error amplifier
needs a gain of −25 dB at 10 Hz, since the forward gain is
equal to 25 dB at this frequency. The high frequency gain of
the error amplifier is:
AVhf = Rfb / Rdc1
Where Rdc1 is the output voltage divider resistor that is
connected from the output of the converter to the input of the
error amplifier. If the output circuit of Figure 42 is used, Rdc1
would be 9.31 k + 453 , or 9.76 k. A gain of −25 dB is
equal to a divider ratio of:
AV = 10(−25/20) = 0.056
so, Rfb / Rdc1 = 0.056
−20
−40
0.01
0.1
1
10
FREQUENCY (Hz)
100
1000
Figure 46. Loop Gain Plot
−75
−90
−105
PHASE (°C)
or, Rfb = 0.056 x 9.76 k = 546
−120
The closest standard value resistor is 560 .
To offset the 2 Hz pole of the output filter, the error
amplifier should have a zero of 2 Hz or slightly higher. For
a 2 Hz zero, the compensation capacitor, Cfb can be
calculated by:
Cfb +
20
−135
−150
−165
1
+ 95 F
2 Rfb 3 Hz
−180
100 F is the closest standard value capacitor and would
be a good choice. This solution will provide a phase margin
of close to 90°. In practice the value of capacitance could be
0.01
0.1
1
10
FREQUENCY (Hz)
Figure 47. Loop Phase Plot
www.onsemi.com
31
100
1000
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR, DYE #1
BASE, #1
EMITTER, #1
COLLECTOR, #1
COLLECTOR, #2
BASE, #2
EMITTER, #2
COLLECTOR, #2
COLLECTOR, #3
BASE, #3
EMITTER, #3
COLLECTOR, #3
COLLECTOR, #4
BASE, #4
EMITTER, #4
COLLECTOR, #4
STYLE 4:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
STYLE 5:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
DRAIN, DYE #1
DRAIN, #1
DRAIN, #2
DRAIN, #2
DRAIN, #3
DRAIN, #3
DRAIN, #4
DRAIN, #4
GATE, #4
SOURCE, #4
GATE, #3
SOURCE, #3
GATE, #2
SOURCE, #2
GATE, #1
SOURCE, #1
STYLE 6:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
STYLE 7:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
SOURCE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE P‐CH
SOURCE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE N‐CH
COLLECTOR, DYE #1
COLLECTOR, #1
COLLECTOR, #2
COLLECTOR, #2
COLLECTOR, #3
COLLECTOR, #3
COLLECTOR, #4
COLLECTOR, #4
BASE, #4
EMITTER, #4
BASE, #3
EMITTER, #3
BASE, #2
EMITTER, #2
BASE, #1
EMITTER, #1
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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