NCP2817BFCCT2G

NCP2817 NOCAP] LongPlay Headphone Amplifier NCP2817 is a dual LongPlay true ground headphone amplifier designed for portable communication device applications such as mobile phones. This part is capable of delivering typical 27 mW of continuous average power into a 32 W load from a 1.8 V power supply with a THD+N of 1%. Based on the power supply delivered to the device, an internal power management block generates a symmetrical positive and negative voltage. Thus, the internal amplifiers provide outputs referenced to Ground and the losses are reduced which helps to increase the battery life. In this NOCAP configuration, the two external heavy coupling capacitors can be removed. It offers significant space and cost savings compared to a typical stereo application. NCP2817 is available with internal gain of −1.5 V/V. It reaches a superior −100 dB PSRR and noise floor. Thus, it offers high fidelity audio sound, as well as a direct connection to the battery. It contains circuitry to prevent from “Pop & Click” noise that would otherwise occur during turn−on and turn−off transitions. The device is available in 12 bump CSP package (1.62 x 1.22, 0.4P) which helps to save space on the board. Features • NOCAP Output Eliminates DC−Blocking Capacitors: www.onsemi.com MARKING DIAGRAM 12 PIN CSP FC SUFFIX CASE 499BJ A L Y WW G 817BC ALYWW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN ASSIGNMENT A1 A2 A3 A4 CPM PVM INL INR B1 B2 B3 B4 PGND /SD AGND SGND C1 C2 C3 C4 CPP VP OUTL OUTR ♦ • • • • • • • • • • • Saves Board Area ♦ Saves Component Cost ♦ No Low−Frequency Response Attenuation LongPlay Architecture: Increase the Battery Life High PSRR (−100 dB): Direct Connection to the Battery High SNR Performance (100 dB) “Pop and Click” Noise Protection Circuitry Internal Gain (−1.5 V/V) or External Adjustable Gain Ultra Low Current Shutdown Mode High Impedance Mode 1.6 V − 5.5 V Operation Thermal Overload Protection Circuitry CSP 1.62 x 1.22, 0.4P These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant (Top View) 12−Pin 1.2 x 1.6 mm CSP ORDERING INFORMATION See detailed ordering and shipping information on page 9 of this data sheet. Typical Applications • Headset Audio Amplifier for ♦ ♦ ♦ ♦ Cellular Phones MP3 player Personal Digital Assistant and Portable Media Player Portable devices © Semiconductor Components Industries, LLC, 2015 November, 2015 − Rev. 0 1 Publication Order Number: NCP2817/D CPM VRP CPP VP NCP2817 PVM Power Management & Charge Pump PGND VRM VRP INL − OUTL + /SD Biasing VRM Pop & Click Suppression VRP + INR OUTR − SGND AGND VRM Figure 1. Block Diagram PIN FUNCTION DESCRIPTION Pin Pin Name A1 CPM Input / Output Charge pump flying capacitor negative terminal. A 1 mF ceramic capacitor to CPP is required A2 PVM Output Charge pump output. A 1 mF ceramic capacitor to ground is needed A3 INL Input Left input of the audio source A4 INR Input Right input of the audio source B1 PGND Ground B2 /SD Input Type Description Power ground. This pin should be connected directly to the ground plane. Enable activation. B4 SGND Ground Sense Ground. Connect to shield terminal of headphone jack or ground plane. C1 CPP Input / Output Charge pump flying capacitor positive terminal. A 1 mF ceramic capacitor to CPM is required C2 VP Power Positive supply voltage. Connected to single secondary cell Lithium−Ion battery or any other kind of power supply C3 OUTL Output Left audio channel output signal C4 OUTR Output Right audio channel output signal B3 AGND Ground Analog ground. This pin should be connected directly to the GND plane. Careful layout and no direct connection to other ground pins are required to ensure good noise immunity www.onsemi.com 2 NCP2817 MAXIMUM RATINGS Rating Symbol Value Unit VP −0.3 to + 6.0 V Vmr1 −0.3 to VP + 0.3 V Human Body Model (HBM) ESD Rating are (Notes 2 and 3) ESD HBM 2000 V Machine Model (MM) ESD Rating are (Note 2 and 3) ESD MM 200 V VP Pin: Power Supply Voltage (Note 1) /SD Pin: Input CSP 1.62 x 1.22, 0.4P package (Note 6 and 7) Thermal Resistance Junction to Case °C/W RqJC (Note 7) Operating Ambient Temperature Range TA −40 to + 85 °C Operating Junction Temperature Range TJ −40 to + 125 °C Maximum Junction Temperature (Note 6) TJMAX + 150 °C Storage Temperature Range TSTG −65 to + 150 °C Moisture Sensitivity (Note 5) MSL Level 1 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25°C. 2. According to JEDEC standard JESD22−A108B. 3. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114 for all pins. Machine Model (MM) ±200 V per JEDEC standard: JESD22−A115 for all pins. 4. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 class II. 5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A. 6. The thermal shutdown set to 150 °C (typical) avoids irreversible damage on the device due to power dissipation. 7. The RqCA is dependent on the PCB heat dissipation. The maximum power dissipation (PD) is dependent on the min input voltage, the max output current and external components selected. R qCA + 125 * T A PD * R qJC ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for VP = 3.6 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and VP = 3.6 V. Symbol VBATTERY Parameter Conditions Supply voltage range ISD Shutdown current IQ Quiescent current RIN Input resistance RSD /SD pull−down resistor Min High−level input voltage SD pin VIL Low−level input voltage SD pin UVLO UVLO threshold UVLOHYS Max Unit 5.5 V 1 mA 2.3 3.0 mA 10 12.5 kW 1.6 VP = 1.8 V 7.5 Maximum input signal swing VIH Typ 300 kW 2.8 VPP 1.2 V 0.4 1.4 V UVLO hysteresis 100 mV TSD Thermal shutdown temperature 160 °C ± 0.5 mV 1 ms VOS Output offset voltage TWU Turning On time VLP Max Output Swing (peak value) PO Max Output Power (Note 8) Falling edge V Input AC grounded VP = 1.8 V, Headset = 32 W VP = 1.8 V, THD+N = 1% Headset = 16 W Headset = 32 W 8. Guaranteed by design and characterized. 9. Typical application circuit as depicted www.onsemi.com 3 1.13 Vpeak mW 20 41 27 NCP2817 ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for VP = 3.6 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and VP = 3.6 V. Symbol PO Parameter Max Output Power Conditions Min Typ VP = 3.6 V, THD+N = 1% Headset = 16 W Headset = 32 W 42 27 Headset ≥ 16 W −95 Crosstalk (Note 8) Max Unit mW −80 dB PSRR Power Supply Rejection Ratio Inputs Shorted to Ground F = 217 Hz to 1 kHz −100 dB THD+N Total Harmonic Distortion + Noise Headset = 16 W POUT = 10 mW, F = 1 kHz 0.02 % THD+N Total Harmonic Distortion + Noise Headset = 32 W POUT = 10 mW, F = 1 kHz 0.02 % THD+N Total Harmonic Distortion + Noise Headset = 32 W VOUTR − VOUTL= 400 mV, F = 1 kHz −80 dB SNR Signal to noise ratio 100 dB ZSD Output Impedance in Shutdown Mode 12 kW B Version only TA = +25°C FSW1 Headset charge pump switching frequency POUT > 500 mW 1 MHz FSW2 Headset charge pump switching frequency POUT < 500 mW 125 kHz AV Voltage Gain −2 ±0.3 Max Channel to channel gain tolerance −1.54 8. Guaranteed by design and characterized. 9. Typical application circuit as depicted www.onsemi.com 4 −1.5 +2 −1.46 % V/V NCP2817 TYPICAL OPERATING CHARACTERISTICS 1 1 Right Left 0.1 THD+N (%) THD+N (%) Right Left 0.01 0.001 10 100 1000 FREQUENCY (Hz) 10k 0.1 0.01 0.001 10 100k Figure 2. THD+N vs Frequency @ Pout = 10 mW, RL = 32 W, VP = 1.8 V THD+N (%) THD+N (%) 1 0.1 0.01 0.1 0.01 0.01 0.1 1 10 0.001 0.01 100 Pout (W) 1 Pout (W) Figure 4. THD+N vs Pout @ 255C Load = 32 W, VP = 1.8 V Figure 5. THD+N vs Pout @ 255C Load = 16 W, VP = 1.8 V 0 0.1 10 100 0 Right Left −20 −40 CROSSTALK (dB) CROSSTALK (dB) 100k Right Left 1 −60 −80 −100 Right Left −40 −60 −80 −100 −120 −140 10 10k 10 Right Left −20 1000 FREQUENCY (Hz) Figure 3. THD+N vs Frequency @ Pout = 10 mW, RL = 16 W, VP = 1.8 V 10 0.001 0.001 100 100 1000 FREQUENCY (Hz) −120 10 10k Figure 6. PSRR vs Frequency @ VP = 3.6 V 100 1000 FREQUENCY (Hz) Figure 7. Crosstalk vs. Frequency @ VP = 3.6 V Pout = 10 mW www.onsemi.com 5 10k NCP2817 TYPICAL OPERATING CHARACTERISTICS 3.0 700 2.5 600 500 Pdis (mW) 2.0 Iq (mA) Vp = 1.6 V Vp = 1.8 V Vp = 2.5 V Vp = 3.6 V Vp = 4.2 V Vp = 5 V Vp = 5.5 V 1.5 1.0 400 300 200 0.5 100 0 0 1.5 2.5 3.5 4.5 5.5 0 20 40 60 80 100 120 VP (V) Pout (mW) Figure 8. Quiescent Current vs VP (VP Rising) Figure 9. Power Dissipation vs Pout @ 255C (Pout Left + Right) 40 70 35 60 30 140 50 (mW) (mW) 25 20 40 30 15 20 10 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1.5 5.5 Vp (V) 3.5 Vp (V) Figure 10. Maximum Output Power vs Vp (THD+N < 1%, RL = 32 W) Figure 11. Maximum Output Power vs Vp(THD+N < 1%, RL = 16 W) www.onsemi.com 6 2.0 2.5 3.0 4.0 4.5 5.0 5.5 NCP2817 DETAIL OPERATING DESCRIPTION VBATTERY CPM VRP CPP VP CFLY Power Management & Charge Pump PVM PGND CPM VRM Audio Left Input CINL VRP INL − OUTL + /SD Biasing VRM Pop&Click Suppression VRP Audio Right Input CINR + INR OUTR − SGND AGND VRM Figure 12. Typical Application Circuit Detailed Descriptions it generates the symmetrical positive and negative rails that supplies amplifiers output stage. This feature allows the output of the amplifiers to be biased around the ground level and eliminates need of huge DC voltage blocking capacitors. The NCP2817 stereo headphone amplifier features the ON Semiconductor NOCAP architecture that eliminates the large output DC−blocking capacitors required by conventional headphone amplifier. An integrated power supply block generates low noise positive (VRP) and negative (VRM) voltages from the positive supply voltage (VP). The stereo headphone amplifiers operate from these symmetrical supplies. Amplifiers output are referenced to ground (GND), instead of DC voltage (typically VP/2) for conventional headphone amplifiers. The NCP2817 integrates two true ground amplifiers, an Under Voltage Lock Out (UVLO), a short circuit protection and a thermal shutdown circuitry. In addition, a special circuit is embedded to eliminate pop and click noise that occurs during turn on and turn off time. NCP2817 has an embedded gain setting network set to 1.5 V/V. LongPlay Architecture The “LongPlay” feature, based on unique ultra low current consumption architecture saves more battery life by reducing the quiescent current depending on the load. Current Limit Protection Circuit The NCP2817 output power stage features a protection circuitry against short to ground. The current is limited to 300 mA typical when an output is shorted to GND and a signal is applied to the input. Thermal Overload Protection Internal amplifiers are switched off when the temperature exceed 160°C, and will be switched back on when the temperature decreases below 140°C. NOCAPTM NOCAP is a patented architecture which requires only two small ceramic capacitors. From single positive only rail, www.onsemi.com 7 NCP2817 Under Voltage Lockout Power Supply Decoupling Capacitor (C1) When the battery voltage decreases below 1.4 V, the amplifiers are turned off. The hysteresis to turn back on the device is 100 mV. The NCP2817 is a NOCAP amplifier and proper power supply bypassing is critical to reduce noise, high THD+N and PSRR performances. It is recommended to use a 1uF X5R / X7R ceramic capacitor and place it as close as possible to the VP pin. Pop and Click Suppression Circuitry The NCP2817 includes a special circuitry to eliminate any pop and click noise during turn on and turn off time. During uncontrolled turn on and turn off sequences, normal amplifiers would create an output offset. This offset drives the loudspeaker and generates a parasitic noise called “pop and click noise”. The NCP2817 carefully controls the amplifier output stages during turn on and off sequences to eliminate this problem. Input capacitor selection The input coupling capacitor blocks the DC voltage at the amplifier input terminal. This capacitor creates a high−pass filter with the RIN input resistor (10 kW for NCP2817). The size of the capacitor must be large enough to cut off low frequencies without severe attenuation in the audio bandwidth (20 Hz − 20 kHz). The cut off frequency for the input high−pass filter is: Fc + Shutdown Function The device enters in shutdown mode when shutdown signal is low. During the shutdown mode, the DC quiescent current of the circuit does not exceed 1 mA. In this configuration, the output impedance is 20 kW on each output. Layout Recommendation Minimize trace impedance of the power, the ground and all output traces. The voltage drop between NCP2817 and the headset load results in decrease of output power and efficiency. We strongly recommend using wide traces for power supply inputs to optimize the power supplies efficiency and regulation performances. Good ground connection improves the amplifier immunity to external switching noise, improves crosstalk between channels as well as general audio performances. We also recommend wide PCB traces for the power outputs routing. If possible, we recommend to use local Ground and power planes. The power supply decoupling capacitor CBYP will help to minimize the input voltage ripple during fast load transients. It is important to minimize traces impedances from CBYP to GND plane and from CBYP to VP pin as close as possible of the VP pin. CBYP should be placed as close as possible to the VP pin. The charge pump creates the VPM negative voltage that supplies the amplifiers. CFLY and CPVM capacitors location and access impedances are also critical. Connect CFLY and CPVM as close as possible of the NCP2817 and route their terminal to the associated pin with wide traces to minimize impedance and optimize the charge pump ripple and efficiency performances. In addition, the CFLY and CPVM capacitors as well as the traces connecting capacitors to the device should be kept away from the audio input and output traces to avoid any switching noise coupling with the audio signal. AGND is the ground reference for all internal analog features so, particular attention should govern the AGND pin connection to the Ground reference plane. AGND pin should be directly connected to the board Ground reference plane and keep it separated from other ground connections. The AGND to GND ground reference plane trace should not be shared with the trace between SGND or PGND and the Ground plane. 1 2pR inC in With RIN = 10 kW A Fc < 20 Hz is recommended. Charge Pump Capacitor Selection Use ceramic capacitor with low ESR for better performances. X5R / X7R capacitor is recommended. The CFLY flying capacitor serves to transfer charge during the generation of the negative voltage and directly affects load regulation and charge pump output impedance. A too low value results in poor current performance while higher value increases charge pump regulation and lowers output impedance (until internal switches RDS(on) becomes predominant). We recommend 1 mF, but lower values can be uses in systems with lower audio power requirements. The CPVM capacitor must be equal at least to the CFLY capacitor to allow maximum transfer charge. In addition, the ESR of CPVM capacitor directly affects ripple on PVM as well as charge pump output impedance. We recommend 1 mF, but lower values can be uses in systems with lower audio power requirements. Table 1. SUGGEST TYPICAL VALUE AND MANUFACTURER Value Reference Package Manufacturer 1 mF C1005X5R0J105K 0402 TDK 1 mF GRM155R60J105K19 0402 Murata www.onsemi.com 8 NCP2817 ORDERING INFORMATION Device NCP2817BFCCT2G Package Shipping† WLCSP12 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NOCAP is a trademark of Semiconductor Components Industries, LLC (SCILLC). www.onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WLCSP12 1.62x1.22x0.539 CASE 499BJ ISSUE D DATE 02 JUN 2022 GENERIC MARKING DIAGRAM* XXXXX ALYWW G XXXXX A L Y WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON48124E WLCSP12 1.62x1.22x0.539 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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