NCP4304A, NCP4304B
Secondary Side
Synchronous Rectification
Driver for High Efficiency
SMPS Topologies
The NCP4304A/B is a full featured controller and driver tailored to
control synchronous rectification circuitry in switch mode power
supplies. Due to its versatility, it can be used in various topologies such
as flyback, forward and Half Bridge Resonant LLC.
The combination of externally adjustable minimum on and off times
helps to fight the ringing induced by the PCB layout and other
parasitic elements. Therefore, a reliable and noise less operation of the
SR system is insured.
The extremely low turn off delay time, high sink current capability
of the driver and automatic package parasitic inductance
compensation system allow to maximize synchronous rectification
MOSFET conduction time that enables further increase of SMPS
efficiency.
Finally, a wide operating VCC range combined with two versions of
driver voltage clamp eases implementation of the SR system in 24 V
output applications.
Features
• Self-Contained Control of Synchronous Rectifier in CCM, DCM,
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
and QR Flyback Applications
Precise True Secondary Zero Current Detection with Adjustable
Threshold
Automatic Parasitic Inductance Compensation Input
Typically 40 ns Turn off Delay from Current Sense Input to Driver
Zero Current Detection Pin Capability up to 200 V
Optional Ultrafast Trigger Interface for Further Improved
Performance in Applications that Work in Deep CCM
Disable Input to Enter Standby or Low Consumption Mode
Adjustable Minimum On Time Independent of VCC Level
Adjustable Minimum Off Time Independent of VCC Level
5 A/2.5 A Peak Current Sink/Source Drive Capability
Operating Voltage Range up to 30 V
Gate Drive Clamp of Either 12 V (NCP4304A) or 6 V (NCP4304B)
Low Startup and Standby Current Consumption
Maximum Frequency of Operation up to 500 kHz
SOIC−8 Package
These are Pb−Free Devices
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8
1
1
DFN8
MN SUFFIX
CASE 488AF
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAMS
8
4304x
ALYW G
G
NCP
4304x
ALYWG
G
SOIC−8
DFN8
1
4304x
A
L
Y
W
G
= Specific Device Code
x = A or B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(*Note: Microdot may be in either location)
PINOUT INFORMATION
VCC
MIN_TOFF
MIN_TON
TRIG/DIS
Notebook Adapters
High Power Density AC/DC Power Supplies
Gaming Consoles
All SMPS with High Efficiency Requirements
© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 6
8
7
6
5
DRV
GND
COMP
CS
(NOTE: For DFN the exposed pad must be either
unconnected or preferably connected to ground.
The GND pin must be always connected to ground.)
ORDERING INFORMATION
Package
Shipping†
NCP4304ADR2G
SOIC−8
(Pb−Free)
2,500 /
Tape & Reel
NCP4304BDR2G
SOIC−8
(Pb−Free)
2,500 /
Tape & Reel
NCP4304AMNTWG
DFN8
(Pb−Free)
4,000 /
Tape & Reel
NCP4304BMNTWG
DFN8
(Pb−Free)
4,000 /
Tape & Reel
Device
Typical Applications
•
•
•
•
1
2
3
4
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1
Publication Order Number:
NCP4304/D
NCP4304A, NCP4304B
NCP4304
RMIN_TOFF
RMIN_TON
C2
VCC
DRV
MIN_TOFF GND
MIN_TON COMP
TRIG/DIS
CS
+Vbulk
+Vout
TR1
M1
M3
N2
+
C4
LLC
STAGE
CONTROL
RTN
N1
M2
N3
M4
C1
NCP4304
RMIN_TOFF
RMIN_TON
C3
DRV
VCC
GND
MIN_TOFF
MIN_TON COMP
CS
TRIG/DIS
D1
OK1
Figure 1. Typical Application Example – LLC Converter
Vbulk
TR1
+
C1
R1
C2
+Vout
D3
VCC
+
C3
FLYBACK
CONTROL
CIRCUITRY
C5
D4
GND
C4
DRV
FB
+
M2
M1
RMIN_TOFF
R3
CS
R2
R5
R4
RMIN_TON
VCC
DRV
MIN_TOFF GND
MIN_TON COMP
TRIG/DIS
CS
D5
OK1
R6
Figure 2. Typical Application Example − DCM or QR Flyback Converter
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2
NCP4304A, NCP4304B
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
1
VCC
Supplies the driver
Pin Description
2
MIN_TOFF
Minimum off time adjust
Adjust the minimum off time period by connecting resistor to ground.
3
MIN_TON
Minimum on time adjust
Adjust the minimum on time period by connecting resistor to ground.
4
TRIG/DIS
Forced reset input
This ultrafast input turns off the SR MOSFET in CCM applications. Activates
sleep mode if pulled up for more than 100 ms.
5
CS
Current sense of the SR
MOSFET
This pin detects if the current flows through the SR MOSFET and/or its body
diode. Basic turn off detection threshold is 0 mV. A resistor in series with this
pin can modify the turn off threshold if needed.
6
COMP
Compensation inductance
connection
7
GND
IC ground
8
DRV
Gate driver output
Supply terminal of the controller. Accepts up to 30 V continuously.
Use as a Kelvin connection to auxiliary compensation inductance. If SR
MOSFET package parasitic inductance compensation is not used (like for
SMT MOSFETs), connect this pin directly to GND pin.
Ground connection for the SR MOSFET driver and VCC decoupling capacitor.
Ground connection for minimum ton, toff adjust resistors and trigger input.
GND pin should be wired directly to the SR MOSFET source
terminal/soldering point using Kelvin connection.
Driver output for the SR MOSFET.
VDD
toff_min Generator Start
Enable SET
MINIMUM OFF
TIME
GENERATOR
MIN_TOFF
VDD
100 mA
&
ZCD SET
DETECTION CS
&
COMPENSATION
CS
Blanking of CS
during
toff_min, ton_min
ZCD Reset
&
&
S
Q
R
Q
DRV Out
DRIVER
DRV
OR
COMP
1k5
MINIMUM ON
TIME
GENERATOR
MIN_TON
DRV Set Enable
DRV Reset
Enable RESET
VDD
VCC
MANAGEMENT
UVLO
VCC
ton_min Generator Start
TIMER
VDD
Sleep Mode
100 ms
INV
One shot
ZCD Reset
TRIG/DIS
GND
S
Q
R
Q
&
10 mA
OR
INV
VTH = 2 V
Trigger Blanking
120 ns
during DRV rising edge
INV
One shot
120 ns
Figure 3. Internal Circuit Architecture
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3
NCP4304A, NCP4304B
MAXIMUM RATINGS
Symbol
Rating
Value
Unit
VCC
IC Supply Voltage
−0.3 to 30
V
VDRV
Driver Output Voltage
−0.3 to 17
V
VCS
Current Sense Input dc Voltage
−4 to 200
V
Current Sense Input Dynamic Voltage (tpw = 200 ns)
−10 to 200
V
Trigger Input Voltage
−0.3 to 10
V
VCsdyn
VTRIG/DIS
VMIN_TON, VMIN_TOFF MIN_TON and MIN_TOFF Input Voltage
IMIN_TON, IMIN_TOFF
VCOMP
VCOMP_dyn
−0.3 to 10
V
−10 to +10
mA
Static Voltage Difference between COMP and GND Pins (Internally Clamped)
−3 to 10
V
Dynamic Voltage Difference between COMP and GND Pins (tpw = 200 ns)
−10 to 10
V
MIN_TON and MIN_TOFF Current
ICOMP
Current into COMP Pin
−5 to 5
mA
RqJA
Thermal Resistance Junction-to-Air, SOIC − A/B Versions
180
°C/W
RqJA
Thermal Resistance Junction-to-Air, DFN − A/B Versions, 50 mm2 − 1.0 oz. Copper
Spreader
180
°C/W
RqJA
Thermal Resistance Junction-to-Air, DFN − A/B Versions, 600 mm2 − 1.0 oz. Copper
Spreader
80
°C/W
150
°C
−60 to +150
°C
TJmax
Maximum Junction Temperature
TSmax
Storage Temperature Range
TLmax
Lead Temperature (Soldering, 10 s)
ESD Capability, Human Body Model except Pin VCS – Pin 5, HBM ESD Capability on
Pin 5 is 650 V per JEDEC Standard JESD22−A114E
ESD Capability, Machine Model per JEDEC Standard JESD22−A115−A
300
°C
2
kV
200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device meets latchup tests defined by JEDEC Standard JESD78.
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 12 V, CDRV = 0 nF, RMIN_TON = RMIN_TOFF = 10 kW,
VTRIG/DIS = 0 V, fCS = 100 kHz, DCCS = 50%, VCS_high = 4 V, VCS_low = −1 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
SUPPLY SECTION
VCC_on
Turn-on threshold level (VCC going up)
1
9.3
9.9
10.5
V
VCC_off
Minimum operating voltage after turn-on (VCC going down)
1
8.3
8.9
9.5
V
VCC hysteresis
1
0.6
1.0
1.4
V
ICC1_A
ICC1_B
Internal IC consumption (no output load on pin 8, fSW = 500 kHz,
ton_min = 500 ns, toff_min = 620 ns)
1
−
−
4.5
4.0
6.6
6.2
mA
ICC2_A
ICC2_B
Internal IC consumption (CDRV = 1 nF on pin 8, fSW = 400 kHz,
ton_min = 500 ns, toff_min = 620 ns)
1
−
−
9.0
6.5
12
9
mA
ICC3_A
ICC3_B
Internal IC consumption (CDRV = 10 nF on pin 8, fSW = 400 kHz,
ton_min = 500 ns, toff_min = 620 ns)
1
−
−
57.0
35.0
80
65
mA
ICC_StartUp
Startup current consumption (VCC = VCC_on − 0.1 V, no switching at
CS pin)
1
−
35
75
mA
ICC_Disable_1
Current consumption during disable mode (No switching at CS pin,
VTRIG/DIS = 5 V)
1
−
45
90
mA
ICC_Disable_2
Current consumption during disable mode (CS pin is switching,
fSW = 500 kHz, VCS_high = 4 V, VCS_low =−1 V, VTRIG/DIS = 5 V)
1
−
200
330
mA
tr_A
Output voltage rise-time for A version (CDRV = 10 nF)
8
−
120
−
ns
tr_B
Output voltage rise-time for B version (CDRV = 10 nF)
8
−
80
−
ns
tf_A
Output voltage fall-time for A version (CDRV = 10 nF)
8
−
50
−
ns
tf_B
Output voltage fall-time for B version (CDRV = 10 nF)
8
−
35
−
ns
Roh
Driver source resistance (Note 1)
8
−
1.8
7
W
Rol
Driver sink resistance
8
−
1
2
W
VCC_hyste
DRIVE OUTPUT
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4
NCP4304A, NCP4304B
ELECTRICAL CHARACTERISTICS (continued)
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 12 V, CDRV = 0 nF, RMIN_TON = RMIN_TOFF = 10 kW,
VTRIG/DIS = 0 V, fCS = 100 kHz, DCCS = 50%, VCS_high = 4 V, VCS_low = −1 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
Output source peak current
8
−
2.5
−
A
IDRV_pk(sink)
Output sink peak current
8
−
5
−
A
VDRV(min_A)
Minimum drive output voltage for A version (VCC = VCC_off + 200 mV)
8
8.3
−
−
V
VDRV(min_B)
Minimum drive output voltage for B version (VCC = VCC_off + 200 mV)
8
4.5
−
−
V
VDRV(CLMP_A)
Driver clamp voltage for A version (12 < VCC < 28, CDRV = 1 nF)
8
10
12
14.3
V
VDRV(CLMP_B)
Driver clamp voltage for B version (12 < VCC < 28, CDRV = 1 nF)
8
5
6
8
V
DRIVE OUTPUT
IDRV_pk(source)
CS INPUT
tpd_on
The total propagation delay from CS input to DRV output turn on
(VCS goes down from 4 V to −1 V, tf_CS = 5 ns, COMP pin connected
to GND)
5, 8
−
60
90
ns
tpd_off
The total propagation delay from CS input to DRV output turn off
(VCS goes up from −1 V to 4 V, tr_CS = 5 ns, COMP pin connected to
GND), (Note 1)
5, 8
−
40
55
ns
5
95
100
105
mA
Ishift_CS
Current sense input current source (VCS = 0 V)
Vth_cs_on
Current sense pin turn-on input threshold voltage
5, 8
−120
−85
−50
mV
Vth_cs_off
Current sense pin turn-off threshold voltage, COMP pin connected to
GND (Note 1)
5, 8
−1
−
0
mV
Compensation inverter gain
5,6,8
1
mA
ns
Gcomp
ICS_Leakage
Current Sense input leakage current, VCS = 200 V
5
−1
−
−
−
TRIGGER/DISABLE INPUT
tTRIG/DIS_pw_min
Minimum trigger pulse width (Note 1)
4
30
−
−
VTRIG/DIS
Trigger input threshold voltage (VTRIG/DIS goes up)
4
1.5
−
2.5
V
tp_TRIG/DIS
Propagation delay from trigger input to the DRV output
(VTRIG/DIS goes up from 0 to 5 V, tr_TRIG/DIS = 5 ns)
4
−
13
30
ns
Light load turn off filter duration
4
70
100
130
ms
IC operation recovery time when leaving light load disable mode
(VTRIG/DIS goes down from 5 to 0 V, tf_TRIG/DIS = 5 ns)
4
−
−
10
ms
Blanking time of trigger during DRV rising edge (VCS < Vth_cs_on,
single pulse on trigger tTRIG/DIS_pw = 50 ns)
4
−
120
−
ns
Trigger input pull down current (VTRIG/DIS = 5 V)
4
−
10
−
mA
tTRIG/DIS_light_load
tTRIG/DIS_light_
load_rec.
tTRIG/DIS_blank
ITRIG/DIS
ton_min AND toff_min ADJUST
ton_min
Minimum ton period (RMIN_TON = 0 W)
3
−
130
−
ns
toff_min
Minimum toff period (RMIN_TOFF = 0 W)
2
560
600
690
ns
ton_min
Minimum ton period (RMIN_TON = 10 kW)
3
0.9
1.0
1.1
ms
toff_min
Minimum toff period (RMIN_TOFF = 10 kW)
2
0.9
1.0
1.1
ms
ton_min
Minimum ton period (RMIN_TON = 50 kW)
3
−
4.8
−
ms
toff_min
Minimum toff period (RMIN_TOFF = 50 kW)
2
−
4.8
−
ms
ton_min
Minimum ton period (RMIN_TON = 100 kW) (Note 2)
3
8.64
9.6
10.56
ms
toff_min
Minimum toff period (RMIN_TOFF = 100 kW) (Note 2)
2
8.55
9.5
10.45
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Guaranteed by design.
2. Guaranteed by design and verified by characterization, see Figure 4. ton_min on RMIN_TON dependency.
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5
NCP4304A, NCP4304B
TYPICAL CHARACTERISTICS
10000
ton_min (ns)
8000
6000
4000
2000
0
0
10000
20000
30000
40000
50000
60000
70000
RMIN_TON (W)
Figure 4. ton_min on RMIN_TON Dependency
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6
80000
90000
100000
NCP4304A, NCP4304B
9.890
8.880
8.870
9.880
8.860
8.850
VCC_off (V)
VCC_on (V)
9.870
9.860
8.840
8.830
9.850
8.820
9.840
8.810
9.830
8.800
9.820
−40 −25 −10 5
20
35
50
65
80
95
8.790
−40 −25 −10 5
110 125
35
50
65
80
95
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. VCC Startup Voltage
Figure 6. VCC Turn-off Voltage
1.040
44
1.035
42
1.030
110 125
40
ICC_Startup (mA)
VCC_hyste (V)
20
1.025
1.020
1.015
38
36
1.010
34
1.005
32
1.000
−40 −25 −10 5
20
35
50
65
80
95
30
−40 −25 −10
110 125
5
20
35
50
65
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. VCC Hysteresis
Figure 8. Startup Current
12.0
95
110 125
95
110 125
12.065
11.9
12.060
12.055
11.7
VDRV(H)_A (V)
VDRV(H)_A (V)
11.8
12.050
11.6
11.5
12.045
11.4
12.040
11.3
12.035
11.2
12.030
11.1
11.0
−40 −25 −10 5
20
35
50
65
80
95
110 125
12.025
−40 −25 −10 5
20
35
50
65
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Driver High Level – A Version,
VCC = 12 V and CDRV = 1 nF
Figure 10. Driver High Level – A Version,
VCC = 12 V and CDRV = 10 nF
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NCP4304A, NCP4304B
7.0
7.70
6.9
7.65
6.8
7.60
VDRV(H)_B (V)
VDRV(H)_B (V)
6.7
6.6
6.5
6.4
6.3
7.55
7.50
7.45
7.40
6.2
7.35
6.1
7.30
6.0
7.25
5.9
−40 −25 −10 5
20
35
50
65
80
95
7.20
−40 −25 −10 5
110 125
TEMPERATURE (°C)
Figure 11. Driver High Level – B Version,
VCC = 12 V and CDRV = 1 nF
35
50
65
80
95
110 125
Figure 12. Driver High Level – B Version,
VCC = 12 V and CDRV = 10 nF
9.10
6.40
9.05
6.30
VDRV(min_B) (V)
9.00
VDRV(min_A) (V)
20
TEMPERATURE (°C)
8.95
8.90
8.85
6.20
6.10
6.00
5.90
8.80
8.75
−40 −25 −10 5
20
35
50
65
80
95
110 125
5.80
−40 −25 −10 5
TEMPERATURE (°C)
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
Figure 13. Minimal Driver High Level − A Version,
VCC_off + 0.2 V and CDRV = 0 nF
Figure 14. Minimal Driver High Level − B Version,
VCC_off + 0.2 V and CDRV = 0 nF
14.0
15.0
13.8
14.5
13.4
VDRV(CLMP_A) (V)
VDRV(CLMP_A) (V)
13.6
13.2
13.0
12.8
12.6
12.4
14.0
13.5
13.0
12.2
12.0
−40 −25 −10 5
20
35
50
65
80
95
110 125
12.5
−40 −25 −10 5
TEMPERATURE (°C)
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
Figure 15. Driver Clamp Level − A Version,
VCC = 28 V and CDRV = 1 nF
Figure 16. Driver Clamp Level − A Version,
VCC = 28 V and CDRV = 10 nF
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NCP4304A, NCP4304B
7.1
8.4
7.0
8.2
6.8
VDRV(CLMP_B) (V)
VDRV(CLMP_B) (V)
6.9
6.7
6.6
6.5
6.4
8.0
7.8
7.6
7.4
6.3
7.2
6.2
6.1
−40 −25 −10 5
20
35
50
65
80
95
7.0
−40 −25 −10 5
110 125
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Driver Clamp Level − B Version,
VCC = 28 V and CDRV = 1 nF
Figure 18. Driver Clamp Level − B Version,
VCC = 28 V and CDRV = 10 nF
60.0
45.0
40.0
50.0
35.0
30.0
tpd_off (ns)
tpd_on (ns)
40.0
30.0
25.0
20.0
15.0
20.0
10.0
10.0
5.0
0.0
−40 −25 −10 5
20
35
50
65
80
95
0.0
−40 −25 −10 5
110 125
35
50
65
80
95
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. CS to DRV Turn-on Propagation
Delay
Figure 20. CS to DRV Turn-off Propagation
Delay
101.0
−40.0
100.5
−50.0
−60.0
Vth_cs_on (mV)
100.0
Ishift_CS (mA)
20
99.5
99.0
98.5
−70.0
−80.0
−90.0
−100.0
98.0
−40 −25 −10
5
20
35
50
65
80
95
−110.0
−40 −25 −10
110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. CS Pin Shift Current
Figure 22. CS Turn-on Threshold
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2.12
16.0
2.10
14.0
2.08
12.0
tp_TRIG/DIS (ns)
VTRIG/DIS (V)
NCP4304A, NCP4304B
2.06
2.04
2.02
10.0
8.0
6.0
2.00
4.0
1.98
2.0
1.96
−40 −25 −10 5
20
35
50
65
80
95
110 125
0.0
−40 −25 −10 5
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 23. Trigger Input Threshold Voltage
Figure 24. Propagation Delay from Trigger
Input to DRV Turn-off
9.210
101.5
9.205
tTRIG/DIS_light_load_rec (ms)
tTRIG/DIS_light_load (ms)
101.0
100.5
100.0
99.5
9.200
9.195
9.190
9.185
9.180
5
20
35
50
65
80
95
110 125
9.175
−40 −25 −10 5
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 25. Light Load Transition Timer
Duration
Figure 26. Light Load to Normal Operation
Recovery Time
18.0
165.0
16.0
164.0
14.0
163.0
12.0
162.0
ton_min (ns)
ITRIG/DIS (mA)
99.0
−40 −25 −10
10.0
8.0
6.0
161.0
160.0
159.0
4.0
158.0
2.0
157.0
0.0
−40 −25 −10 5
20
35
50
65
80
95
110 125
156.0
−40 −25 −10 5
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 27. Trigger Input Pulldown Current
Figure 28. Minimum on Time @ RMIN_TON = 0 W
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10
NCP4304A, NCP4304B
999.0
994.5
998.5
994.0
998.0
993.5
toff_min (ns)
ton_min (ns)
997.5
997.0
996.5
996.0
995.5
993.0
992.5
992.0
995.0
991.5
994.5
994.0
−40 −25 −10 5
20
35
50
65
80
95
991.0
−40 −25 −10 5
110 125
TEMPERATURE (°C)
Figure 29. Minimum On Time @ RMIN_TON = 10 kW
4940
4860
4920
4840
4900
4800
4780
4760
4740
65
80
95
110 125
4860
4840
4820
4720
4800
4700
4780
5
20
35
50
65
80
95
4760
−40 −25 −10 5
110 125
TEMPERATURE (°C)
620.0
4.95
615.0
4.90
610.0
4.85
ICC1_A (mA)
5.00
605.0
600.0
590.0
4.65
50
65
65
80
95
110 125
4.75
4.70
35
50
4.80
595.0
20
35
Figure 32. Minimum On Time @ RMIN_TON = 50 kW
625.0
5
20
TEMPERATURE (°C)
Figure 31. Minimum Off Time @ RMIN_TOFF = 50 kW
toff_min (ns)
50
4880
ton_min (ns)
toff_min (ns)
4820
585.0
−40 −25 −10
35
Figure 30. Minimum Off Time @ RMIN_TOFF = 10 kW
4880
4680
−40 −25 −10
20
TEMPERATURE (°C)
80
95
110 125
4.60
−40 −25 −10 5
TEMPERATURE (°C)
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
Figure 33. Minimum Off Time @ RMIN_TOFF = 0 W
Figure 34. Internal IC Consumption
(A Version, No Load on Pin 8, fSW = 500 kHz,
ton_min = 500 ns, toff_min = 620 ns)
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11
NCP4304A, NCP4304B
4.200
9.35
4.180
9.30
4.140
ICC2_A (mA)
ICC1_B (mA)
4.160
4.120
4.100
4.080
9.25
9.20
9.15
4.060
9.10
4.040
4.020
−40 −25 −10
5
20 35 50 65 80
TEMPERATURE (°C)
95
9.05
−40 −25 −10 5
110 125
Figure 35. Internal IC Consumption (B version,
CDRV = 0 nF, fSW = 500 kHz,
ton_min = 500 ns, toff_min = 620 ns)
20 35 50 65 80
TEMPERATURE (°C)
95
110 125
Figure 36. Internal IC Consumption (A Version,
CDRV = 1 nF, fSW = 400 kHz,
ton_min = 500 ns, toff_min = 620 ns)
7.60
52.8
52.7
7.40
52.6
ICC3_A (mA)
7.00
6.80
6.60
52.5
52.4
52.3
52.2
52.1
6.40
52.0
6.20
−40 −25 −10
5
20 35 50 65 80
TEMPERATURE (°C)
95
110 125
51.9
−40 −25 −10 5
Figure 37. Internal IC Consumption
(B Version, CDRV = 1 nF, fSW = 400 kHz,
ton_min = 500 ns, toff_min = 620 ns)
20 35 50 65 80
TEMPERATURE (°C)
34.5
34.0
33.5
33.0
32.5
−40 −25 −10 5
95
110 125
Figure 38. Internal IC Consumption (A Version,
CDRV = 10 nF, fSW = 400 kHz,
ton_min = 500 ns, toff_min = 620 ns)
35.0
ICC3_B (mA)
ICC2_B (mA)
7.20
20
35
50
65
80
95
TEMPERATURE (°C)
Figure 39. Internal IC Consumption
(B Version, CDRV = 10 nF, fSW = 400 kHz,
ton_min = 500 ns, toff_min = 620 ns)
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12
110 125
NCP4304A, NCP4304B
APPLICATION INFORMATION
General Description
To overcome issues after turn on and off events, the
NCP4304A/B provides adjustable minimum on time and off
time blanking periods. Blanking times can be adjusted
independently of IC VCC using resistors connected to GND.
If needed, blanking periods can be modulated using
additional components.
An ultrafast trigger input helps to implement synchronous
rectification systems in CCM applications (like CCM
flyback or forward). The time delay from trigger input to
driver turn off event is 10 ns (typicaly). Additionally, the
trigger input can be used to disable the IC and activate a low
consumption standby mode. This feature can be used to
decrease standby consumption of an SMPS.
Finally, the NCP4304A/B features a special input that can
be used to automatically compensate for SR MOSFET
parasitic inductance effect. This technique achieves the
maximum available on-time and thus optimizes efficiency
when a MOSFET in standard package (like TO−220 or
TO247) is used. If a SR MOSFET in SMT package with
negligible inductance is used, the compensation input is
connected to GND pin.
The NCP4304A/B is designed to operate either as
a standalone IC or as a companion IC to a primary side
controller to help achieve efficient synchronous
rectification in switch mode power supplies. This controller
features a high current gate driver along with high-speed
logic circuitry to provide appropriately timed drive signals
to a synchronous rectification MOSFET. With its novel
architecture, the NCP4304A/B has enough versatility to
keep the synchronous rectification efficient under any
operating mode.
The NCP4304A/B works from an available bias supply
with voltage range from 10.4 V to 28 V (typical). The wide
VCC range allows direct connection to the SMPS output
voltage of most adapters such as notebook and LCD TV
adapters. As a result, the NCP4304A/B simplifies circuit
operation compared to other devices that require specific
bias power supplies (e.g. 5 V). The high voltage capability
of the VCC is also a unique feature designed to allow
operation for a broader range of applications.
Precise turn off threshold of the current sense comparator
together with accurate offset current source allows the user
to adjust for any required turn off current threshold of the SR
MOSFET switch using a single resistor. Compared to other
SR controllers that provide turn off thresholds in the range
of −10 mV to −5 mV, the NCP4304A/B offers a turn off
threshold of 0 mV that in combination with a low RDS(on) SR
MOSFET significantly reduces the turn off current
threshold and improves efficiency.
Zero Current Detection and Parasitic Inductance
Compensation
Figure 40 shows the internal connection of the ZCD
circuitry on the current sense input. The synchronous
rectification MOSFET is depicted with it’s parasitic
inductances to demonstrate operation of the compensation
system.
+Vout
SR MOSFET
LDRAIN
LSOURCE
+
LCOMP
GND
M1
DRV
Vdd
RSHIFT_CS
Ishift_CS
Ishift_CS
100 mA
+
VREF = Vth_cs_on
−
+
−
CS
ZCD SET
To Internal Logic
+
−
+
Vth_cs_off
ZCD RESET
−
−1
COMP
Figure 40. ZCD Sensing Circuitry Functionality
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13
GND
NCP4304A, NCP4304B
The SR MOSFET is turned-off as soon as the voltage on
the CS pin is higher than Vth_cs_off. For the same ringing
reason, a minimum off time timer is asserted once the
turn‐off is detected. The minimum off time can be externally
adjusted using RMIN_TOFF resistor. MOSFET M1 conducts
when the secondary current decreases, therefore the turn-off
time depends on its RDS(on). The 0 mV threshold provides
an optimum switching period usage while keeping enough
time margin for the gate turn off. The RSHIFT_CS resistor
provides the designer with the possibility to modify
(increase) the actual turn-off current threshold.
When the voltage on the secondary winding of the SMPS
reverses, the body diode of M1 starts to conduct current and
the voltage of M1’s drain drops approximately to −1 V. The
CS pin sources current of 100 mA that creates a voltage drop
on the RSHIFT_CS resistor. Once the voltage on the CS pin
is lower than Vth_cs_on threshold, M1 is turned on. Because
of parasitic impedances, significant ringing can occur in the
application. To overcome sudden turn-off due to mentioned
ringing, the minimum conduction time of the SR MOSFET
is activated. Minimum conduction time can be adjusted
using RMIN_TON resistor.
VDS
ISEC
Vth_cs_off − (RSHIFT_CS ⋅ Ishift_CS)
Vth_cs_on − (RSHIFT_CS ⋅ Ishift_CS)
VDRV
Blank
ton_min
toff_min
The ton_min and toff_min are adjustable by RMIN_TON and RMIN_TOFF resistors.
Figure 41. ZCD Comparators Thresholds and Blanking Periods Timing
If using a SR MOSFET in TO−220 package (or other
package which features leads), the parasitic inductance of
the package leads causes a turn-off current threshold
increase. This is because current that flows through the SR
MOSFET has quite high di(t)/dt that induces error voltage
on the SR MOSFET leads inductance. This error voltage,
that is proportional to the secondary current derivative,
shifts the CS input voltage to zero when significant current
still flows through the channel. Zero current threshold is thus
detected when current still flows through the SR MOSFET
channel – please refer to Figure 42 for better understanding.
As a result, the SR MOSFET is turned-off prematurely and
the efficiency of the SMPS is not optimized.
If no RSHIFT_CS resistor is used, the turn-on and turn-off
thresholds are fully given by the CS input specification
(please refer to parametric table). Once non-zero
RSHIFT_CS resistor is used, both thresholds move down
(i.e. higher MOSFET turn off current) as the CS pin offset
current causes a voltage drop that is equal to:
V RSHIFT_CS + RSHIFT_CS @ I shift_CS
(eq. 1)
Final turn-on and turn-off thresholds can be then calculated
as:
V CS_turn_on + V th_cs_on * ǒRSHIFT_CS @ I shift_CSǓ
(eq. 2)
V CS_turn_off + V th_cs_off * ǒRSHIFT_CS @ I shift_CSǓ
(eq. 3)
Note that RSHIFT_CS impact on turn-on threshold is less
critical compare to turn-off threshold.
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NCP4304A, NCP4304B
Figure 42. Waveforms from SR System Using MOSFET in TO−220 Package Without Parasitic Inductance
Compensation – SR MOSFET Channel Conduction Time is Reduced
Note that the efficiency impact of the error caused by
parasitic inductance increases with lower RDS(on)
MOSFETs and/or higher operating frequency.
The NCP4304A/B offers a way to compensate for
MOSFET parasitic inductances effect − refer to Figure 43.
VDS
ISEC
VLDRAIN
VRDS(on)
VLSOURCE
D
VLCOMP
S
LDRAIN
RDS(on)
LSOURCE
CS
LCOMP
GND
COMP
Figure 43. Package Parasitic Inductances Compensation Principle
current sense comparator thus “sees” between its terminals
a voltage that would be seen on the SR MOSFET channel
resistance in case the lead inductances wouldn’t exist. The
current sense comparator of the NCP4304A/B is thus able to
detect the secondary current zero crossing very precisely.
More over, the secondary current turn-off threshold is then
di(t)/t independent thus the NCP4304A/B allows to increase
operating frequency of the SR system. One should note that
the parasitic resistance of compensation inductance should
Dedicated input (COMP) offers the possibility to use an
external compensation inductance (wire strap or PCB). If
the value of this compensation inductance is LCOMP =
LDRAIN + LSOURCE, the compensation voltage created
on this inductance is exactly the same as the sum of error
voltages created on drain and source parasitic inductances
i.e. VLDRAIN + VLSOURCE. The internal analog inverter
(Figure 40) inverts compensation voltage VLCOMP and
offsets the current sense comparator turn-off threshold. The
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15
NCP4304A, NCP4304B
be as low as possible compared to the SR MOSFET channel
and leads resistance otherwise compensation is not efficient.
Typical value of compensation inductance for a TO−220
package is 7 nH. Waveforms from the application with
compensated SR system can be seen in Figure 44. One can
see the conduction time has been significantly increased and
turn-off current reduced.
Figure 44. Waveforms SR System Using MOSFET in TO−220 Package with Parasitic Inductance Compensation –
SR MOSFET Channel Conduction Time is Optimized
comparator. Ideally the CS turn-off comparator should
detect voltage that is caused by secondary current directly on
the SR MOSFET channel resistance. Practically this is not
possible because of the bonding wires, leads and soldering.
To assure the best efficiency results, a Kelvin connection of
the SR controller to the power circuitry should be
implemented (i.e. GND pin should be connected to the SR
MOSFET source soldering point and current sense pin
should be connected to the SR MOSFET drain soldering
point). Any impact of PCB parasitic elements on the SR
controller functionality is then avoided. Figures 45 and 46
show examples of SR system layouts using parasitic
inductance compensation (i.e. for low RDS(on) MOSFET in
TO−220 package ) and not using compensation (i.e. for
higher RDS(on) MOSFET in TO−220 package or SMT
package MOSFETs).
Note that using the compensation system is only
beneficial in applications that are using a low RDS(on)
MOSFET in non-SMT package. Using the compensation
method allows for optimized efficiency with a standard
TO−220 package that in turn results in reduced costs, as the
SMT MOSFETs usually require reflow soldering process
and more expensive PCB.
From the above paragraphs and parameter tables it is
evident that turn-off threshold precision is quite critical. If
we consider a SR MOSFET with RDS(on) of 1 mW, the 1 mV
error voltage on the CS pin results in a 1 A turn-off current
threshold difference. Thus the PCB layout is very critical
when implementing the SR system. Note that the CS turn-off
comparator as well as compensation inputs are referred to
the GND pin. Any parasitic impedance (resistive or
inductive − talking about mW and nH values) can cause a
high error voltage that is then evaluated by the CS
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16
NCP4304A, NCP4304B
NCP4304
Figure 45. Recommended Layout When Parasitic
Inductance Compensation is Used
Figure 46. Recommended Layout When Parasitic
Inductance Compensation is Not Used
Trigger/Disable Input
(above 2.5 V) the driver is disabled immediately, except
during DRV rising edge when TRIG/DIS is blanked for
120 ns. If the trigger signal is high for more than 100 ms the
driver enters standby mode. The IC consumption is reduced
below 100 mA during the standby mode. The device
recovers operation in 10 ms when the trigger voltage is
increased to exit standby mode. TRIG/DIS input is superior
to CS input except blanking period. TRIG/DIS signal
turns-OFF the SR MOSFET or disable its turn-ON if
TRIG/DIS is pulled above VTRIG/DIS.
The NCP4304A/B features an ultrafast trigger input that
exhibits a typically of 10 ns delay from its activation to the
turn-off of the SR MOSFET. The main purpose of this input
is to turn-off the SR MOSFET in applications operating in
CCM mode via a signal coming from the primary side or
direct synchronization SR MOSFET turn-on and turn-off
event according to primary controller signals. The
NCP4304A/B operation can be disabled using the
TRIG/DIS input. If the TRIG/DIS input is pulled high
R
100 ms
Timer
VTRIG/DIS = 2 V
SLEEP MODE
Inv
One Shot
TRIG/DIS
4
ZCD RESET
10 mA
Trigger Information
from the Primary
ZD 10 V
S
Q
R
Q
AND
Inv
Trigger Blanking
120 ns
During DRV Rising Edge
One Shot
GND
Figure 47. Trigger Input Internal Circuitry
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17
120 ns
OR
DRV RESET
Inv DRV SET ENABLE
toff_min Generator Start
NCP4304A, NCP4304B
pulled LOW and CS (VDS) is still under Vth_cs_on threshold
then the DRV is turned-ON (t7 marker).
Time markers t14 and t15 in Figure 48 demonstrate
situation when CS (VDS) is above Vth_cs_on threshold and
TRIG/DIS is pulled down. In this case the driver stays LOW
(t12 to t15 marker).
Figure 48 depicts driver turn-ON events. Turn-ON of the
SR MOSFET is possible if CS (VDS) signal falls under
Vth_cs_on threshold and TRIG/DIS is pulled LOW (t1 to t3
time interval).
When the CS (VDS) reached the Vth_cs_on threshold and
TRIG/DIS is pulled HIGH the driver stays LOW (t6, t7 time
markers) if the TRIG/DIS is HIGH. If the TRIG/DIS is
VDS
Vth_cs_off
Vth_cs_on
TRIG/DIS
DRV
t0
t1 t2 t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13 t14 t15
Figure 48. DRV Turn ON Events
The TRIG/DIS input is blanked for 120 ns after DRV set
signal to avoid undesirable behavior during SR MOSFET
turn-ON event. The blanking time in combination with high
threshold voltage (2 V) prevent triggering on ringing and
spikes that are present on the TRIG/DIS input pin during the
SR MOSFET turn-on process. DRV response to the short
needle pulse on the TRIG/DIS pin is depicted in Figure 49
– this short pulse turns-on the DRV for 120 ns.
VDS
Vth_cs_off
Vth_cs_on
TRIG/DIS
Disable of Trigger
Min_ON_Time
DRV
t0
t1
120 ns
t2
t3
Figure 49. Trigger Needle Pulse and Trigger Blank Sequence
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18
NCP4304A, NCP4304B
Advantage of the trigger blanking time during DRV
turn-ON event is evident from Figure 50. Rising edge of the
DRV signal may cause additional spikes on the TRIG/DIS
input. These spikes, in combination with ultra-fast
performance of the trigger logic, could turn-OFF the SR
MOSFET in inappropriate time. Implementation of the
trigger blanking time period helps to avoid such situation.
VDS
Vth_cs_off
Vth_cs_on
TRIG/DIS
Disable of Trigger
Min_ON_Time
DRV
t0
t1
120 ns t4
t2
t5 t6
t3
Figure 50. Trigger Blanking Masked-out Noise in Trigger Signal During Switch-ON Event
Figure 51 depicts driver turn-OFF events in details. If the
CS (VDS) stays below Vth_cs_off threshold driver is
turned-OFF according to rising edge of the TRIG/DIS
signal. TRIG/DIS can turn-OFF the driver also during
minimum-ON time period (time marker t2 and t3 in
Figure 51).
Figure 52 depicts another driver turn-OFF events in
details. Driver is turned-OFF according to the CS (VDS)
signal (t2 marker) and only after minimum-ON time
elapsed. TRIG/DIS signal needs to be LOW during this
event. If the CS (VDS) voltage reaches Vth_cs_off threshold
before minimum-ON time period ends and TRIG/DIS pin is
LOW the DRV is turned-OFF on the falling edge of the
minimum-ON time period (t4 and t6 time markers in
Figure 52).
Figure 53 depicts performance of the NCP4304A/B
controller when trigger pin is permanently pulled LOW. In
this case the DRV is turned ON and OFF according to the CS
(VDS) signal. The driver can be turned off only after
minimum-ON time period elapsed. The driver is turned-ON
in the time when CS (VDS) reaches Vth_cs_on threshold
(t1−t2, t5–t6, t9–t10 markers). DRV is turned-OFF if CS
(VDS) signal reaches Vth_cs_off threshold (t4 marker). The
DRV ON-time is prolonged till minimum-ON time period
falling edge if the CS (VDS) reaches Vth_cs_off before
minimum-ON time period elapsed (t7−t8, t11−t12 markers).
Figure 54 depicts entering into the sleep mode. If the
TRIG/DIS is pulled up for more than 100 ms the
NCP4304A/B enters low consumption mode. The DRV
stays LOW (disabled) during entering sleep mode.
Figure 55 shows sleep mode transition 2nd case – i.e.
TRIG/DIS rising edge comes during the trigger blank
period.
Figure 56 depicts entering into sleep mode and wake-up
sequence.
Figures 57 and 58 show wake-up situations in details. If
the NCP4304A/B is in sleep mode and TRIG/DIS is pulled
LOW NCP4304A/B requires up to 10 ms period to recover
all internal circuitry to normal operation mode. The driver
is then enabled in the next cycle of CS (VDS) signal only.
The DRV stays LOW during waking-up time period.
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19
NCP4304A, NCP4304B
VDS
Vth_cs_off
Vth_cs_on
TRIG/DIS
Min_ON_Time
DRV
t0
t1
t2
t3
Figure 51. Driver Turn-OFF Events Based on the TRIG/DIS Input
VDS
Vth_cs_off
Vth_cs_on
TRIG/DIS
Min_ON_Time
DRV
t0
t1 t2
t3 t4
Figure 52. Driver OFF Sequence Chart 2
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20
t5
t6
NCP4304A, NCP4304B
VDS
Vth_cs_off
Vth_cs_on
TRIG/DIS
Min_ON_Time
DRV
t0
t1 t2 t3
t4
t5 t6
t7 t8
t9
t11
t10
t12
Figure 53. TRIG/DIS is LOW Sequence Chart
VDS
Vth_cs_off
Vth_cs_on
TRIG/DIS
Min_ON_Time
Power Consumption
100 ms
DRV
t0
t1 t2
t3
Figure 54. TRIG/DIS from LOW to HIGH Sequence 1
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21
NCP4304A, NCP4304B
VDS
Vth_cs_off
Vth_cs_on
TRIG/DIS
Min_ON_Time
Power Consumption
100 ms
120 ns
DRV
t0
t1 t2
t3
Figure 55. TRIG/DIS from LOW to HIGH Sequence 2
VDS
100 ms
TRIG/DIS
10 ms
Power
Consumption
Sleep Mode
DRV
t0
t1
t2
t3 t4
Figure 56. Sleep Mode Sequence
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22
NCP4304A, NCP4304B
VDS
Vth_cs_off
Vth_cs_on
TRIG/DIS
Sleep Mode
Power
Consumption
10 ms
Wake Up
Driver
LOW
DRV
t0
t1
t2 t3 t4
t5
t6
t7 t8
t9
Figure 57. Waking-up Sequence
VDS
Vth_cs_off
Vth_cs_on
Sleep
Mode
TRIG/DIS
DRV
T1
t0
t4 t5
t2
Waking-up Time
Waked Up
t1
t3
Figure 58. Wake-up Time Sequence
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23
NCP4304A, NCP4304B
sequence elapses in time t4 the DRV is turned ON. In time
t5 Trigger signal rises up and terminates this cycle of the CS
signal in time t5. Next cycle starts in time t6. Trigger enables
DRV and VDS is under Vth_cs_on threshold voltage so DRV
turns ON in time t6. TRIG/DIS signal rises up to HIGH level
in time t7, consequently DRV turns OFF and this starts
minimum OFF time generator. Because minimum OFF time
period is longer then the rest of time to the end of cycle of
VDS − DRV is disabled.
Figure 59 shows IC behavior in case the trigger signal
features two pulses during one cycle of the VDS (CS) signal.
TRIG/DIS enables driver at time t1 and DRV turns ON
because the VDS voltage is under Vth_cs_on threshold
voltage. The trigger signal and consequently DRV output
fall down in time t2. The minimum OFF time generator is
triggered in time t2. TRIG/DIS drops down to LOW level in
time t3 but there is still minimum OFF time sequence present
so the DRV output stays low. When the minimum OFF time
VDS
Vth_cs_off
Vth_cs_on
TRIG/DIS
Min_ON_Time
Min_OFF_Time
DRV
t0
t1
t2
t3
t4
t5
t6
t7 t8 t9 t10
Figure 59. IC Behavior when Multiple Trigger Pulses Appear on TRIG/DIS Input
transformer can be for instance prepared on a small toroidal
ferrite core with diameter of 8 mm. Proper safety insulation
between primary and secondary sides can be easily assured
by using triple insulated wire for one or even both windings.
The primary MOSFET gate voltage rising edge is delayed
by external circuitry consisting of transistors Q1, Q2 and
surrounding components. The primary MOSFET is thus
turned-on with a slight delay so that the secondary controller
turns-off the SR MOSFET by trigger signal prior to the
primary switching. This method reduces the commutation
losses and the SR MOSFET drain voltage spike, which
results in improved efficiency.
It is also possible to use capacitive coupling (use
additional capacitor with safety insulation) between the
primary and secondary to transmit the trigger signal. We do
not recommend this technique as the parasitic capacitive
currents between primary and secondary may affect the
trigger signal and thus overall system functionality.
Note that the TRIG/DIS input is an ultrafast input that is
sensitive even to very narrow voltage pulses. Thus it is wise
to keep this input on a low impedance path and provide it
with a clean triggering signal in the time this input is enabled
by internal logic.
A typical application schematic of a CCM flyback
converter with the NCP4304A/B driver can be seen in
Figure 60. In this application the trigger signal is taken
directly from the flyback controller driver output and
transmitted to the secondary side by pulse transformer TR2.
Because the TRIG/DIS input is edge sensitive, it is not
necessary to transmit the entire primary driver pulse to the
secondary. The coupling capacitor C5 is used to allow pulse
transformer core reset and also to prepare a needle pulse
(a pulse with width lower than 100 ns) to be transmitted to
the NCP4304A/B TRIG/DIS input. The advantage of needle
trigger pulse usage is that the required volt-second product
of the pulse transformer is very low and that allows the
designer to use very small and cheap magnetics. The trigger
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24
NCP4304A, NCP4304B
Vbulk
TR1
+
C2
R5
C3
+Vout
D3
Delay Generator
VCC
FLYBACK
CONTROL
CIRCUITRY DRV
FB
CS
+
M2
+
C4
R2
C7
D4
GND
Q2
D1
Q1
C6
M1
R3
R4
R1
R9
C1
R6
D2
R7
OK1
C5
R10
VCC
DRV
MIN_TOFF GND
MIN_TON COMP
TRIG/DIS
CS
D5
TR2
R11
Figure 60. Typical Application Schematic when NCP4304A/B is Used in CCM Flyback Converter
ton_min and toff_min Adjustment
timers avoid false triggering on the CS input after the
MOSFET is turned on or off. The adjustment is based on an
internal timing capacitance and external resistors connected
to the GND pin – refer to Figure 61 for better understanding.
The NCP4304A/B offers adjustable minimum ON and
OFF time periods that ease the implementation of the
synchronous rectification system in a power supply. These
Vdd
To Internal Logic
VREF
IRMIN_TON
+
−
MIN_TON
+
−
Discharge
Switch
Ct
IRMIN_TON
ton_min
RMIN_TON
GND
Figure 61. Internal Circuitry of ton_min Generator (toff_min Generator Works in the Same Way)
Current through the RMIN_TON adjust resistor can be
calculated as:
I RMIN_TON +
V REF
R MIN_TON
t on_min + C t @
V REF
I RMIN_TON
+ Ct @
V
REF
V
REF
R MIN_TON
(eq. 5)
(eq. 4)
+ C t @ R MIN_TON
As the same current is used for the internal timing
capacitor (Ct) charging, one can calculate the minimum
on-time duration using this equation.
As can be seen from Equation 5, the minimum ON and
OFF times are independent of the VREF or VCC level. The
www.onsemi.com
25
NCP4304A, NCP4304B
minimum ton and toff blanking periods from measured
values in Figures 62 and 63.
6
6
5
5
4
4
toff_min (ms)
ton_min (ms)
internal capacitor size would be too high if we would use
directly IRMIN_TON current thus this current is decreased by
the internal current mirror ratio. One can then estimate
3
2
3
2
1
1
0
0
0
10
20
30
40
50
60
0
10
20
RMIN_TON (kW)
Figure 62. MIN_TON Adjust Characteristic
30
40
RMIN_TOFF (kW)
50
60
Figure 63. MIN_TOFF Adjust Characteristic
to modulate blanking periods by using an external NPN
transistor − refer to Figure 64. The modulation signal can be
derived based on the load current or feedback regulator
voltage.
The absolute minimum ton duration is internally clamped
to 130 ns and minimum toff duration to 600 ns in order to
prevent any potential issues with the minimum ton and/or toff
input being shorted to GND.
Some applications may require adaptive minimum on and
off time blanking periods. With NCP4304A/B it is possible
Vdd
To Internal Logic
VREF
−
MIN_TON
IRMIN_TON
IRMIN_TON
+
Modulation Current
+
ton_min
−
Discharge
Switch
Ct
RMIN_TON
ton_min Modulation
Voltage Input
GND
Figure 64. Possible Connection for ton_min and toff_min Modulation
In LLC applications with a very wide operating frequency
range it is necessary to have very short minimum on time and
off time periods in order to reach the required maximum
operating frequency. However, when a LLC converter
operates under low frequency, the minimum off time period
may then be too short. To overcome possible issues with the
LLC operating under low line and light load conditions, one
can prolong the minimum off time blanking period by using
resistors RDRAIN1 and RDRAIN2 connected from the
opposite SR MOSFET drain – refer to Figure 65.
www.onsemi.com
26
NCP4304A, NCP4304B
RDRAIN1
C2
RMIN_TOFF
RMIN_TON
VCC
DRV
MIN_TOFF GND
MIN_TON COMP
TRIG/DIS
CS
+Vbulk
+Vout
TR1
M1
M3
N2
+
LCOMP1
LLC
STAGE
CONTROL
C4
RTN
N1
M2
LCOMP2
N3
M4
C1
RDRAIN2
RMIN_TOFF
Trig from Primary
(Option for LLC)
C3
VCC
DRV
MIN_TOFF GND
MIN_TON COMP
TRIG/DIS
CS
RMIN_TON
D1
OK1
Note: LCOMP1, 2 are optional for MOSFETs with leads.
Figure 65. Possible Connection for toff_min Prolongation in LLC Application with
Wide Operating Frequency Range
Note that RDRAIN1 and RDRAIN2 should be designed in
such a way that the maximum pulse current into the
MIN_TOFF adjust pin is below 10 mA. Voltage on the
MIN_TOFF and MIN_TON pins is clamped by internal
zener protection to 10 V.
off process always starts before the drain to source voltage
rises up significantly. Therefore, the MOSFET switch
always operates under Zero Voltage Switching (ZVS)
conditions when implemented in a synchronous
rectification system.
The following steps show how to approximately calculate
the power dissipation and DIE temperature of the
NCP4304A/B controller. Note that real results can vary due
to the effects of the PCB layout on the thermal resistance.
Power Dissipation Calculation
It is important to consider the power dissipation in the
MOSFET driver of a SR system. If no external gate resistor
is used and the internal gate resistance of the MOSFET is
very low, nearly all energy losses related to gate charge are
dissipated in the driver. Thus it is necessary to check the SR
driver power losses in the target application to avoid over
temperature and to optimize efficiency.
In SR systems the body diode of the SR MOSFET starts
conducting before turn on because the Vth_cs_on threshold
level is below 0 V. On the other hand, the SR MOSFET turn
Step 1 – MOSFET Gate-to-Source Capacitance:
During ZVS operation the gate to drain capacitance does
not have a Miller effect like in hard switching systems
because the drain to source voltage is close to zero and its
change is negligible.
www.onsemi.com
27
NCP4304A, NCP4304B
C, Capacitance (pF)
8000
7000
VDS = 0 V
6000
VGS = 0 V
D
Ciss
5000
4000
Crss
3000
2000
1000
0
10
Ciss = Cgs + Cgd
Crss = Cgd
Coss = Cds + Cgd
Ciss
Cgd
Cds
G
Cgs
Coss
Crss
0
VGS VDS
10
20
30
S
40
Gate-to-Source or Drain-to-Source Voltage (V)
Figure 66. Typical MOSFET Capacitance Dependency on VDS and VGS Voltage
Therefore, the input capacitance of a MOSFET operating
in ZVS mode is given by the parallel combination of the gate
to source and gate to drain capacitances (i.e. Ciss capacitance
for given gate to source voltage). The total gate charge,
Qg_total, of most MOSFETs on the market is defined for hard
switching conditions. In order to accurately calculate the
driving losses in a SR system, it is necessary to determine the
gate charge of the MOSFET for operation specifically in a
ZVS system. Some manufacturers define this parameter as
Qg_ZVS. Unfortunately, most datasheets do not provide this
data. If the Ciss (or Qg_ZVS) parameter is not available then
it will need to be measured. Please note that the input
capacitance is not linear (as shown Figure 66) and it needs
to be characterized for a given gate voltage clamp level.
The total driving loss can be calculated using the selected
gate driver clamp voltage and the input capacitance of the
MOSFET:
P DRV_total + V CC @ V clamp @ C g_ZVS @ f SW
Where:
VCC
Vclamp
Cg_ZVS
fsw
(eq. 6)
is the supply voltage
is the driver clamp voltage
is the gate to source capacitance of the
MOSFET in ZVS mode
is the switching frequency of the target
application
The total driving power loss won’t only be dissipated in
the IC, but also in external resistances like the external gate
resistor (if used) and the MOSFET internal gate resistance
(Figure 67). Because NCP4304A/B features a clamped
driver, it’s high side portion can be modeled as a regular
driver switch with equivalent resistance and a series voltage
source. The low side driver switch resistance does not drop
immediately at turn-off, thus it is necessary to use an
equivalent value (Rdrv_low_eq) for calculations. This method
simplifies power losses calculations and still provides
acceptable accuracy. Internal driver power dissipation can
then be calculated using Equation 7:
Step 2 – Gate Drive Losses Calculation:
Gate drive losses are affected by the gate driver clamp
voltage. Gate driver clamp voltage selection depends on the
type of MOSFET used (threshold voltage versus channel
resistance). The total power losses (driving loses and
conduction losses) should be considered when selecting the
gate driver clamp voltage. Most of today’s MOSFETs for SR
systems feature low RDS(on) for 5 V VGS voltage and thus it
is beneficial to use the B version. However, there is still a big
group of MOSFETs on the market that require higher gate
to source voltage − in this case the A version should be used.
www.onsemi.com
28
NCP4304A, NCP4304B
VCC
VCC
DRV
Rg_ext
+
VCC − Vclamp
−
Rdrv_high_eq.
SR MOSFET
Rg_int
Rdrv_low_eq.
GND
Cg_ZVS
Figure 67. Equivalent Schematic of Gate Drive Circuitry
P DRV_IC +
ǒ
Ǔ
R drv_low_eq
1
@ C g_ZVS @ V clamp 2 @ f SW @
) C g_ZVS @ V clamp @ f SW @ ǒV CC * V clampǓ
2
R drv_low_eq ) R g_ext ) R g_int
)
ǒ
R drv_high_eq
Ǔ
(eq. 7)
1
@ C g_ZVS @ V clamp 2 @ f SW @
2
R drv_high_eq ) R g_ext ) R g_int
Step 4 – IC Die Temperature Arise Calculation:
Where:
Rdrv_low_eq is the Ddriver low side switch equivalent
resistance (1.55 W)
Rdrv_high_eq is the driver high-side switch equivalent
resistance (7 W)
is the external gate resistor (if used)
Rg_ext
Rg_int
is the internal gate resistance
of the MOSFET
The die temperature can be calculated now that the total
internal power losses have been determined (driver losses
plus internal IC consumption losses). The SO−8 package
thermal resistance is specified in the maximum ratings table
for a 35 mm thin copper layer with no extra copper plates on
any pin (i.e. just 0.5 mm trace to each pin with standard
soldering points are used).
The die temperature is calculated as:
Step 3 – IC Consumption Calculation:
T DIE + ǒP DRV_IC ) P ICCǓ @ R qJA ) T A
In this step, power dissipation related to the internal IC
consumption is calculated. This power loss is given by the
ICC current and the IC supply voltage. The ICC current
depends on switching frequency and also on the selected
ton_min and toff_min periods because there is current flowing
out from the MIN_TON and MIN_TOFF pins. The most
accurate method for calculating these losses is to measure
the ICC current when CDRV = 0 nF and the IC is switching
at the target frequency with given ton_min and toff_min adjust
resistors. Refer also to Figure 68 for typical IC consumption
charts when the driver is not loaded. IC consumption losses
can be calculated as:
P ICC + V CC @ I CC
(eq. 9)
Where:
PDRV_IC is the IC driver internal power dissipation
is the IC control internal power dissipation
PICC
is the thermal resistance from junction to
RqJA
ambient
is the ambient temperature
TA
(eq. 8)
www.onsemi.com
29
NCP4304A, NCP4304B
POWER CONSUMTION (mW)
180
160
A Version,
VCC = 30 V
140
120
B Version,
VCC = 30 V
100
80
A Version,
VCC = 12 V
60
40
B Version,
VCC = 12 V
20
0
50
100
150
200
250
300
350
400
450
500
OPERATING FREQUENCY (kHz)
Figure 68. IC Power Consumption as a Function of Frequency for
CDRV = 0 nF, RMIN_TON = RMIN_TOFF = 5 kW
POWER CONSUMTION (mW)
400
350
300
A Version,
VCC = 30 V
250
B Version,
VCC = 30 V
200
A Version,
VCC = 12 V
150
100
B Version,
VCC = 12 V
50
0
50
100
150
200
250
300
350
400
450
500
OPERATING FREQUENCY (kHz)
Figure 69. IC Power Consumption as a Function of Frequency for
CDRV = 1 nF, RMIN_TON = RMIN_TOFF = 5 kW
POWER CONSUMTION (mW)
800
A Version,
VCC = 30 V
700
B Version,
VCC = 30 V
600
500
400
300
200
B Version,
VCC = 12 V
100
0
50
A Version,
VCC = 12 V
100
150
200
250
300
350
400
450
500
OPERATING FREQUENCY (kHz)
Figure 70. IC Power Consumption as a Function of Frequency for
CDRV = 10 nF, RMIN_TON = RMIN_TOFF = 5 kW
www.onsemi.com
30
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8, 4x4
CASE 488AF−01
ISSUE C
1
SCALE 2:1
A
B
D
PIN ONE
REFERENCE
2X
0.15 C
2X
0.15 C
0.10 C
8X
ÉÉ
ÉÉ
ÉÉ
0.08 C
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
EXPOSED Cu
DETAIL B
ÇÇÇÇ
(A3)
A
A1
C
D2
ÇÇÇÇ
e
8X
SEATING
PLANE
ÉÉÉ
ÉÉÉ
ÇÇÇ
A3
A1
ALTERNATE
CONSTRUCTIONS
8X
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.25
0.35
4.00 BSC
1.91
2.21
4.00 BSC
2.09
2.39
0.80 BSC
0.20
−−−
0.30
0.50
−−−
0.15
XXXXXX
XXXXXX
ALYWG
G
E2
5
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
GENERIC
MARKING DIAGRAM*
L
4
ÇÇÇÇ
8
MOLD CMPD
DETAIL B
SIDE VIEW
K
ÇÇÇ
ÇÇÇ
ÉÉÉ
TOP VIEW
1
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. DETAILS A AND B SHOW OPTIONAL CONSTRUCTIONS FOR TERMINALS.
L
L
L1
NOTE 4
DETAIL A
DATE 15 JAN 2009
b
XXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
SOLDERING FOOTPRINT*
2.21
8X
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.63
4.30 2.39
PACKAGE
OUTLINE
8X
0.35
0.80
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON15232D
DFN8, 4X4, 0.8P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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