NCP5109A, NCP5109B
High Voltage, High and Low
Side Driver
The NCP5109 is a high voltage gate driver IC providing two
outputs for direct drive of 2 N−channel power MOSFETs or IGBTs
arranged in a half−bridge configuration version B or any other
high−side + low−side configuration version A.
It uses the bootstrap technique to ensure a proper drive of the
high−side power switch. The driver works with 2 independent inputs.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Voltage Range: Up to 200 V
dV/dt Immunity ±50 V/nsec
Negative Current Injection Characterized Over the Temperature Range
Gate Drive Supply Range from 10 V to 20 V
High and Low Drive Outputs
Output Source / Sink Current Capability 250 mA / 500 mA
3.3 V and 5 V Input Logic Compatible
Up to VCC Swing on Input Pins
Extended Allowable Negative Bridge Pin Voltage Swing to −10 V
for Signal Propagation
Matched Propagation Delays Between Both Channels
Outputs in Phase with the Inputs
Independent Logic Inputs to Accommodate All Topologies (Version A)
Cross Conduction Protection with 100 ns Internal Fixed Dead Time
(Version B)
Under VCC LockOut (UVLO) for Both Channels
Pin−to−Pin Compatible with Industry Standards
These are Pb−Free Devices
Typical Applications
• Half−Bridge Power Converters
• Any Complementary Drive Converters (Asymmetrical Half−Bridge,
•
8
SOIC−8
D SUFFIX
CASE 751
1
5109x
ALYW
G
1
DFN10
MN SUFFIX
CASE 506DH
5109
x
A
L
Y
W
G
5109x
ALYWG
G
= Specific Device Code
= A or B version
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PINOUT INFORMATION
VCC
IN_HI
IN_LO
GND
1
2
3
4
Active Clamp) (A Version Only).
Full−Bridge Converters
8
7
6
5
VBOOT
DRV_HI
BRIDGE
DRV_LO
SOIC−8
VCC
IN_HI
IN_LO
GND
DRV_LO
1
VBOOT
NC
DRV_HI
NC
BRIDGE
DFN−10
ORDERING INFORMATION
See detailed ordering and shipping information on page 16 of
this data sheet.
© Semiconductor Components Industries, LLC, 2017
February, 2017 − Rev. 2
1
Publication Order Number:
NCP5109/D
NCP5109A, NCP5109B
Vbulk
+
C1
D4
GND
Q1
Vcc
T1
C3
U1
VBOOT
GND
IN_LO
L1
Out+
+
C4
C3
Vcc
IN_HI DRV_HI
NCP1395
D1
Lf
Out−
Bridge
D2
GND DRV_LO
C6
Q2
NCP5109
GND
GND
GND
R1
D3
GND
U2
Figure 1. Typical Application Resonant Converter (LLC type)
Vbulk
+
C1
C5
D4
GND
Q1
Vcc
C3
GND
T1
Vcc
U1
VBOOT
D1
C4
L1
Out+
+
C3
IN_HI DRV_HI
MC34025
IN_LO
Bridge
Out−
D2
GND DRV_LO
C6
NCP5109
GND
Q2
GND
GND
R1
D3
GND
U2
Figure 2. Typical Application Half Bridge Converter
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2
NCP5109A, NCP5109B
VCC
VCC
VBOOT
UV
DETECT
IN_HI
PULSE
TRIGGER
S Q
R Q
LEVEL
SHIFTER
GND
GND
UV
DETECT
DRV_HI
BRIDGE
VCC
IN_LO
DRV_LO
DELAY
GND
GND
GND
GND
GND
Figure 3. Detailed Block Diagram: Version A
VCC
VCC
VBOOT
UV
DETECT
IN_HI
PULSE
TRIGGER
CROSS
CONDUCTION
PREVENTION
GND
GND
IN_LO
S Q
R Q
LEVEL
SHIFTER
UV
DETECT
DRV_HI
BRIDGE
VCC
DRV_LO
DELAY
GND
GND
GND
Figure 4. Detailed Block Diagram: Version B
PIN DESCRIPTION
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Pin Name
Description
IN_HI
Logic Input for High Side Driver Output in Phase
IN_LO
Logic Input for Low Side Driver Output in Phase
GND
Ground
DRV_LO
Low Side Gate Drive Output
VCC
Low Side and Main Power Supply
VBOOT
Bootstrap Power Supply
DRV_HI
High Side Gate Drive Output
BRIDGE
Bootstrap Return or High Side Floating Supply Return
NC
Removed for creepage distance (DFN package only)
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3
NCP5109A, NCP5109B
MAXIMUM RATINGS
Rating
VCC
VCC_transient
Symbol
Main power supply voltage
Main transient power supply voltage:
IVCC_max = 5 mA during 10 ms
VBRIDGE
VHV: High Voltage BRIDGE pin
VBRIDGE
Allowable Negative Bridge Pin Voltage for IN_LO Signal Propagation to DRV_LO
(see characterization curves for detailed results)
Value
Unit
−0.3 to 20
V
23
V
−1 to 200
V
−10
V
VBOOT−VBRIDGE
VHV: Floating supply voltage
−0.3 to 20
V
VDRV_HI
VHV: High side output voltage
VBRIDGE − 0.3 to
VBOOT + 0.3
V
VDRV_LO
Low side output voltage
−0.3 to VCC + 0.3
V
50
V/ns
−1.0 to VCC + 0.3
V
2
kV
200
V
dVBRIDGE/dt
VIN_XX
Allowable output slew rate
Inputs IN_HI, IN_LO
ESD Capability:
− HBM model (all pins except pins 6−7−8 in 8 pins
package or 11−12−13 in 14 pins package)
− Machine model (all pins except pins 6−7−8 in 8 pins
package or 11−12−13 in 14 pins package)
Latch up capability per JEDEC JESD78
RqJA
Power dissipation and Thermal characteristics
SO−8: Thermal Resistance, Junction−to−Air
DFN10 3x3: Thermal Resistance, Junction−to−Ambient 1 Oz Cu
DFN10 3x3: 50 mm2 Printed Circuit Copper Clad
TST
Storage Temperature Range
TJ_max
Maximum Operating Junction Temperature
°C/W
178
172
−55 to +150
°C
+150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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4
NCP5109A, NCP5109B
ELECTRICAL CHARACTERISTIC (VCC = Vboot = 15 V, VGND = Vbridge, −40°C < TJ < 125°C, Outputs loaded with 1 nF)
TJ −40°C to 125°C
Symbol
Min
Typ
Max
Units
Output high short circuit pulsed current VDRV = 0 V, PW v 10 ms (Note 1)
IDRVsource
−
250
−
mA
Output low short circuit pulsed current VDRV = VCC, PW v 10 ms (Note 1)
Rating
OUTPUT SECTION
IDRVsink
−
500
−
mA
Output resistor (Typical value @ 25°C) Source
ROH
−
30
60
W
Output resistor (Typical value @ 25°C) Sink
ROL
−
10
20
W
High level output voltage, VBIAS−VDRV_XX @ IDRV_XX = 20 mA
VDRV_H
−
0.7
1.6
V
Low level output voltage VDRV_XX @ IDRV_XX = 20 mA
VDRV_L
−
0.2
0.6
V
Turn−on propagation delay (Vbridge = 0 V)
tON
−
100
170
ns
Turn−off propagation delay (Vbridge = 0 V or 50 V) (Note 2)
tOFF
−
100
170
ns
Output voltage rise time (from 10% to 90% @ VCC = 15 V) with 1 nF load
tr
−
85
160
ns
Output voltage fall time (from 90% to 10% @VCC = 15 V) with 1 nF load
tf
−
35
75
ns
Propagation delay matching between the High side and the Low side @ 25°C (Note 3)
Dt
−
20
35
ns
Internal fixed dead time (only valid for B version) (Note 4)
DT
65
100
190
ns
tPW1
−
−
50
ns
tPW2
20
15
−
−
−
−
ns
Low level input voltage threshold
VIN
−
−
0.8
V
Input pull−down resistor (VIN < 0.5 V)
RIN
−
200
−
kW
High level input voltage threshold
VIN
2.3
−
−
V
Logic “1” input bias current @ VIN_XX = 5 V @ 25°C
IIN+
−
5
25
mA
Logic “0” input bias current @ VIN_XX = 0 V @ 25°C
IIN−
−
−
2.0
mA
DYNAMIC OUTPUT SECTION
Minimum input width that changes the output
Maximum input width that does not change the output
SOIC−8
DFN10
INPUT SECTION
SUPPLY SECTION
VCC UV Start−up voltage threshold
VCC_stup
8.0
8.9
9.9
V
VCC_shtdwn
7.3
8.2
9.1
V
VCC_hyst
0.3
0.7
−
V
Vboot_stup
8.0
8.9
9.9
V
Vboot_shtdwn
7.3
8.2
9.1
V
Vboot_hyst
0.3
0.7
−
V
IHV_LEAK
−
5
40
mA
Consumption in active mode (VCC = Vboot, fsw = 100 kHz and 1 nF load on both driver
outputs)
ICC1
−
4
5
mA
Consumption in inhibition mode (VCC = Vboot)
ICC2
−
250
400
mA
VCC current consumption in inhibition mode
ICC3
−
200
−
mA
Vboot current consumption in inhibition mode
ICC4
−
50
−
mA
VCC UV Shut−down voltage threshold
Hysteresis on VCC
Vboot Start−up voltage threshold reference to bridge pin
(Vboot_stup = Vboot − Vbridge)
Vboot UV Shut−down voltage threshold
Hysteresis on Vboot
Leakage current on high voltage pins to GND
(VBOOT = VBRIDGE = DRV_HI = 200 V)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Parameter guaranteed by design.
2. Turn−off propagation delay @ Vbridge = 200 V is guaranteed by design.
3. See characterization curve for Dt parameters variation on the full range temperature.
4. Version B integrates a dead time in order to prevent any cross conduction between DRV_HI and DRV_LO. See timing diagram of Figure 10.
5. Timing diagram definition see: Figure 7, Figure 8 and Figure 9.
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5
NCP5109A, NCP5109B
IN_HI
IN_LO
DRV_HI
DRV_LO
Figure 5. Input/Output Timing Diagram (A Version)
IN_HI
IN_LO
DRV_HI
DRV_LO
Figure 6. Input/Output Timing Diagram (B Version)
IN_HI
(IN_LO)
ton
50%
50%
tr
90%
DRV_HI
(DRV_LO)
tf
toff
90%
10%
10%
Figure 7. Propagation Delay and Rise / Fall Time Definition
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6
NCP5109A, NCP5109B
IN_LO
&
IN_HI
50%
50%
ton_HI
toff_HI
90%
Delta_t
DRV_HI
10%
ton_LO
Delta_t
90%
toff_LO
DRV_LO
Matching Delay 1 = ton_HI − ton_LO
Matching Delay 2 = toff_LO − toff_HI
10%
Figure 8. Matching Propagation Delay (A Version)
50%
IN_HI
50%
toff_HI
ton_HI
90%
DRV_HI
10%
Matching Delay1=ton_HI−ton_LO
Matching Delay2=toff_HI−toff_LO
IN_LO
50%
50%
toff_LO
ton_LO
90%
DRV_LO
10%
Figure 9. Matching Propagation Delay (B Version)
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7
NCP5109A, NCP5109B
IN_HI
IN_LO
DRV_HI
DRV_LO
Internal Deadtime
Internal Deadtime
Figure 10. Input/Output Cross Conduction Output Protection Timing Diagram (B Version)
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8
NCP5109A, NCP5109B
CHARACTERIZATION CURVES
140
120
TON, PROPAGATION DELAY (ns)
TON, PROPAGATION DELAY (ns)
140
TON High Side
100
80
60
TON Low Side
40
20
0
10
12
14
16
VCC, VOLTAGE (V)
18
TON Low Side
120
100
80
60
TON High Side
40
20
0
−40
20
Figure 11. Turn ON Propagation Delay vs.
Supply Voltage (VCC = VBOOT)
20
40
60
80
TEMPERATURE (°C)
100
120
140
TOFF, PROPAGATION DELAY (ns)
TOFF, PROPAGATION DELAY (ns)
0
Figure 12. Turn ON Propagation Delay vs.
Temperature
140
120
TOFF Low Side
100
80
60
TOFF High Side
40
20
0
10
12
14
16
VCC, VOLTAGE (V)
18
120
TOFF Low Side
100
80
TOFF High Side
60
40
20
0
−40
20
Figure 13. Turn OFF Propagation Delay vs.
Supply Voltage (VCC = VBOOT)
−20
0
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 14. Turn OFF Propagation Delay vs.
Temperature
160
TOFF PROPAGATION DELAY (ns)
140
TON, PROPAGATION DELAY (ns)
−20
120
100
80
60
40
20
0
140
120
100
80
60
40
20
0
0
10
20
30
40
0
50
10
20
30
40
BRIDGE PIN VOLTAGE (V)
BRIDGE PIN VOLTAGE (V)
Figure 15. High Side Turn ON Propagation
Delay vs. VBRIDGE Voltage
Figure 16. High Side Turn OFF Propagation
Delay vs. VBRIDGE Voltage
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9
50
NCP5109A, NCP5109B
CHARACTERIZATION CURVES
140
140
120
TON, RISETIME (ns)
160
TON, RISETIME (ns)
120
tr High Side
100
80
60
40
tr Low Side
12
14
16
VCC, VOLTAGE (V)
80
60
18
0
−40
20
70
60
60
TOFF, FALLTIME (ns)
TOFF, FALLTIME (ns)
70
tf Low Side
40
30
20
18
100
120
tf High Side
30
20
0
−40
20
Figure 19. Turn OFF Falltime vs. Supply
Voltage (VCC = VBOOT)
tf Low Side
−20
0
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 20. Turn OFF Falltime vs. Temperature
20
200
180
160
15
DEAD TIME (ns)
PROPAGATION DELAY MATCHING (ns)
20
40
60
80
TEMPERATURE (°C)
40
10
10
14
16
VCC, VOLTAGE (V)
0
50
tf High Side
12
−20
Figure 18. Turn ON Risetime vs. Temperature
80
0
10
tr High Side
40
Figure 17. Turn ON Risetime vs. Supply
Voltage (VCC = VBOOT)
50
tr Low Side
20
20
0
10
100
10
5
140
120
100
80
60
40
20
0
−40
−20
0
20
40
60
80
100
0
−40
120
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Propagation Delay Matching
Between High Side and Low Side Driver vs.
Temperature
Figure 22. Dead Time vs. Temperature
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10
120
NCP5109A, NCP5109B
1.4
1.4
1.2
1.2
LOW LEVEL INPUT VOLTAGE
THRESHOLD (V)
LOW LEVEL INPUT VOLTAGE THRESHOLD (V)
CHARACTERIZATION CURVES
1
0.8
0.6
0.4
0.2
0
10
12
14
16
18
0.8
0.6
0.4
0.2
0.0
−40
20
VCC, VOLTAGE (V)
20
40
60
TEMPERATURE (°C)
Figure 23. Low Level Input Voltage Threshold
vs. Supply Voltage (VCC = VBOOT)
Figure 24. Low Level Input Voltage Threshold
vs. Temperature
2.5
2
1.5
1
0.5
0
10
0
80
100
120
12
14
16
VCC, VOLTAGE (V)
18
2.0
1.5
1.0
0.5
0.0
−40
20
Figure 25. High Level Input Voltage Threshold
vs. Supply Voltage (VCC = VBOOT)
−20
0
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 26. High Level Input Voltage Threshold
vs. Temperature
6
LOGIC “0” INPUT CURRENT (mA)
4
LOGIC “0” INPUT CURRENT (mA)
−20
2.5
HIGH LEVEL INPUT VOLTAGE
THRESHOLD (V)
HIGH LEVEL INPUT VOLTAGE
THRESHOLD (V)
1.0
3.5
3
2.5
2
1.5
1
0.5
0
10
12
14
16
VCC, VOLTAGE (V)
18
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
−40
20
−20
0
20
40
60
TEMPERATURE (°C)
80
100
Figure 28. Logic “0” Input Current vs.
Temperature
Figure 27. Logic “0” Input Current vs. Supply
Voltage (VCC = VBOOT)
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11
120
NCP5109A, NCP5109B
CHARACTERIZATION CURVES
10
LOGIC “1” INPUT CURRENT (mA)
LOGIC “1” INPUT CURRENT (mA)
8
7
6
5
4
3
2
1
0
10
12
14
16
VCC, VOLTAGE (V)
18
8
6
4
2
0
−40
20
20
40
60
80
100
120
Figure 30. Logic “1” Input Current vs.
Temperature
1.0
LOW LEVEL OUTPUT VOLTAGE (V)
1
LOW LEVEL OUTPUT VOLTAGE
THRESHOLD (V)
0
TEMPERATURE (°C)
Figure 29. Logic “1” Input Current vs. Supply
Voltage (VCC = VBOOT)
0.8
0.6
0.4
0.2
0
10
12
14
16
VCC, VOLTAGE (V)
18
20
0.8
0.6
0.4
0.2
0.0
−40
Figure 31. Low Level Output Voltage vs.
Supply Voltage (VCC = VBOOT)
0
20
40
60
80
TEMPERATURE (°C)
100
120
1.6
HIGH LEVEL OUTPUT VOLTAGE (V)
1.2
0.8
0.4
0
10
−20
Figure 32. Low Level Output Voltage vs.
Temperature
1.6
HIGH LEVEL OUTPUT VOLTAGE
THRESHOLD (V)
−20
12
14
16
VCC, VOLTAGE (V)
18
20
1.2
0.8
0.4
0.0
−40
−20
0
20
40
60
TEMPERATURE (°C)
80
100
Figure 34. High Level Output Voltage vs.
Temperature
Figure 33. High Level Output Voltage vs.
Supply Voltage (VCC = VBOOT)
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12
120
NCP5109A, NCP5109B
CHARACTERIZATION CURVES
400
350
OUTPUT SOURCE CURRENT (mA)
OUTPUT SOURCE CURRENT (mA)
400
Isrc High Side
300
250
Isrc Low Side
200
150
100
50
0
10
12
14
16
VCC, VOLTAGE (V)
18
350
300
250
200
150
Isrc Low Side
100
50
0
−40
20
Isrc High Side
−20
0
20
40
100
120
Figure 36. Output Source Current vs.
Temperature
600
600
Isink High Side
OUTPUT SINK CURRENT (mA)
Isink High Side
500
400
Isink Low Side
300
200
100
12
14
16
18
500
400
300
200
100
0
−40
20
Isink Low Side
−20
VCC, VOLTAGE (V)
20
40
60
80
100
Figure 38. Output Sink Current vs.
Temperature
0.2
0.16
0.12
0.08
0.04
0
0
0
TEMPERATURE (°C)
Figure 37. Output Sink Current vs. Supply
Voltage (VCC = VBOOT)
HIGH SIDE LEAKAGE CURRENT ON
HV PINS TO GND (mA)
OUTPUT SINK CURRENT (mA)
80
TEMPERATURE (°C)
Figure 35. Output Source Current vs. Supply
Voltage (VCC = VBOOT)
0
10
60
100
200
HV PINS VOLTAGE (V)
Figure 39. Leakage Current on High Voltage
Pins (200 V) to Ground vs. VBRIDGE Voltage
(VBRIGDE = VBOOT = VDRV_HI)
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13
120
NCP5109A, NCP5109B
CHARACTERIZATION CURVES
100
VBOOT CURRENT SUPPLY (mA)
VBOOT SUPPLY CURRENT (mA)
100
80
60
40
20
0
0
4
8
12
16
80
60
40
20
0
−40
20
−20
0
Figure 40. VBOOT Supply Current vs. Bootstrap
Supply Voltage
60
80
100
120
400
200
VCC CURRENT SUPPLY (mA)
VCC SUPPLY CURRENT (mA)
40
Figure 41. VBOOT Supply Current vs.
Temperature
240
160
120
80
40
0
0
4
8
12
16
300
200
100
0
−40
20
−20
0
VCC, VOLTAGE (V)
9.8
8.8
UVLO SHUTDOWN VOLTAGE (V)
9.0
VCC UVLO Startup
9.4
9.2
9.0
8.8
8.6
8.4
VBOOT UVLO Startup
8.2
8.0
−40
−20
0
20
40
60
40
60
80
100
120
Figure 43. VCC Supply Current vs. Temperature
10.0
9.6
20
TEMPERATURE (°C)
Figure 42. VCC Supply Current vs. VCC Supply
Voltage
UVLO STARTUP VOLTAGE (V)
20
TEMPERATURE (°C)
VBOOT, VOLTAGE (V)
80
100
120
VCC UVLO Shutdown
8.6
8.4
8.2
8.0
VBOOT UVLO Shutdown
7.8
7.6
7.4
7.2
7.0
−40
TEMPERATURE (°C)
−20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 44. UVLO Startup Voltage vs.
Temperature
Figure 45. UVLO Shutdown Voltage vs.
Temperature
www.onsemi.com
14
120
NCP5109A, NCP5109B
CHARACTERIZATION CURVES
40
ICC+ IBOOT CURRENT SUPPLY (mA)
ICC+ IBOOT CURRENT SUPPLY (mA)
25
CLOAD = 1 nF/Q = 15 nC
20
15
10
5
RGATE = 0 R to 22 R
0
0
100
200
300
400
500
CLOAD = 2.2 nF/Q = 33 nC
35
30
25
RGATE = 10 R
20
RGATE = 22 R
15
10
5
0
0
600
100
SWITCHING FREQUENCY (kHz)
Figure 46. ICC1 Consumption vs. Switching
Frequency with 15 nC Load on Each Driver @
VCC = 15 V
CLOAD = 3.3 nF/Q = 50 nC
60
ICC+ IBOOT CURRENT SUPPLY (mA)
ICC+ IBOOT CURRENT SUPPLY (mA)
600
120
RGATE = 0 R
50
40
RGATE = 10 R
30
RGATE = 22 R
20
10
0
0
CLOAD = 6.6 nF/Q = 100 nC
RGATE = 0 R
100
80
RGATE = 10 R
60
40
RGATE = 22 R
20
0
100
200
300
400
500
600
0
SWITCHING FREQUENCY (kHz)
Figure 48. ICC1 Consumption vs. Switching
Frequency with 50 nC Load on Each Driver @
VCC = 15 V
100
200
300
400
500
SWITCHING FREQUENCY (kHz)
600
Figure 49. ICC1 Consumption vs. Switching
Frequency with 100 nC Load on Each Driver @
VCC = 15 V
0
−5
NEGATIVE PULSE VOLTAGE (V)
0
NEGATIVE PULSE VOLTAGE (V)
200
300
400
500
SWITCHING FREQUENCY (kHz)
Figure 47. ICC1 Consumption vs. Switching
Frequency with 33 nC Load on Each Driver @
VCC = 15 V
70
−40°C
−10
25°C
−15
125°C
−20
−25
−30
−35
RGATE = 0 R
0
100
200
300
400
500
NEGATIVE PULSE DURATION (ns)
−5
−10
25°C
−15
−20
125°C
−25
−30
−35
600
−40°C
0
Figure 50. NCP5109A, Negative Voltage Safe
Operating Area on the Bridge Pin
100
200
300
400
500
NEGATIVE PULSE DURATION (ns)
Figure 51. NCP5109B, Negative Voltage Safe
Operating Area on the Bridge Pin
www.onsemi.com
15
600
NCP5109A, NCP5109B
APPLICATION INFORMATION
Negative Voltage Safe Operating Area
Summary:
• If the negative pulse characteristic (negative voltage
level & pulse width) is above the curves the driver
runs in safe operating area.
• If the negative pulse characteristic (negative voltage
level & pulse width) is below one or all curves the
driver will NOT run in safe operating area.
Note, each curve of the Figure 50 (or 51) represents the
negative voltage and width level where the driver starts to
fail at the corresponding die temperature.
If in the application the bridge pin is too close of the safe
operating limit, it is possible to limit the negative voltage
to the bridge pin by inserting one resistor and one diode as
follows:
When the driver is used in a half bridge configuration, it
is possible to see negative voltage appearing on the bridge
pin (pin 6) during the power MOSFETs transitions. When
the high−side MOSFET is switched off, the body diode of
the low−side MOSFET starts to conduct. The negative
voltage applied to the bridge pin thus corresponds to the
forward voltage of the body diode. However, as pcb copper
tracks and wire bonding introduce stray elements
(inductance and capacitor), the maximum negative voltage
of the bridge pin will combine the forward voltage and the
oscillations created by the parasitic elements. As any
CMOS device, the deep negative voltage of a selected pin
can inject carriers into the substrate, leading to an erratic
behavior of the concerned component. ON Semiconductor
provides characterization data of its half−bridge driver to
show the maximum negative voltage the driver can safely
operate with. To prevent the negative injection, it is the
designer duty to verify that the amount of negative voltage
pertinent to his/her application does not exceed the
characterization curve we provide, including some safety
margin.
In order to estimate the maximum negative voltage
accepted by the driver, this parameter has been
characterized over full the temperature range of the
component. A test fixture has been developed in which we
purposely negatively bias the bridge pin during the
freewheel period of a buck converter. When the upper gate
voltage shows signs of an erratic behavior, we consider the
limit has been reached.
Figure 50 (or 51), illustrates the negative voltage safe
operating area. Its interpretation is as follows: assume a
negative 10 V pulse featuring a 100 ns width is applied on
the bridge pin, the driver will work correctly over the whole
die temperature range. Should the pulse swing to −20 V,
keeping the same width of 100 ns, the driver will not work
properly or will be damaged for temperatures below
125°C.
Vcc
D2
Vbulk
MUR160
1
2
IN_Hi
3
IN_LO
0
4
U1
NCP5109A
8
VCC
VBOOT
IN_HI
DRV_HI
IN_LO
BRIDGE
GND
DRV_LO
C1
100n
M1
7
R1
6
5
10R
M2
D1
MUR160
0
Figure 52. R1 and D1 Improves the Robustness of the
Driver
R1 and D1 should be placed as close as possible of the
driver. D1 should be connected directly between the bridge
pin (pin 6) and the ground pin (pin 4). By this way the
negative voltage applied to the bridge pin will be limited
by D1 and R1 and will prevent any wrong behavior.
ORDERING INFORMATION
Package
Shipping†
NCP5109ADR2G
SOIC−8 (Pb−Free)
2500 / Tape & Reel
NCP5109BDR2G
SOIC−8 (Pb−Free)
2500 / Tape & Reel
NCP5109AMNTWG
DFN10 (Pb−Free)
3000 / Tape & Reel
NCP5109BMNTWG
DFN10 (Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
16
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN10 3x3, 0.5P
CASE 506DH
ISSUE O
SCALE 2:1
D
2X
0.10 C
2X
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
0.10 C
ALTERNATE A−2
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
ÉÉÉ
ÇÇÇ
ÇÇÇ
A1
DETAIL B
A3
ALTERNATE B−1
A
10X
L
L1
ALTERNATE A−1
E
TOP VIEW
0.10 C
0.05 C
SIDE VIEW
NOTE 4
(A3)
A1
C
10X
MOLD CMPD
ALTERNATE B−2
DETAIL B
SEATING
PLANE
0.10 C A B
1
ÉÉ
ÇÇ
EXPOSED Cu
ALTERNATE
CONSTRUCTIONS
A
A1
D2
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE
TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS
THE TERMINALS.
5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG
SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30
MICRONS ONTO BOTTOM SURFACE OF TERMINAL.
6. FOR DEVICE OPN CONTAINING W OPTION, DETAIL A ALTERNATE CONSTRUCTION A−2 AND DETAIL B ALTERNATE CONSTRUCTION B−2 ARE NOT APPLICABLE.
A
B
L
PIN ONE
REFERENCE
DATE 24 MAY 2016
L
DETAIL B
XXXXX
XXXXX
ALYWG
G
0.10 C A B
E2
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
E3
K
10
6
e
10X
b
0.10 C A B
0.05 C
BOTTOM VIEW
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
3.00 BSC
2.40
2.60
3.00 BSC
1.50
1.70
0.10 BSC
0.50 BSC
0.30
−−−
0.35
0.45
0.00
0.05
GENERIC
MARKING DIAGRAM*
WETTABLE FLANK
CONSTRUCTION
5
DIM
A
A1
A3
b
D
D2
E
E2
E3
e
K
L
L1
NOTE 3
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
10X
0.58 may or may not be present.
RECOMMENDED
SOLDERING FOOTPRINT*
2.66
PACKAGE
OUTLINE
0.94
3.30
1.80
1
0.50
PITCH
10X
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON12036G
DFN10 3X3, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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